OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example
    from Rev 47 to Rev 48
    ↔ Reverse comparison
  •

Rev 47 → Rev 48

/bit_manipulation/main.c
75,8 → 75,8
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// intro
neorv32_uart_printf("NEORV32 Bit Manipulation (B.Zbb) Extension Test\n\n");
/blink_led/main.c
73,8 → 73,8
**************************************************************************/
int main() {
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check if GPIO unit is implemented at all
if (neorv32_gpio_available() == 0) {
/coremark/core_portme.c
151,7 → 151,7
/* NEORV32-specific */
neorv32_cpu_dint(); // no interrupt, thanks
neorv32_rte_setup(); // capture all exceptions and give debug information
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); // init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00); // init UART at default baud rate, no parity bits
 
 
// Disable coremark compilation by default
/cpu_test/main.c
104,12 → 104,14
**************************************************************************/
int main() {
 
volatile uint64_t temp64;
register uint32_t tmp_a, tmp_b;
volatile uint32_t dummy_dst __attribute__((unused));
uint8_t id;
 
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// Disable cpu_test compilation by default
#ifndef RUN_CPUTEST
141,13 → 143,12
neorv32_cpu_set_minstret(0);
neorv32_cpu_set_mcycle(0);
 
// enable performance counter auto increment
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0);
neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable performance counter auto increment (ALL counters)
neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code to standard counters only
 
neorv32_mtime_set_time(0);
// set CMP of machine system timer MTIME to max to prevent an IRQ
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFUL;
uint64_t mtime_cmp_max = 0xffffffffffffffffULL;
neorv32_mtime_set_timecmp(mtime_cmp_max);
 
 
171,28 → 172,10
neorv32_rte_setup(); // this will install a full-detailed debug handler for all traps
 
int install_err = 0;
// here we are overriding the default debug handlers
install_err += neorv32_rte_exception_install(RTE_TRAP_I_MISALIGNED, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_I_ACCESS, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_I_ILLEGAL, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_BREAKPOINT, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_L_MISALIGNED, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_L_ACCESS, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_S_MISALIGNED, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_S_ACCESS, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_UENV_CALL, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_MENV_CALL, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_MTI, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_MSI, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_MEI, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_0, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_1, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_2, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_3, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_4, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_5, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_6, global_trap_handler);
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_7, global_trap_handler);
// initialize ALL provided trap handler (overriding the default debug handlers)
for (id=0; id<NEORV32_RTE_NUM_TRAPS; id++) {
install_err += neorv32_rte_exception_install(id, global_trap_handler);
}
 
if (install_err) {
neorv32_uart_printf("RTE install error (%i)!\n", install_err);
200,23 → 183,11
}
 
// enable interrupt sources
install_err = neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_MEIE); // machine external interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); // fast interrupt channel 0
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E); // fast interrupt channel 1
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E); // fast interrupt channel 2
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); // fast interrupt channel 3
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E); // fast interrupt channel 4
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E); // fast interrupt channel 5
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E); // fast interrupt channel 6
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E); // fast interrupt channel 7
neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt
neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt
neorv32_cpu_irq_enable(CSR_MIE_MEIE); // machine external interrupt
// enable FAST IRQ sources only where actually needed
 
if (install_err) {
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err);
return 0;
}
 
// test intro
neorv32_uart_printf("\nStarting tests...\n\n");
 
233,7 → 204,7
cnt_test++;
 
// get current cycle counter
tmp_a = neorv32_cpu_get_cycle();
temp64 = neorv32_cpu_get_cycle();
 
// wait some time to have a nice increment
asm volatile ("nop");
240,8 → 211,7
asm volatile ("nop");
 
// make sure cycle counter has incremented and there was no exception during access
if ((neorv32_cpu_get_cycle() > tmp_a) &&
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
if ((neorv32_cpu_get_cycle() > temp64) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
test_ok();
}
else {
258,7 → 228,7
cnt_test++;
 
// get current instruction counter
tmp_a = neorv32_cpu_get_instret();
temp64 = neorv32_cpu_get_instret();
 
// wait some time to have a nice increment
asm volatile ("nop");
265,7 → 235,7
asm volatile ("nop");
 
// make sure instruction counter has incremented and there was no exception during access
if ((neorv32_cpu_get_instret() > tmp_a) &&
if ((neorv32_cpu_get_instret() > temp64) &&
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
test_ok();
}
958,11 → 928,14
// Fast interrupt channel 0 (WDT)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ0 (fast interrupt 0) test (via WDT): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ0 test (via WDT): ", cnt_test);
 
if (neorv32_wdt_available()) {
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E);
 
// configure WDT
neorv32_wdt_setup(CLK_PRSC_4096, 0, 1); // highest clock prescaler, trigger IRQ on timeout, lock access
WDT_CT = 0; // try to deactivate WDT (should fail as access is loced)
981,6 → 954,9
 
// no more WDT interrupts
neorv32_wdt_disable();
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ0E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
988,60 → 964,31
 
 
// ----------------------------------------------------------
// Fast interrupt channel 1 (GPIO)
// Fast interrupt channel 1 (reserved)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ1 (fast interrupt 1) test (via GPIO): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ1 test (reserved): ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (neorv32_gpio_available()) {
cnt_test++;
 
// clear output port
neorv32_gpio_port_set(0);
// ----------------------------------------------------------
// Fast interrupt channel 2 (CFS)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ2 test (via CFS): ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
// configure GPIO.in(31) for pin-change IRQ
neorv32_gpio_pin_change_config(0x80000000);
 
// trigger pin-change IRQ by setting GPIO.out(31)
// the testbench connects GPIO.out => GPIO.in
neorv32_gpio_pin_set(31);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_1) {
test_ok();
}
else {
test_fail();
}
 
// disable GPIO pin-change IRQ
neorv32_gpio_pin_change_config(0);
 
// clear output port
neorv32_gpio_port_set(0);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
}
else {
neorv32_uart_printf("skipped (on real HW)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 2 (UART)
// Fast interrupt channel 3 (UART.RX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ2 (fast interrupt 2) test (via UART): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ3 test (via UART.RX): ", cnt_test);
 
if (neorv32_uart_available()) {
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E);
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
1051,10 → 998,8
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
 
// enable UART TX done IRQ
UART_CT |= (1 << UART_CT_TX_IRQ);
 
// trigger UART TX IRQ
// trigger UART RX IRQ
// the default test bench connects UART.TXD_O to UART_RXD_I
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active
 
// wait for UART to finish transmitting
1064,37 → 1009,82
asm volatile("nop");
asm volatile("nop");
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
// re-enable UART sim_mode if it was enabled and disable UART TX done IRQ
// re-enable UART sim_mode if it was enabled
UART_CT = uart_ct_backup;
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_2) {
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (on real HW)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 4 (UART.TX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ4 test (via UART.TX): ", cnt_test);
 
cnt_test++;
 
// UART TX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E);
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
// backup current UART configuration
volatile uint32_t uart_ct_backup = UART_CT;
 
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
 
// trigger UART TX IRQ
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// re-enable UART sim_mode if it was enabled
UART_CT = uart_ct_backup;
 
neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) {
test_ok();
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
test_fail();
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 3 (SPI)
// Fast interrupt channel 5 (SPI)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ3 (fast interrupt 3) test (via SPI): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ5 test (via SPI): ", cnt_test);
 
if (neorv32_spi_available()) {
cnt_test++;
 
// configure SPI, enable transfer-done IRQ
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 1);
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E);
 
// configure SPI
neorv32_spi_setup(CLK_PRSC_2, 0, 0);
 
// trigger SPI IRQ
neorv32_spi_trans(0);
while(neorv32_spi_busy()); // wait for current transfer to finish
1103,7 → 1093,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) {
test_ok();
}
else {
1112,6 → 1102,9
 
// disable SPI
neorv32_spi_disable();
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1119,17 → 1112,19
 
 
// ----------------------------------------------------------
// Fast interrupt channel 3 (TWI)
// Fast interrupt channel 6 (TWI)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ3 (fast interrupt 3) test (via TWI): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ6 test (via TWI): ", cnt_test);
 
if (neorv32_twi_available()) {
cnt_test++;
 
// configure TWI, fastest clock, transfer-done IRQ enable, disable peripheral clock stretching
neorv32_twi_setup(CLK_PRSC_2, 1, 0);
// configure TWI, fastest clock, no peripheral clock stretching
neorv32_twi_setup(CLK_PRSC_2, 0);
 
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
 
// trigger TWI IRQ
neorv32_twi_generate_start();
neorv32_twi_trans(0);
1139,7 → 1134,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) {
test_ok();
}
else {
1148,6 → 1143,7
 
// disable TWI
neorv32_twi_disable();
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1155,38 → 1151,105
 
 
// ----------------------------------------------------------
// Fast interrupt channel 4..7 (SoC fast IRQ)
// Fast interrupt channel 7 (GPIO)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ4..7 (SoC fast interrupt 0..3, via testbench) test: ", cnt_test);
neorv32_uart_printf("[%i] FIRQ7 test (via GPIO): ", cnt_test);
 
cnt_test++;
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (neorv32_gpio_available()) {
cnt_test++;
 
// trigger all SoC Fast interrupts at once
neorv32_cpu_dint(); // do not fire yet!
sim_irq_trigger((1 << CSR_MIE_FIRQ4E) | (1 << CSR_MIE_FIRQ5E) | (1 << CSR_MIE_FIRQ6E) | (1 << CSR_MIE_FIRQ7E));
// clear output port
neorv32_gpio_port_set(0);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
 
// make sure all SoC FIRQs have been triggered
tmp_a = (1 << CSR_MIP_FIRQ4P) | (1 << CSR_MIP_FIRQ5P) | (1 << CSR_MIP_FIRQ6P) | (1 << CSR_MIP_FIRQ7P);
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) {
neorv32_cpu_eint(); // allow IRQs to fire again
asm volatile ("nop");
asm volatile ("nop"); // irq should kick in HERE
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) { // make sure FIRQ7 was last IRQ to be handled
test_ok();
// configure GPIO.in(31) for pin-change IRQ
neorv32_gpio_pin_change_config(0x80000000);
 
// trigger pin-change IRQ by setting GPIO.out(31)
// the testbench connects GPIO.out => GPIO.in
neorv32_gpio_pin_set(31);
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) {
test_ok();
}
else {
test_fail();
}
 
// disable GPIO pin-change IRQ
neorv32_gpio_pin_change_config(0);
 
// clear output port
neorv32_gpio_port_set(0);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
}
else {
test_fail();
neorv32_uart_printf("skipped (not implemented)\n");
}
}
else {
test_fail();
neorv32_uart_printf("skipped (on real HW)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 8..15 (SoC fast IRQ 0..7)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ8..15 (SoC fast IRQ 0..7; via testbench) test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
 
cnt_test++;
 
// enable SOC FIRQs
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) {
neorv32_cpu_irq_enable(id);
}
 
// trigger all SoC Fast interrupts at once
neorv32_cpu_dint(); // do not fire yet!
sim_irq_trigger((1 << CSR_MIE_FIRQ8E) | (1 << CSR_MIE_FIRQ9E) | (1 << CSR_MIE_FIRQ10E) | (1 << CSR_MIE_FIRQ11E) |
(1 << CSR_MIE_FIRQ12E) | (1 << CSR_MIE_FIRQ13E) | (1 << CSR_MIE_FIRQ14E) | (1 << CSR_MIE_FIRQ15E));
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// make sure all SoC FIRQs have been triggered
tmp_a = (1 << CSR_MIP_FIRQ8P) | (1 << CSR_MIP_FIRQ9P) | (1 << CSR_MIP_FIRQ10P) | (1 << CSR_MIP_FIRQ11P) |
(1 << CSR_MIP_FIRQ12P) | (1 << CSR_MIP_FIRQ13P) | (1 << CSR_MIP_FIRQ14P) | (1 << CSR_MIP_FIRQ15P);
 
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) {
neorv32_cpu_eint(); // allow IRQs to fire again
asm volatile ("nop");
asm volatile ("nop"); // irq should kick in HERE
 
tmp_a = neorv32_cpu_csr_read(CSR_MCAUSE);
if ((tmp_a >= TRAP_CODE_FIRQ_8) && (tmp_a <= TRAP_CODE_FIRQ_15)) {
test_ok();
}
else {
test_fail();
}
}
 
// disable SOC FIRQs
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) {
neorv32_cpu_irq_disable(id);
}
}
else {
neorv32_uart_printf("skipped (on real HW)\n");
}
 
neorv32_cpu_eint(); // re-enable IRQs globally
 
 
1291,7 → 1354,7
// check if PMP is implemented
if (neorv32_cpu_pmp_get_num_regions() != 0) {
 
// Test access to protected region
// Create PMP protected region
// ---------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
cnt_test++;
/demo_freeRTOS/main.c
127,8 → 127,8
// clear GPIO.out port
neorv32_gpio_port_set(0);
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
231,8 → 231,8
#include <neorv32.h>
int main() {
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
neorv32_uart_print("ERROR! FreeRTOS has not been compiled. Use >>make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe<< to compile it.\n");
return 0;
}
/demo_gpio_irq/main.c
72,8 → 72,8
// setup run-time environment for interrupts and exceptions
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_pwm/main.c
73,8 → 73,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_trng/main.c
75,8 → 75,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_twi/main.c
83,8 → 83,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
104,8 → 104,8
neorv32_uart_printf("This program allows to create TWI transfers by hand.\n"
"Type 'help' to see the help menu.\n\n");
 
// configure TWI, second slowest clock, no IRQ, no clock-stretching
neorv32_twi_setup(CLK_PRSC_2048, 0, 0);
// configure TWI, second slowest clock, no clock-stretching
neorv32_twi_setup(CLK_PRSC_2048, 0);
 
// no active bus session yet
bus_claimed = 0;
/demo_wdt/main.c
75,8 → 75,8
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/game_of_life/main.c
97,8 → 97,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/hello_world/main.c
65,8 → 65,8
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/hex_viewer/main.c
81,9 → 81,11
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// disable global interrupts
neorv32_cpu_dint();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
229,11 → 231,11
cas_desired = (uint32_t)hexstr_to_uint(terminal_buffer, strlen(terminal_buffer));
 
// try to execute atomic compare-and-swap
if (neorv32_cpu_atomic_cas(mem_address, cas_expected, cas_desired)) {
neorv32_uart_printf("\nAtomic-CAS: Failed!\n");
if (neorv32_cpu_atomic_cas(mem_address, cas_expected, cas_desired) == 0) {
neorv32_uart_printf("\nAtomic-CAS: Successful!\n");
}
else {
neorv32_uart_printf("\nAtomic-CAS: Successful!\n");
neorv32_uart_printf("\nAtomic-CAS: Failed!\n");
}
}
else {

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