OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example
    from Rev 49 to Rev 50
    ↔ Reverse comparison
  •

Rev 49 → Rev 50

/blink_led/main.c
73,7 → 73,7
**************************************************************************/
int main() {
 
// init UART at default baud rate, no parity bits
// init UART (primary UART = UART0; if no id number is specified the primary UART is used) at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
 
// check if GPIO unit is implemented at all
/cpu_test/main.c
108,6 → 108,7
register uint32_t tmp_a, tmp_b;
volatile uint32_t dummy_dst __attribute__((unused));
uint8_t id;
uint32_t is_simulation = 0;
 
 
// init UART at default baud rate, no parity bits
123,6 → 124,14
return 0;
#endif
 
// check if this is a simulation (using primary UART0)
if (UART0_CT & (1 << UART_CT_SIM_MODE)) {
is_simulation = 1;
}
else {
is_simulation = 0;
}
 
neorv32_uart_printf("\n<< CPU/PROCESSOR TEST >>\n");
neorv32_uart_printf("build: "__DATE__" "__TIME__"\n");
 
152,9 → 161,8
neorv32_mtime_set_timecmp(mtime_cmp_max);
 
 
// intro
// fancy intro
// -----------------------------------------------
 
// logo
neorv32_rte_print_logo();
 
388,7 → 396,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] External memory access (@ 0x%x) test: ", cnt_test, (uint32_t)EXT_MEM_BASE);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)) {
cnt_test++;
 
429,12 → 437,12
neorv32_uart_printf("skipped (on real HW)\n");
}
 
 
/*
// ----------------------------------------------------------
// Test FENCE.I instruction (instruction buffer / i-cache clear & reload)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Testing FENCE.I operation: ", cnt_test);
neorv32_uart_printf("[%i] FENCE.I test: ", cnt_test);
 
// check if implemented
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1 << CSR_MZEXT_ZIFENCEI)) {
453,8 → 461,8
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
*/
 
 
// ----------------------------------------------------------
// Illegal CSR access (CSR not implemented)
// ----------------------------------------------------------
601,7 → 609,7
// Unaligned instruction address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ALIGN (instruction alignment) exception test: ", cnt_test);
neorv32_uart_printf("[%i] I_ALIGN (instr. alignment) exception test: ", cnt_test);
 
// skip if C-mode is implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) == 0) {
629,7 → 637,7
// Instruction access fault
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ACC (instruction bus access) exception test: ", cnt_test);
neorv32_uart_printf("[%i] I_ACC (instr. bus access) exception test: ", cnt_test);
cnt_test++;
 
// call unreachable aligned address
647,7 → 655,7
// Illegal instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ILLEG (illegal instruction) exception test: ", cnt_test);
neorv32_uart_printf("[%i] I_ILLEG (illegal instr.) exception test: ", cnt_test);
 
cnt_test++;
 
673,7 → 681,7
// Illegal compressed instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] CI_ILLEG (illegal compressed instruction) exception test: ", cnt_test);
neorv32_uart_printf("[%i] CI_ILLEG (illegal compr. instr.) exception test: ", cnt_test);
 
// skip if C-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) != 0) {
705,7 → 713,7
// Breakpoint instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] BREAK (break instruction) exception test: ", cnt_test);
neorv32_uart_printf("[%i] BREAK (break instr.) exception test: ", cnt_test);
cnt_test++;
 
asm volatile("EBREAK");
722,7 → 730,7
// Unaligned load address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] L_ALIGN (load address alignment) exception test: ", cnt_test);
neorv32_uart_printf("[%i] L_ALIGN (load addr alignment) exception test: ", cnt_test);
cnt_test++;
 
// load from unaligned address
758,7 → 766,7
// Unaligned store address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] S_ALIGN (store address alignment) exception test: ", cnt_test);
neorv32_uart_printf("[%i] S_ALIGN (store addr alignment) exception test: ", cnt_test);
cnt_test++;
 
// store to unaligned address
794,7 → 802,7
// Environment call from M-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] ENVCALL (ecall instruction) from M-mode exception test: ", cnt_test);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from M-mode exception test: ", cnt_test);
cnt_test++;
 
asm volatile("ECALL");
811,7 → 819,7
// Environment call from U-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] ENVCALL (ecall instruction) from U-mode exception test: ", cnt_test);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from U-mode exception test: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
874,7 → 882,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MSI (via testbench) interrupt test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// trigger IRQ
902,7 → 910,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MEI (via testbench) interrupt test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// trigger IRQ
964,45 → 972,38
 
 
// ----------------------------------------------------------
// Fast interrupt channel 1 (reserved)
// Fast interrupt channel 1 (CFS)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ1 test (reserved): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ1 test (via CFS): ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
// ----------------------------------------------------------
// Fast interrupt channel 2 (CFS)
// Fast interrupt channel 2 (UART0.RX)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ2 test (via CFS): ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
// ----------------------------------------------------------
// Fast interrupt channel 3 (UART.RX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ3 test (via UART.RX): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ2 test (via UART0.RX): ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E);
 
// wait for UART to finish transmitting
// wait for UART0 to finish transmitting
while(neorv32_uart_tx_busy());
 
// backup current UART configuration
uint32_t uart_ct_backup = UART_CT;
// backup current UART0 configuration
tmp_a = UART0_CT;
 
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
// disable UART0 sim_mode if it is enabled
UART0_CT &= ~(1 << UART_CT_SIM_MODE);
 
// trigger UART RX IRQ
// the default test bench connects UART.TXD_O to UART_RXD_I
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active
// trigger UART0 RX IRQ
// the default test bench connects UART0.TXD_O to UART0_RXD_I
UART0_DATA = 0; // we need to access the raw HW here, since >UART0_SIM_MODE< might be active
 
// wait for UART to finish transmitting
// wait for UART0 to finish transmitting
while(neorv32_uart_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
1009,13 → 1010,13
asm volatile("nop");
asm volatile("nop");
 
// re-enable UART sim_mode if it was enabled
UART_CT = uart_ct_backup;
// re-enable UART0 sim_mode if it was enabled
UART0_CT = tmp_a;
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ2E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_2) {
test_ok();
}
else {
1028,27 → 1029,27
 
 
// ----------------------------------------------------------
// Fast interrupt channel 4 (UART.TX)
// Fast interrupt channel 3 (UART0.TX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ4 test (via UART.TX): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ3 test (via UART0.TX): ", cnt_test);
 
cnt_test++;
 
// UART TX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E);
// UART0 TX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E);
 
// wait for UART to finish transmitting
// wait for UART0 to finish transmitting
while(neorv32_uart_tx_busy());
 
// backup current UART configuration
volatile uint32_t uart_ct_backup = UART_CT;
// backup current UART0 configuration
tmp_a = UART0_CT;
 
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
// disable UART0 sim_mode if it is enabled
UART0_CT &= ~(1 << UART_CT_SIM_MODE);
 
// trigger UART TX IRQ
UART_DATA = 0; // we need to access the raw HW here, since >DEVNULL_UART_OVERRIDE< might be active
// trigger UART0 TX IRQ
UART0_DATA = 0; // we need to access the raw HW here, since >UART0_SIM_MODE< might be active
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
1058,11 → 1059,11
asm volatile("nop");
 
// re-enable UART sim_mode if it was enabled
UART_CT = uart_ct_backup;
UART0_CT = tmp_a;
 
neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ3E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) {
test_ok();
}
else {
1071,16 → 1072,108
 
 
// ----------------------------------------------------------
// Fast interrupt channel 5 (SPI)
// Fast interrupt channel 4 (UART1.RX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ5 test (via SPI): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ4 test (via UART1.RX): ", cnt_test);
 
if (neorv32_uart1_available()) {
cnt_test++;
 
// UART1 RX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E);
 
// initialize UART1
UART1_CT = 0;
tmp_a = UART0_CT; // copy configuration from UART0
tmp_a &= ~(1 << UART_CT_SIM_MODE); // make sure sim_mode is disabled
UART1_CT = tmp_a;
 
// trigger UART1 RX IRQ
UART1_DATA = 0;
 
// wait for UART1 to finish transmitting
while(neorv32_uart1_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// disable UART1
UART1_CT = 0;
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ4E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_4) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 5 (UART1.TX)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ5 test (via UART1.TX): ", cnt_test);
 
if (neorv32_uart1_available()) {
cnt_test++;
 
// UART1 RX interrupt enable
neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E);
 
// initialize UART1
UART1_CT = 0;
tmp_a = UART0_CT; // copy configuration from UART0
tmp_a &= ~(1 << UART_CT_SIM_MODE); // make sure sim_mode is disabled
UART1_CT = tmp_a;
 
// trigger UART1 TX IRQ
UART1_DATA = 0;
 
// wait for UART1 to finish transmitting
while(neorv32_uart1_tx_busy());
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
asm volatile("nop");
 
// disable UART1
UART1_CT = 0;
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Fast interrupt channel 6 (SPI)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ6 test (via SPI): ", cnt_test);
 
if (neorv32_spi_available()) {
cnt_test++;
 
// enable fast interrupt
neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
 
// configure SPI
neorv32_spi_setup(CLK_PRSC_2, 0, 0);
1093,7 → 1186,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_5) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) {
test_ok();
}
else {
1104,7 → 1197,7
neorv32_spi_disable();
 
// disable fast interrupt
neorv32_cpu_irq_disable(CSR_MIE_FIRQ5E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1112,10 → 1205,10
 
 
// ----------------------------------------------------------
// Fast interrupt channel 6 (TWI)
// Fast interrupt channel 7 (TWI)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ6 test (via TWI): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ7 test (via TWI): ", cnt_test);
 
if (neorv32_twi_available()) {
cnt_test++;
1123,7 → 1216,7
// configure TWI, fastest clock, no peripheral clock stretching
neorv32_twi_setup(CLK_PRSC_2, 0);
 
neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
 
// trigger TWI IRQ
neorv32_twi_generate_start();
1134,7 → 1227,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_6) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) {
test_ok();
}
else {
1143,7 → 1236,7
 
// disable TWI
neorv32_twi_disable();
neorv32_cpu_irq_disable(CSR_MIE_FIRQ6E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1151,12 → 1244,12
 
 
// ----------------------------------------------------------
// Fast interrupt channel 7 (GPIO)
// Fast interrupt channel 8 (GPIO)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ7 test (via GPIO): ", cnt_test);
neorv32_uart_printf("[%i] FIRQ8 test (via GPIO): ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
if (neorv32_gpio_available()) {
cnt_test++;
 
1163,7 → 1256,7
// clear output port
neorv32_gpio_port_set(0);
 
neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E);
neorv32_cpu_irq_enable(CSR_MIE_FIRQ8E);
 
// configure GPIO.in(31) for pin-change IRQ
neorv32_gpio_pin_change_config(0x80000000);
1176,7 → 1269,7
asm volatile("nop");
asm volatile("nop");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) {
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_8) {
test_ok();
}
else {
1188,7 → 1281,7
 
// clear output port
neorv32_gpio_port_set(0);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ7E);
neorv32_cpu_irq_disable(CSR_MIE_FIRQ8E);
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
1200,24 → 1293,30
 
 
// ----------------------------------------------------------
// Fast interrupt channel 8..15 (SoC fast IRQ 0..7)
// Fast interrupt channel 9 (reserved)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ9 test: ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
// ----------------------------------------------------------
// Fast interrupt channel 10..15 (SoC fast IRQ 0..5)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ8..15 (SoC fast IRQ 0..7; via testbench) test: ", cnt_test);
neorv32_uart_printf("[%i] FIRQ10..15 (SoC fast IRQ 0..5; via testbench) test: ", cnt_test);
 
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
 
cnt_test++;
 
// enable SOC FIRQs
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) {
for (id=CSR_MIE_FIRQ10E; id<=CSR_MIE_FIRQ15E; id++) {
neorv32_cpu_irq_enable(id);
}
 
// trigger all SoC Fast interrupts at once
neorv32_cpu_dint(); // do not fire yet!
sim_irq_trigger((1 << CSR_MIE_FIRQ8E) | (1 << CSR_MIE_FIRQ9E) | (1 << CSR_MIE_FIRQ10E) | (1 << CSR_MIE_FIRQ11E) |
(1 << CSR_MIE_FIRQ12E) | (1 << CSR_MIE_FIRQ13E) | (1 << CSR_MIE_FIRQ14E) | (1 << CSR_MIE_FIRQ15E));
sim_irq_trigger((1 << CSR_MIE_FIRQ10E) | (1 << CSR_MIE_FIRQ11E) | (1 << CSR_MIE_FIRQ12E) | (1 << CSR_MIE_FIRQ13E) | (1 << CSR_MIE_FIRQ14E) | (1 << CSR_MIE_FIRQ15E));
 
// wait some time for the IRQ to arrive the CPU
asm volatile("nop");
1224,8 → 1323,7
asm volatile("nop");
 
// make sure all SoC FIRQs have been triggered
tmp_a = (1 << CSR_MIP_FIRQ8P) | (1 << CSR_MIP_FIRQ9P) | (1 << CSR_MIP_FIRQ10P) | (1 << CSR_MIP_FIRQ11P) |
(1 << CSR_MIP_FIRQ12P) | (1 << CSR_MIP_FIRQ13P) | (1 << CSR_MIP_FIRQ14P) | (1 << CSR_MIP_FIRQ15P);
tmp_a = (1 << CSR_MIP_FIRQ10P) | (1 << CSR_MIP_FIRQ11P) | (1 << CSR_MIP_FIRQ12P) | (1 << CSR_MIP_FIRQ13P) | (1 << CSR_MIP_FIRQ14P) | (1 << CSR_MIP_FIRQ15P);
 
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) {
neorv32_cpu_eint(); // allow IRQs to fire again
1242,7 → 1340,7
}
 
// disable SOC FIRQs
for (id=CSR_MIE_FIRQ8E; id<=CSR_MIE_FIRQ15E; id++) {
for (id=CSR_MIE_FIRQ10E; id<=CSR_MIE_FIRQ15E; id++) {
neorv32_cpu_irq_disable(id);
}
}
1257,7 → 1355,7
// Test WFI ("sleep") instructions, wakeup via MTIME
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] WFI (wait for interrupt / sleep instruction) test (wake-up via MTIME): ", cnt_test);
neorv32_uart_printf("[%i] WFI (sleep instruction) test (wake-up via MTIME): ", cnt_test);
 
if (neorv32_mtime_available()) {
cnt_test++;
1349,7 → 1447,7
// ----------------------------------------------------------
// Test physical memory protection
// ----------------------------------------------------------
neorv32_uart_printf("[%i] Physical memory protection (PMP): ", cnt_test);
neorv32_uart_printf("[%i] PMP - Physical memory protection: ", cnt_test);
 
// check if PMP is implemented
if (neorv32_cpu_pmp_get_num_regions() != 0) {
1377,7 → 1475,7
 
 
// ------ EXECUTE: should fail ------
neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] execute test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] execute test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1402,7 → 1500,7
 
 
// ------ LOAD: should work ------
neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] read test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] read test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1427,7 → 1525,7
 
 
// ------ STORE: should fail ------
neorv32_uart_printf("[%i] - PMP: U-mode [!X,!W,R] write test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] write test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1451,8 → 1549,8
}
 
 
// ------ Lock test - pmpcfg0.0 ------
neorv32_uart_printf("[%i] - PMP: pmpcfg0.0 [mode=off] lock test: ", cnt_test);
// ------ Lock test - pmpcfg0.0 / pmpaddr0 ------
neorv32_uart_printf("[%i] PMP: Entry [mode=off] lock test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1462,26 → 1560,10
tmp_a = neorv32_cpu_csr_read(CSR_PMPCFG0);
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // try to re-write CFG content
 
if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPCFG0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
test_fail();
}
else {
test_ok();
}
 
 
// ------ Lock test - pmpaddr0 ------
neorv32_uart_printf("[%i] - PMP: pmpaddr0 [mode=off] lock test: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked, but entry is deactivated (mode = off)
 
// make sure a locked cfg cannot be written
tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
tmp_b = neorv32_cpu_csr_read(CSR_PMPADDR0);
neorv32_cpu_csr_write(CSR_PMPADDR0, 0xABABCDCD); // try to re-write ADDR content
 
if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPADDR0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPCFG0)) || (tmp_b != neorv32_cpu_csr_read(CSR_PMPADDR0)) || (neorv32_cpu_csr_read(CSR_MCAUSE) != 0)) {
test_fail();
}
else {
1501,7 → 1583,7
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (succeeding access): ", cnt_test);
 
#ifdef __riscv_atomic
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
1538,7 → 1620,7
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (failing access): ", cnt_test);
 
#ifdef __riscv_atomic
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
if (is_simulation) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
1571,22 → 1653,22
// HPM reports
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
neorv32_uart_printf("\n\n-- HPM reports (%u HPMs available) --\n", num_hpm_cnts_global);
neorv32_uart_printf("#IR - Total number of instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = HPM_0
//neorv32_uart_printf("#TM - Current system time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = HPM_1
neorv32_uart_printf("#CY - Total number of clk cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = HPM_2
neorv32_uart_printf("#03 - Retired compr. instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
neorv32_uart_printf("#04 - I-fetch wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
neorv32_uart_printf("#05 - I-issue wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
neorv32_uart_printf("#06 - Multi-cyc. ALU wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
neorv32_uart_printf("#07 - Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
neorv32_uart_printf("#11 - Cond. branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
neorv32_uart_printf("#12 - Cond. branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
neorv32_uart_printf("\n\n-- HPM reports LOW (%u HPMs available) --\n", num_hpm_cnts_global);
neorv32_uart_printf("#IR - Total number of instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
//neorv32_uart_printf("#TM - Current system time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = "HPM_1"
neorv32_uart_printf("#CY - Total number of clk cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = "HPM_2"
neorv32_uart_printf("#03 - Retired compr. instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
neorv32_uart_printf("#04 - I-fetch wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
neorv32_uart_printf("#05 - I-issue wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
neorv32_uart_printf("#06 - Multi-cyc. ALU wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
neorv32_uart_printf("#07 - Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
neorv32_uart_printf("#11 - Cond. branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
neorv32_uart_printf("#12 - Cond. branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
 
 
// ----------------------------------------------------------
/demo_twi/main.c
178,6 → 178,7
neorv32_uart_printf("Select new clock prescaler (0..7): ");
neorv32_uart_scan(terminal_buffer, 2, 1); // 1 hex char plus '\0'
uint8_t prsc = (uint8_t)hexstr_to_uint(terminal_buffer, strlen(terminal_buffer));
 
if ((prsc >= 0) && (prsc < 8)) { // valid?
TWI_CT = 0; // reset
TWI_CT = (1 << TWI_CT_EN) | (prsc << TWI_CT_PRSC0);
189,18 → 190,19
}
 
// print new clock frequency
uint32_t clock = SYSINFO_CLK;
uint32_t div = 0;
switch (prsc) {
case 0: clock = clock / 2; break;
case 1: clock = clock / 4; break;
case 2: clock = clock / 8; break;
case 3: clock = clock / 64; break;
case 4: clock = clock / 128; break;
case 5: clock = clock / 1024; break;
case 6: clock = clock / 2048; break;
case 7: clock = clock / 4096; break;
default: clock = 0; break;
case 0: div = 4 * 2; break;
case 1: div = 4 * 4; break;
case 2: div = 4 * 8; break;
case 3: div = 4 * 64; break;
case 4: div = 4 * 128; break;
case 5: div = 4 * 1024; break;
case 6: div = 4 * 2048; break;
case 7: div = 4 * 4096; break;
default: div = 0; break;
}
uint32_t clock = SYSINFO_CLK / div;
neorv32_uart_printf("New I2C clock: %u Hz\n", clock);
}
 

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