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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/example
    from Rev 50 to Rev 51
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  •

Rev 50 → Rev 51

/bit_manipulation/main.c
50,6 → 50,10
#define BAUD_RATE (19200)
//** Number of test cases for each instruction */
#define NUM_TEST_CASES (10000)
//** Run Zbb tests when 1 */
#define RUN_ZBB_TESTS (1)
//** Run Zbs tests when 1 */
#define RUN_ZBS_TESTS (1)
/**@}*/
 
 
75,18 → 79,22
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// intro
neorv32_uart_printf("NEORV32 Bit Manipulation (B.Zbb) Extension Test\n\n");
neorv32_uart_printf("NEORV32 Bit Manipulation Extension Test\n\n");
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
 
neorv32_uart_printf("Starting bit manipulation extensions tests (%i test cases per instruction)...\n", num_tests);
neorv32_uart_printf("Starting bit manipulation extension tests (%i test cases per instruction)...\n", num_tests);
 
// -------------------------------------------------------------
// Zbb
// -------------------------------------------------------------
#if (RUN_ZBB_TESTS != 0)
// CLZ
neorv32_uart_printf("\nCLZ:\n");
err_cnt = 0;
294,8 → 302,106
err_cnt += check_result(i, opa, 0, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
#endif
 
// -------------------------------------------------------------
// Zbs
// -------------------------------------------------------------
#if (RUN_ZBS_TESTS != 0)
// SBSET
neorv32_uart_printf("\nSBSET:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_sbset(opa, opb);
res_hw = riscv_intrinsic_sbset(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBCLR
neorv32_uart_printf("\nSBCLR:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_sbclr(opa, opb);
res_hw = riscv_intrinsic_sbclr(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBINV
neorv32_uart_printf("\nSBINV:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_sbinv(opa, opb);
res_hw = riscv_intrinsic_sbinv(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBEXT
neorv32_uart_printf("\nSBEXT:\n");
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
opb = xorshift32();
res_sw = riscv_emulate_sbext(opa, opb);
res_hw = riscv_intrinsic_sbext(opa, opb);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBSETI
neorv32_uart_printf("\nSBSETI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_sbset(opa, 20);
res_hw = riscv_intrinsic_sbseti20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBCLRI
neorv32_uart_printf("\nSBCLRI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_sbclr(opa, 20);
res_hw = riscv_intrinsic_sbclri20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBINVI
neorv32_uart_printf("\nSBINVI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_sbinv(opa, 20);
res_hw = riscv_intrinsic_sbinvi20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
 
// SBEXTI
neorv32_uart_printf("\nSBEXTI (imm=20):\n"); // FIXME: static immediate
err_cnt = 0;
for (i=0;i<num_tests; i++) {
opa = xorshift32();
res_sw = riscv_emulate_sbext(opa, 20);
res_hw = riscv_intrinsic_sbexti20(opa);
err_cnt += check_result(i, opa, opb, res_sw, res_hw);
}
print_report(err_cnt, num_tests);
#endif
 
 
neorv32_uart_printf("\nBit manipulation extension tests done.\n");
 
return 0;
/bit_manipulation/neorv32_b_extension_intrinsics.h
158,6 → 158,10
// ################################################################################################
 
 
// ---------------------------------------------
// Zbb - Base instructions
// ---------------------------------------------
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLZ (count leading zeros) [B.Zbb]
*
511,11 → 515,181
}
 
 
// ---------------------------------------------
// Zbs - Single-bit instructions
// ---------------------------------------------
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBCLR (clear single bit) [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Bit [operand2] cleared in operand 1.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbclr(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
 
// sbclr a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100100, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBSET (set single bit) [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Bit [operand2] set in operand 1.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbset(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
 
// sbset a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0010100, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBINV (invert single bit) [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Bit [operand2] inverted in operand 1.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbinv(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
 
// sbinv a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0110100, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBEXT (extract single bit) [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Extracted bit (indexed by operand 2) from operand 1 in bit 0.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbext(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
 
// sbext a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100100, a1, a0, 0b101, a0, 0b0110011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBCLR (clear single bit), bit 20 [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Bit 20 cleared in operand 1.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbclri20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
 
// sbclri a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, a0, 0b001, a0, 0b0010011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBSET (set single bit), bit 20 [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Bit 20 set in operand 1.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbseti20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
 
// sbseti a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0010100, 0b10100, a0, 0b001, a0, 0b0010011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBINV (invert single bit) [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Bit 20 inverted in operand 1.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbinvi20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
 
// sbinvi a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0110100, 0b10100, a0, 0b001, a0, 0b0010011);
 
return result;
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBEXT (extract single bit) [B.Zbs]
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
* @warning Fixed shift amount (20) for now.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Extracted bit (20) from operand 1 in bit 0.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbexti20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
 
// sbexti a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, a0, 0b101, a0, 0b0010011);
 
return result;
}
 
 
// ################################################################################################
// Emulation functions
// ################################################################################################
 
 
// ---------------------------------------------
// Zbb - Base instructions
// ---------------------------------------------
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation CLZ (count leading zeros) [emulation]
*
838,5 → 1012,70
}
 
 
// ---------------------------------------------
// Zbs - Single-bit instructions
// ---------------------------------------------
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBCLR (clear single bit) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Bit [operand2] cleared in operand 1.
**************************************************************************/
uint32_t riscv_emulate_sbclr(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
 
return rs1 & (~(1 << shamt));
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBSET (set single bit) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Bit [operand2] set in operand 1.
**************************************************************************/
uint32_t riscv_emulate_sbset(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
 
return rs1 | (1 << shamt);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBINV (invert single bit) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Bit [operand2] inverted in operand 1.
**************************************************************************/
uint32_t riscv_emulate_sbinv(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
 
return rs1 ^ (1 << shamt);
}
 
 
/**********************************************************************//**
* Intrinsic: Bit manipulation SBEXT (extract single bit) [emulation]
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a0).
* @return Extracted bit (indexed by operand 2) from operand 1 in bit 0.
**************************************************************************/
uint32_t riscv_emulate_sbext(uint32_t rs1, uint32_t rs2) {
 
uint32_t shamt = rs2 & 0x1f;
 
return (rs1 >> shamt) & 1;
}
 
 
#endif // neorv32_b_extension_intrinsics_h
/blink_led/main.c
73,8 → 73,8
**************************************************************************/
int main() {
 
// init UART (primary UART = UART0; if no id number is specified the primary UART is used) at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART (primary UART = UART0; if no id number is specified the primary UART is used) at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check if GPIO unit is implemented at all
if (neorv32_gpio_available() == 0) {
/coremark/core_portme.c
150,8 → 150,8
{
/* NEORV32-specific */
neorv32_cpu_dint(); // no interrupt, thanks
neorv32_rte_setup(); // capture all exceptions and give debug information
neorv32_uart_setup(BAUD_RATE, 0b00); // init UART at default baud rate, no parity bits
neorv32_rte_setup(); // capture all exceptions and give debug information, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
 
// Disable coremark compilation by default
/cpu_test/main.c
95,8 → 95,7
 
 
/**********************************************************************//**
* This program uses mostly synthetic case to trigger all implemented exceptions.
* Each exception is captured and evaluated for correct detection.
* High-level CPU/processor test program.
*
* @note Applications has to be compiler with <USER_FLAGS+=-DRUN_CPUTEST>
*
111,8 → 110,8
uint32_t is_simulation = 0;
 
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// Disable cpu_test compilation by default
#ifndef RUN_CPUTEST
1077,7 → 1076,7
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ4 test (via UART1.RX): ", cnt_test);
 
if (neorv32_uart1_available()) {
if ((neorv32_uart1_available()) && (is_simulation)) { // UART1 available and we are in a simulation
cnt_test++;
 
// UART1 RX interrupt enable
/demo_freeRTOS/main.c
127,8 → 127,8
// clear GPIO.out port
neorv32_gpio_port_set(0);
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
231,8 → 231,8
#include <neorv32.h>
int main() {
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
neorv32_uart_print("ERROR! FreeRTOS has not been compiled. Use >>make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe<< to compile it.\n");
return 0;
}
/demo_gpio_irq/main.c
72,8 → 72,8
// setup run-time environment for interrupts and exceptions
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_nco/main.c
73,8 → 73,8
// setup run-time environment for interrupts and exceptions
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_pwm/main.c
73,8 → 73,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_trng/main.c
75,8 → 75,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_twi/main.c
83,8 → 83,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/demo_wdt/main.c
75,8 → 75,8
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/game_of_life/main.c
97,8 → 97,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/hello_world/main.c
65,8 → 65,8
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
/hex_viewer/main.c
84,8 → 84,8
// disable global interrupts
neorv32_cpu_dint();
 
// init UART at default baud rate, no parity bits
neorv32_uart_setup(BAUD_RATE, 0b00);
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch

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