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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/include
    from Rev 65 to Rev 66
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Rev 65 → Rev 66

/neorv32.h
492,6 → 492,89
 
 
/**********************************************************************//**
* @defgroup FIRQ_ALIASES Fast Interrupt Requests (FIRQ) Aliases (MIE, MIP, MCAUSE, RTE-ID)
* @name Fast Interrupt Requests (FIRQ) Aliases (MIE, MIP, MCAUSE, RTE-ID)
**************************************************************************/
/**@{*/
/** @name Watchdog Timer (WDT) */
/**@{*/
#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define WDT_RTE_ID RTE_TRAP_FIRQ_0 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Custom Functions Subsystem (CFS) */
/**@{*/
#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */
/**@{*/
#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Secondary Universal Asynchronous Receiver/Transmitter (UART1) */
/**@{*/
#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Serial Peripheral Interface (SPI) */
/**@{*/
#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define SPI_RTE_ID RTE_TRAP_FIRQ_6 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Two-Wire Interface (TWI) */
/**@{*/
#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define TWI_RTE_ID RTE_TRAP_FIRQ_7 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name External Interrupt Controller (XIRQ) */
/**@{*/
#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Smart LED Controller (NEOLED) */
/**@{*/
#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Stream Link Interface (SLINK) */
/**@{*/
#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ10E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ10P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_10 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_10 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ11E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ11P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_11 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_11 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/**@}*/
 
 
/**********************************************************************//**
* @name Address space sections
**************************************************************************/
/**@{*/
719,6 → 802,27
 
 
/**********************************************************************//**
* @name IO Device: Bus Monitor (BUSKEEPER)
**************************************************************************/
/**@{*/
/** BUSKEEPER module prototype */
typedef struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
} neorv32_buskeeper_t;
 
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
 
/** BUSKEEPER control/data register bits */
enum NEORV32_BUSKEEPER_CTRL_enum {
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
BUSKEEPER_ERR_SRC = 1, /**< BUSKEEPER control register(1) (r/-): Bus error source: 0=processor-external, 1=processor-internal */
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read */
};
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: External Interrupt Controller (XIRQ)
**************************************************************************/
/**@{*/
805,8 → 909,8
UART_CTRL_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
UART_CTRL_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */
UART_CTRL_EN = 28, /**< UART control register(28) (r/w): UART global enable */
UART_CTRL_RX_IRQ = 29, /**< UART control register(29) (r/w: RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty */
UART_CTRL_TX_IRQ = 30, /**< UART control register(30) (r/w: TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full */
UART_CTRL_RX_IRQ = 29, /**< UART control register(29) (r/w): RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty */
UART_CTRL_TX_IRQ = 30, /**< UART control register(30) (r/w): TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full */
UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
};
 
1056,13 → 1160,12
SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */
SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
SYSINFO_CPU_ZBB = 3, /**< SYSINFO_CPU (3): Zbb extension (B sub-extension) available when set (r/-) */
 
SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
SYSINFO_CPU_ZXNOCNT = 7, /**< SYSINFO_CPU (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basie CPU counters available when set (r/-) */
SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
SYSINFO_CPU_HPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
 
SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
/neorv32_spi.h
52,6 → 52,8
void neorv32_spi_cs_en(uint8_t cs);
void neorv32_spi_cs_dis(uint8_t cs);
uint32_t neorv32_spi_trans(uint32_t tx_data);
void neorv32_spi_put_nonblocking(uint32_t tx_data);
uint32_t neorv32_spi_get_nonblocking(void);
int neorv32_spi_busy(void);
 
#endif // neorv32_spi_h
/neorv32_xirq.h
36,26 → 36,12
/**********************************************************************//**
* @file neorv32_xirq.h
* @author Stephan Nolting
* @brief SExternal Interrupt controller HW driver header file.
* @brief External Interrupt controller HW driver header file.
**************************************************************************/
 
#ifndef neorv32_xirq_h
#define neorv32_xirq_h
 
 
/**********************************************************************//**
* @name XIRQ fast interrupt channel
**************************************************************************/
/**@{*/
/** XIRQ MIE FIRQ bit */
#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E // MIE FIRQ bit
/** XIRQ MIP FIRQ bit */
#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P // MIP FIRQ bit
/** XIRQ RTE IRQ ID */
#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8 // RTE IRQ ID
/**@}*/
 
 
// prototypes
int neorv32_xirq_available(void);
int neorv32_xirq_setup(void);

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