URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw/lib/source
- from Rev 52 to Rev 53
- ↔ Reverse comparison
Rev 52 → Rev 53
/neorv32_cpu.c
43,7 → 43,34
#include "neorv32_cpu.h" |
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/**********************************************************************//** |
* Unavailable extensions warning. |
**************************************************************************/ |
#if defined __riscv_f || (__riscv_flen == 32) |
#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and NOT FULLY OPERATIONAL yet! |
#endif |
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#if defined __riscv_d || (__riscv_flen == 64) |
#error Double-precision floating-point extension <D/Zdinx> is NOT supported! |
#endif |
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#if (__riscv_xlen > 32) |
#error Only 32-bit <rv32> is supported! |
#endif |
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#ifdef __riscv_b |
#warning Bit-manipulation extension <B> is still experimental (non-ratified) and does not support all <Zb*> subsets yet. |
#endif |
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#ifdef __riscv_fdiv |
#warning Floating-point division instruction <FDIV> is NOT supported yet! |
#endif |
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#ifdef __riscv_fsqrt |
#warning Floating-point square root instruction <FSQRT> is NOT supported yet! |
#endif |
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/**********************************************************************//** |
* >Private< helper functions. |
**************************************************************************/ |
/neorv32_rte.c
55,14 → 55,6
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/**********************************************************************//** |
* Floating-Point extension notifier. |
**************************************************************************/ |
#ifdef __riscv_flen |
#warning Floating-point extension <F> is WORK-IN-PROGRESS and NOT FULLY OPERATIONAL yet! |
#endif |
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/**********************************************************************//** |
* Setup NEORV32 runtime environment. |
* |
* @note This function installs a debug handler for ALL exception and interrupt sources, which |
355,6 → 347,12
if (tmp & (1<<CSR_MZEXT_ZBS)) { |
neorv32_uart_printf("Zbs "); |
} |
if (tmp & (1<<CSR_MZEXT_ZBA)) { |
neorv32_uart_printf("Zba "); |
} |
if (tmp & (1<<CSR_MZEXT_ZFINX)) { |
neorv32_uart_printf("Zfinx "); |
} |
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// check physical memory protection |
neorv32_uart_printf("\nPMP: "); |
647,15 → 645,19
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uint32_t misa_cc = 0; |
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#ifdef __riscv_atomic |
#if defined __riscv_atomic || defined __riscv_a |
misa_cc |= 1 << CSR_MISA_A_EXT; |
#endif |
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#ifdef __riscv_compressed |
#ifdef __riscv_b |
misa_cc |= 1 << CSR_MISA_B_EXT; |
#endif |
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#if defined __riscv_compressed || defined __riscv_c |
misa_cc |= 1 << CSR_MISA_C_EXT; |
#endif |
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#if (__riscv_flen == 64) |
#if (__riscv_flen == 64) || defined __riscv_d |
misa_cc |= 1 << CSR_MISA_D_EXT; |
#endif |
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665,11 → 667,11
misa_cc |= 1 << CSR_MISA_I_EXT; |
#endif |
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#if (__riscv_flen == 32) |
#if (__riscv_flen == 32) || defined __riscv_f |
misa_cc |= 1 << CSR_MISA_F_EXT; |
#endif |
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#ifdef __riscv_mul |
#if defined __riscv_mul || defined __riscv_m |
misa_cc |= 1 << CSR_MISA_M_EXT; |
#endif |
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