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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/source
    from Rev 59 to Rev 60
    ↔ Reverse comparison
  •

Rev 59 → Rev 60

/neorv32_cpu.c
47,7 → 47,7
* Unavailable extensions warning.
**************************************************************************/
#if defined __riscv_f || (__riscv_flen == 32)
#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and NOT FULLY OPERATIONAL yet!
#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and there is NO NATIVE SUPPORT BY THE COMPILER yet!
#endif
 
#if defined __riscv_d || (__riscv_flen == 64)
714,18 → 714,18
/**********************************************************************//**
* Check if certain Z* extension is available
*
* @param[in] flag Index of the Z-extension to check from #NEORV32_CSR_MZEXT_enum
* @param[in] flag_id Index of the Z-extension to check from #NEORV32_CSR_MZEXT_enum
* @return 0 if extension is NOT available, != 0 if extension is available.
**************************************************************************/
int neorv32_check_zextension(uint32_t flag) {
int neorv32_cpu_check_zext(uint8_t flag_id) {
 
// check if out of range
if (flag > 31) {
if (flag_id > 31) {
return 0;
}
 
uint32_t tmp = neorv32_cpu_csr_read(CSR_MZEXT);
if ((tmp & (1 << flag)) == 0) {
uint32_t mask = (uint32_t)(1 << flag_id);
if ((neorv32_cpu_csr_read(CSR_MZEXT) & mask) == 0) {
return 0;
}
else {
732,3 → 732,4
return 1;
}
}
 
/neorv32_pwm.c
90,25 → 90,78
 
 
/**********************************************************************//**
* Set duty cycle for channel. The PWM duty cycle bits are listed in #NEORV32_PWM_DUTY_enum.
* Get number of implemented channels.
* @warning This function will override all duty cycle configuration registers.
*
* @param[in] channel Channel select (0..3).
* @return Number of implemented channels.
**************************************************************************/
int neorv32_pmw_get_num_channels(void) {
 
neorv32_pwm_disable();
 
uint8_t index = 0;
uint8_t cnt = 0;
 
for (index=0; index<60; index++) {
neorv32_pwm_set(index, 1);
cnt += neorv32_pwm_get(index);
}
 
return (int)cnt;
}
 
 
/**********************************************************************//**
* Set duty cycle for channel.
*
* @param[in] channel Channel select (0..59).
* @param[in] duty Duty cycle (0..255).
**************************************************************************/
void neorv32_pwm_set(uint8_t channel, uint8_t duty) {
 
channel = channel & 0x03;
if (channel > 59) {
return; // out-of-range
}
 
// compute duty-cycle offset
uint32_t reg_offset = (uint32_t)(channel / 4);
uint8_t byte_offset = channel % 4;
 
// read-modify-write
uint32_t duty_mask = 0xff;
uint32_t duty_new = (uint32_t)duty;
 
duty_mask = duty_mask << (channel * 8);
duty_new = duty_new << (channel * 8);
duty_mask = duty_mask << (byte_offset * 8);
duty_new = duty_new << (byte_offset * 8);
 
uint32_t duty_cycle = PWM_DUTY;
uint32_t duty_cycle = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
 
duty_cycle &= ~duty_mask; // clear previous duty cycle
duty_cycle |= duty_new; // set new duty cycle
 
PWM_DUTY = duty_cycle;
(*(IO_REG32 (&PWM_DUTY0 + reg_offset))) = duty_cycle;
}
 
 
/**********************************************************************//**
* Get duty cycle from channel.
*
* @param[in] channel Channel select (0..59).
* @return Duty cycle (0..255) of channel 'channel'.
**************************************************************************/
uint8_t neorv32_pwm_get(uint8_t channel) {
 
if (channel > 59) {
return 0; // out-of-range
}
 
// compute duty-cycle offset
uint32_t reg_offset = (uint32_t)(channel / 4);
uint8_t byte_offset = channel % 4;
 
// read
uint32_t tmp = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
tmp = tmp >> ((byte_offset * 8));
 
return (uint8_t)tmp;
}
/neorv32_rte.c
296,36 → 296,21
// hardware version
neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
neorv32_rte_print_hw_version();
neorv32_uart_printf(")\n");
neorv32_uart_putc(')');
 
// CPU architecture
neorv32_uart_printf("Architecture: ");
// CPU architecture and endianness
neorv32_uart_printf("\nArchitecture: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
tmp = (tmp >> 30) & 0x03;
if (tmp == 0) {
neorv32_uart_printf("unknown");
}
if (tmp == 1) {
neorv32_uart_printf("rv32");
neorv32_uart_printf("rv32-little");
}
if (tmp == 2) {
neorv32_uart_printf("rv64");
}
if (tmp == 3) {
neorv32_uart_printf("rv128");
}
// CPU extensions
neorv32_uart_printf("\nEndianness: ");
if (neorv32_cpu_csr_read(CSR_MSTATUSH) & (1<<CSR_MSTATUSH_MBE)) {
neorv32_uart_printf("big\n");
}
else {
neorv32_uart_printf("little\n");
neorv32_uart_printf("unknown");
}
// CPU extensions
neorv32_uart_printf("Extensions: ");
neorv32_uart_printf("\nExtensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
for (i=0; i<26; i++) {
if (tmp & (1 << i)) {
343,15 → 328,7
if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
neorv32_uart_printf("Zifencei ");
}
if (tmp & (1<<CSR_MZEXT_ZBB)) {
neorv32_uart_printf("Zbb ");
}
if (tmp & (1<<CSR_MZEXT_ZBS)) {
neorv32_uart_printf("Zbs ");
}
if (tmp & (1<<CSR_MZEXT_ZBA)) {
neorv32_uart_printf("Zba ");
}
 
if (tmp & (1<<CSR_MZEXT_ZFINX)) {
neorv32_uart_printf("Zfinx ");
}

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