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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/source
    from Rev 65 to Rev 66
    ↔ Reverse comparison
  •

Rev 65 → Rev 66

/neorv32_cpu.c
612,7 → 612,7
uint32_t neorv32_cpu_hpm_get_counters(void) {
 
// HPMs implemented at all?
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_HPM)) == 0) {
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZIHPM)) == 0) {
return 0;
}
 
695,7 → 695,7
uint32_t neorv32_cpu_hpm_get_size(void) {
 
// HPMs implemented at all?
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_HPM)) == 0) {
if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZIHPM)) == 0) {
return 0;
}
 
/neorv32_neoled.c
96,7 → 96,7
 
/**********************************************************************//**
* Configure NEOLED controller for using WS2812 LEDs (NeoPixel-compatible). This function computes
* all the required timings and finally calls #neorv32_neoled_setup_raw.
* all the required timings and finally calls #neorv32_neoled_setup.
*
* @note WS2812 timing: T_period = 1.2us, T_high_zero = 0.4us, T_high_one = 0.8us. Change the constants if required.
* @note This function uses the SYSINFO_CLK value (from the SYSINFO HW module) to do the timing computations.
/neorv32_rte.c
202,14 → 202,12
return; // handler cannot output anything if UART0 is not implemented
}
 
char tmp;
 
// intro
neorv32_uart0_print("<RTE> ");
 
// cause
register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
tmp = (char)(trap_cause & 0xf);
register char tmp = (char)(trap_cause & 0xf);
if (tmp >= 10) {
tmp = 'a' + (tmp - 10);
}
249,9 → 247,25
default: neorv32_uart0_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
}
 
// check cause if bus access fault exception
if ((trap_cause == TRAP_CODE_I_ACCESS) || (trap_cause == TRAP_CODE_L_ACCESS) || (trap_cause == TRAP_CODE_S_ACCESS)) {
register uint32_t bus_err = NEORV32_BUSKEEPER.CTRL;
if (bus_err & (1<<BUSKEEPER_ERR_FLAG)) { // exception caused by bus system?
if (bus_err & (1<<BUSKEEPER_ERR_TYPE)) {
neorv32_uart0_print(" [TIMEOUT_ERR]");
}
else {
neorv32_uart0_print(" [DEVICE_ERR]");
}
}
else { // exception was not caused by bus system -> has to be caused by PMP rule violation
neorv32_uart0_print(" [PMP_ERR]");
}
}
 
// instruction address
neorv32_uart0_print(" @ PC=");
__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores actual mepc to mscratch
__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores original mepc to mscratch
 
// additional info
neorv32_uart0_print(", MTVAL=");
324,6 → 338,12
if (tmp & (1<<SYSINFO_CPU_ZICSR)) {
neorv32_uart0_printf("Zicsr ");
}
if (tmp & (1<<SYSINFO_CPU_ZICNTR)) {
neorv32_uart0_printf("Zicntr ");
}
if (tmp & (1<<SYSINFO_CPU_ZIHPM)) {
neorv32_uart0_printf("Zihpm ");
}
if (tmp & (1<<SYSINFO_CPU_ZIFENCEI)) {
neorv32_uart0_printf("Zifencei ");
}
330,23 → 350,16
if (tmp & (1<<SYSINFO_CPU_ZMMUL)) {
neorv32_uart0_printf("Zmmul ");
}
if (tmp & (1<<SYSINFO_CPU_ZBB)) {
neorv32_uart0_printf("Zbb ");
}
 
if (tmp & (1<<SYSINFO_CPU_ZFINX)) {
neorv32_uart0_printf("Zfinx ");
}
if (tmp & (1<<SYSINFO_CPU_ZXNOCNT)) {
neorv32_uart0_printf("Zxnocnt(!) ");
}
if (tmp & (1<<SYSINFO_CPU_ZXSCNT)) {
neorv32_uart0_printf("Zxscnt(!) ");
}
 
if (tmp & (1<<SYSINFO_CPU_DEBUGMODE)) {
neorv32_uart0_printf("Debug-Mode ");
neorv32_uart0_printf("Debug ");
}
 
if (tmp & (1<<SYSINFO_CPU_FASTMUL)) {
neorv32_uart0_printf("FAST_MUL ");
}
364,14 → 377,11
neorv32_uart0_printf("not implemented\n");
}
 
// check hardware performance monitors
neorv32_uart0_printf("HPM Counters: %u counters, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
 
 
// Memory configuration
neorv32_uart0_printf("\n=== << Memory System >> ===\n");
 
neorv32_uart0_printf("Boot Config.: Boot ");
neorv32_uart0_printf("Boot Config.: Boot ");
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_BOOTLOADER)) {
neorv32_uart0_printf("via Bootloader\n");
}
379,10 → 389,10
neorv32_uart0_printf("from memory (@ 0x%x)\n", NEORV32_SYSINFO.ISPACE_BASE);
}
 
neorv32_uart0_printf("Instr. base address: 0x%x\n", NEORV32_SYSINFO.ISPACE_BASE);
neorv32_uart0_printf("Instr. base address: 0x%x\n", NEORV32_SYSINFO.ISPACE_BASE);
 
// IMEM
neorv32_uart0_printf("Internal IMEM: ");
neorv32_uart0_printf("Internal IMEM: ");
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_INT_IMEM)) {
neorv32_uart0_printf("yes, %u bytes\n", NEORV32_SYSINFO.IMEM_SIZE);
}
391,8 → 401,8
}
 
// DMEM
neorv32_uart0_printf("Data base address: 0x%x\n", NEORV32_SYSINFO.DSPACE_BASE);
neorv32_uart0_printf("Internal DMEM: ");
neorv32_uart0_printf("Data base address: 0x%x\n", NEORV32_SYSINFO.DSPACE_BASE);
neorv32_uart0_printf("Internal DMEM: ");
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_INT_DMEM)) {
neorv32_uart0_printf("yes, %u bytes\n", NEORV32_SYSINFO.DMEM_SIZE);
}
401,7 → 411,7
}
 
// i-cache
neorv32_uart0_printf("Internal i-cache: ");
neorv32_uart0_printf("Internal i-cache: ");
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_ICACHE)) {
neorv32_uart0_printf("yes, ");
 
439,9 → 449,9
neorv32_uart0_printf("no\n");
}
 
neorv32_uart0_printf("Ext. bus interface: ");
neorv32_uart0_printf("Ext. bus interface: ");
__neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT));
neorv32_uart0_printf("Ext. bus Endianness: ");
neorv32_uart0_printf("Ext. bus Endianness: ");
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT_ENDIAN)) {
neorv32_uart0_printf("big\n");
}
/neorv32_slink.c
34,7 → 34,7
 
 
/**********************************************************************//**
* @file neorv32_slink.h
* @file neorv32_slink.c
* @author Stephan Nolting
* @brief Stream Link Interface HW driver source file.
**************************************************************************/
/neorv32_spi.c
143,8 → 143,6
/**********************************************************************//**
* Initiate SPI transfer.
*
* @warning The SPI always sends MSB first.
*
* @note This function is blocking.
*
* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
160,6 → 158,28
 
 
/**********************************************************************//**
* Initiate SPI TX transfer (non-blocking).
*
* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
**************************************************************************/
void neorv32_spi_put_nonblocking(uint32_t tx_data) {
 
NEORV32_SPI.DATA = tx_data; // trigger transfer
}
 
 
/**********************************************************************//**
* Get SPI RX data (non-blocking).
*
* @return Receive data (8/16/24/32-bit, LSB-aligned).
**************************************************************************/
uint32_t neorv32_spi_get_nonblocking(void) {
 
return NEORV32_SPI.DATA;
}
 
 
/**********************************************************************//**
* Check if SPI transceiver is busy.
*
* @return 0 if idle, 1 if busy
/neorv32_uart.c
256,11 → 256,10
uint8_t p = 0; // initial prsc = CLK/2
 
// raw clock prescaler
#ifdef __riscv_div
// use div instructions
#ifndef make_bootloader
i = (uint16_t)(clock / (2*baudrate));
#else
// division via repeated subtraction
// division via repeated subtraction (minimal size, only for bootloader)
while (clock >= 2*baudrate) {
clock -= 2*baudrate;
i++;
626,11 → 625,11
uint8_t p = 0; // initial prsc = CLK/2
 
// raw clock prescaler
#ifdef __riscv_div
#ifdef make_bootloader
// use div instructions
i = (uint16_t)(clock / (2*baudrate));
#else
// division via repeated subtraction
// division via repeated subtraction (minimal size, only for bootloader)
while (clock >= 2*baudrate) {
clock -= 2*baudrate;
i++;
/neorv32_xirq.c
34,7 → 34,7
 
 
/**********************************************************************//**
* @file neorv32_xirq.h
* @file neorv32_xirq.c
* @author Stephan Nolting
* @brief External Interrupt controller HW driver source file.
**************************************************************************/

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