OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/source
    from Rev 67 to Rev 68
    ↔ Reverse comparison
  •

Rev 67 → Rev 68

/neorv32_rte.c
48,7 → 48,7
static uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS] __attribute__((unused)); // trap handler vector table
 
// private functions
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16)));
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(4)));
static void __neorv32_rte_debug_exc_handler(void);
static void __neorv32_rte_print_true_false(int state);
static void __neorv32_rte_print_checkbox(int state);
65,8 → 65,7
void neorv32_rte_setup(void) {
 
// configure trap handler base address
uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&__neorv32_rte_core));
 
// install debug handler for all sources
uint8_t id;
73,6 → 72,9
for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
neorv32_rte_exception_uninstall(id); // this will configure the debug handler
}
 
// clear BUSKEEPER error flags
NEORV32_BUSKEEPER.CTRL = 0;
}
 
 
111,7 → 113,7
 
// id valid?
if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidentally triggered
return 0;
}
return 1;
126,7 → 128,7
*
* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
**************************************************************************/
static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
static void __attribute__((__interrupt__)) __attribute__((aligned(4))) __neorv32_rte_core(void) {
 
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
133,7 → 135,7
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
 
// compute return address
if (((int32_t)rte_mcause) >= 0) { // modify pc only if exception (MSB cleared)
if (((int32_t)rte_mcause) >= 0) { // modify pc only if not interrupt (MSB cleared)
 
// get low half word of faulting instruction
register uint32_t rte_trap_inst;
151,7 → 153,7
}
 
// find according trap handler
register uint32_t rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler);
register uint32_t rte_handler;
switch (rte_mcause) {
case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
182,7 → 184,7
case TRAP_CODE_FIRQ_13: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
case TRAP_CODE_FIRQ_14: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
case TRAP_CODE_FIRQ_15: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
default: break;
default: rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler); break;
}
 
// execute handler
730,7 → 732,7
/**********************************************************************//**
* NEORV32 runtime environment: Check required ISA extensions (via compiler flags) against available ISA extensions (via MISA csr).
*
* @param[in] silent Show error message (via neorv32.uart) if isa_sw > isa_hw when != 0.
* @param[in] silent Show error message (via neorv32.uart) if isa_sw > isa_hw when = 0.
* @return MISA content according to compiler configuration.
**************************************************************************/
int neorv32_rte_check_isa(int silent) {
746,7 → 748,7
return 0;
}
else {
if ((silent == 0) || (neorv32_uart0_available() == 0)) {
if ((silent == 0) && (neorv32_uart0_available() != 0)) {
neorv32_uart0_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
"SW_ISA = 0x%x (compiler flags)\n"
"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
/neorv32_trng.c
99,20 → 99,15
**************************************************************************/
int neorv32_trng_get(uint8_t *data) {
 
const int retries = 3;
int i;
uint32_t ct_reg;
 
for (i=0; i<retries; i++) {
ct_reg = NEORV32_TRNG.CTRL;
ct_reg = NEORV32_TRNG.CTRL;
 
if ((ct_reg & (1<<TRNG_CTRL_VALID)) == 0) { // output data valid?
continue;
}
 
if (ct_reg & (1<<TRNG_CTRL_VALID)) { // output data valid?
*data = (uint8_t)(ct_reg >> TRNG_CTRL_DATA_LSB);
return 0; // valid data
}
 
return -1; // no valid data available
else {
return -1;
}
}
/neorv32_twi.c
65,9 → 65,8
* Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CTRL_enum.
*
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
* @param[in] ckst_en Enable clock-stretching by peripherals when 1.
**************************************************************************/
void neorv32_twi_setup(uint8_t prsc, uint8_t ckst_en) {
void neorv32_twi_setup(uint8_t prsc) {
 
NEORV32_TWI.CTRL = 0; // reset
 
77,10 → 76,7
uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
ct_prsc = ct_prsc << TWI_CTRL_PRSC0;
 
uint32_t ct_cksten = (uint32_t)(ckst_en & 0x01);
ct_cksten = ct_cksten << TWI_CTRL_CKSTEN;
 
NEORV32_TWI.CTRL = ct_enable | ct_prsc | ct_cksten;
NEORV32_TWI.CTRL = ct_enable | ct_prsc;
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.