URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw/lib
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/include/neorv32.h
71,17 → 71,17
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/-): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/-): Machine instructions-retired counter low word */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/-): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/-): Machine instructions-retired counter high word */ |
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */ |
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CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word */ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word*/ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME) */ |
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word */ |
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CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word */ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word*/ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME) */ |
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */ |
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ |
129,10 → 129,10
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MISA_enum { |
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-), can be switched on/off */ |
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */ |
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-), can be switched on/off */ |
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */ |
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */ |
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */ |
324,17 → 324,17
* @name IO Device: Machine System Timer (MTIME) |
**************************************************************************/ |
/**@{*/ |
/** MTIME (time register) low word (r/-) */ |
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL)) |
/** MTIME (time register) high word (r/-) */ |
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL)) |
/** MTIME (time register) low word (r/w) */ |
#define MTIME_LO (*(IO_REG32 0xFFFFFF90UL)) |
/** MTIME (time register) high word (r/w) */ |
#define MTIME_HI (*(IO_REG32 0xFFFFFF94UL)) |
/** MTIMECMP (time compare register) low word (r/w) */ |
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL)) |
/** MTIMECMP (time register) high word (r/w) */ |
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL)) |
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/** MTIME (time register) 64-bit access (r/-) */ |
#define MTIME (*(IO_ROM64 (&MTIME_LO))) |
/** MTIME (time register) 64-bit access (r/w) */ |
#define MTIME (*(IO_REG64 (&MTIME_LO))) |
/** MTIMECMP (time compare register) low word (r/w) */ |
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO))) |
/**@}*/ |
/include/neorv32_cpu.h
43,7 → 43,6
#define neorv32_cpu_h |
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// prototypes |
int neorv32_cpu_switch_extension(int sel, int state); |
int neorv32_cpu_irq_enable(uint8_t irq_sel); |
int neorv32_cpu_irq_disable(uint8_t irq_sel); |
void neorv32_cpu_delay_ms(uint32_t time_ms); |
/include/neorv32_mtime.h
46,6 → 46,7
|
// prototypes |
int neorv32_mtime_available(void); |
void neorv32_mtime_set_time(uint64_t time); |
uint64_t neorv32_mtime_get_time(void); |
void neorv32_mtime_set_timecmp(uint64_t timecmp); |
uint64_t neorv32_mtime_get_timecmp(void); |
/include/neorv32_rte.h
46,6 → 46,8
void neorv32_rte_enable_debug_mode(void); |
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)); |
int neorv32_rte_exception_uninstall(uint8_t exc_id); |
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void neorv32_rte_print_hw_config(void); |
void neorv32_rte_print_credits(void); |
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#endif // neorv32_rte_h |
/source/neorv32_cpu.c
44,54 → 44,6
|
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/**********************************************************************//** |
* Enable/disable CPU extension during runtime via the 'misa' CSR. |
* |
* @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions. |
* |
* @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum. |
* @param[in] state Set 1 to enable the selected extension, set 0 to disable it; |
* return 0 if success, 1 if error (invalid sel or extension cannot be enabled). |
**************************************************************************/ |
int neorv32_cpu_switch_extension(int sel, int state) { |
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// get current misa setting |
uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA); |
uint32_t misa_prev = misa_curr; |
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// abort if misa.z is cleared |
if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) { |
return 1; |
} |
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// out of range? |
if (sel > 25) { |
return 1; |
} |
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// enable/disable selected extension |
if (state & 1) { |
misa_curr |= (1 << sel); |
} |
else { |
misa_curr &= ~(1 << sel); |
} |
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// try updating misa |
neorv32_cpu_csr_write(CSR_MISA, misa_curr); |
asm volatile("fence.i"); // required to flush prefetch buffers |
asm volatile("nop"); |
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// dit it work? |
if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) { |
return 1; // nope |
} |
else { |
return 0; // fine |
} |
} |
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/**********************************************************************//** |
* Enable specific CPU interrupt. |
* |
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too. |
/source/neorv32_mtime.c
62,10 → 62,23
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/**********************************************************************//** |
* Get current system time since reset. |
* Set current system time. |
* |
* @note The MTIME timer increments with the primary processor clock. |
* |
* @param[in] time New system time (uint64_t) |
**************************************************************************/ |
void neorv32_mtime_set_time(uint64_t time) { |
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MTIME = time; |
} |
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/**********************************************************************//** |
* Get current system time. |
* |
* @note The MTIME timer increments with the primary processor clock. |
* |
* @return Current system time (uint64_t) |
**************************************************************************/ |
uint64_t neorv32_mtime_get_time(void) { |
/source/neorv32_rte.c
373,3 → 373,16
} |
} |
} |
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/**********************************************************************//** |
* NEORV32 runtime environment: Print project credits |
**************************************************************************/ |
void neorv32_rte_print_credits(void) { |
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neorv32_uart_print("\n\nThe NEORV32 Processor Project\n" |
"by Stephan Nolting\n" |
"https://github.com/stnolting/neorv32\n" |
"made in Hannover, Germany\n\n"); |
} |
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