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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib
    from Rev 4 to Rev 6
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  •

Rev 4 → Rev 6

/include/neorv32.h
60,10 → 60,10
* Available CPU Control and Status Registers (CSRs)
**************************************************************************/
enum NEORV32_CPU_CSRS_enum {
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions */
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions */
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
 
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
127,6 → 127,21
 
 
/**********************************************************************//**
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MISA_enum {
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension available (r/-) */
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
};
 
 
/**********************************************************************//**
* CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM)
**************************************************************************/
enum NEORV32_CPU_MFEATURES_enum {
135,6 → 150,7
CPU_MFEATURES_MEM_INT_IMEM = 2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
CPU_MFEATURES_MEM_INT_IMEM_ROM = 3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
CPU_MFEATURES_MEM_INT_DMEM = 4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
CPU_MFEATURES_CSR_COUNTERS = 5, /**< CPU mfeatures CSR (5) (r/-): RISC-V performance counters implemented when 1 (via CSR_COUNTERS_USE generic) */
 
CPU_MFEATURES_IO_GPIO = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
CPU_MFEATURES_IO_MTIME = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
211,13 → 227,13
**************************************************************************/
/**@{*/
/** instruction memory base address (r/w/x) */
#define INSTR_MEM_BASE_ADDR 0x00000000
// -> use value from MEM_ISPACE_BASE CSR
/** data memory base address (r/w/x) */
#define DATA_MEM_BASE_ADDR 0x80000000
// -> use value from MEM_DSPACE_BASE CSR
/** bootloader memory base address (r/-/x) */
#define BOOTLOADER_BASE_ADDRESS 0xFFFF0000
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
/** peripheral/IO devices memory base address (r/w/x) */
#define IO_BASE_ADDRESS 0xFFFFFF80
#define IO_BASE_ADDRESS (0xFFFFFF80UL)
/**@}*/
 
 
226,9 → 242,9
**************************************************************************/
/**@{*/
/** GPIO parallel input port (r/-) */
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80))
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80UL))
/** GPIO parallel output port (r/w) */
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84))
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
/**@}*/
 
 
237,7 → 253,7
**************************************************************************/
/**@{*/
/** CLIC control register (r/w) */
#define CLIC_CT (*(IO_REG32 0xFFFFFF88))
#define CLIC_CT (*(IO_REG32 0xFFFFFF88UL))
 
/** CLIC control register bits */
enum NEORV32_CLIC_CT_enum {
284,7 → 300,7
**************************************************************************/
/**@{*/
/** Watchdog control register (r/w) */
#define WDT_CT (*(IO_REG32 0xFFFFFF8C))
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
 
/** WTD control register bits */
enum NEORV32_WDT_CT_enum {
310,13 → 326,13
**************************************************************************/
/**@{*/
/** MTIME (time register) low word (r/-) */
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90))
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL))
/** MTIME (time register) high word (r/-) */
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94))
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL))
/** MTIMECMP (time compare register) low word (r/w) */
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98))
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
/** MTIMECMP (time register) high word (r/w) */
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9C))
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
 
/** MTIME (time register) 64-bit access (r/-) */
#define MTIME (*(IO_ROM64 (&MTIME_LO)))
330,9 → 346,9
**************************************************************************/
/**@{*/
/** UART control register (r/w) */
#define UART_CT (*(IO_REG32 0xFFFFFFA0))
#define UART_CT (*(IO_REG32 0xFFFFFFA0UL))
/** UART receive/transmit data register (r/w) */
#define UART_DATA (*(IO_REG32 0xFFFFFFA4))
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
 
/** UART control register bits */
enum NEORV32_UART_CT_enum {
373,9 → 389,9
**************************************************************************/
/**@{*/
/** SPI control register (r/w) */
#define SPI_CT (*(IO_REG32 0xFFFFFFA8))
#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL))
/** SPI receive/transmit data register (r/w) */
#define SPI_DATA (*(IO_REG32 0xFFFFFFAC))
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
 
/** SPI control register bits */
enum NEORV32_SPI_CT_enum {
409,9 → 425,9
**************************************************************************/
/**@{*/
/** TWI control register (r/w) */
#define TWI_CT (*(IO_REG32 0xFFFFFFB0))
#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL))
/** TWI receive/transmit data register (r/w) */
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4))
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
 
/** TWI control register bits */
enum NEORV32_TWI_CT_enum {
441,9 → 457,9
**************************************************************************/
/**@{*/
/** PWM control register (r/w) */
#define PWM_CT (*(IO_REG32 0xFFFFFFB8)) // r/w: control register
#define PWM_CT (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
/** PWM duty cycle register (4-channels) (r/w) */
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBC)) // r/w: duty cycle channel 1 and 0
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
 
/** PWM control register bits */
enum NEORV32_PWM_CT_enum {
472,9 → 488,9
**************************************************************************/
/**@{*/
/** TRNG control register (r/w) */
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0))
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0UL))
/** TRNG data register (r/-) */
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4))
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4UL))
 
/** TRNG control register bits */
enum NEORV32_TRNG_CT_enum {
496,8 → 512,8
* @name IO Device: Dummy Device (DEVNULL)
**************************************************************************/
/**@{*/
/** TRNG data register (r/w) */
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFC))
/** DEVNULL data register (r/w) */
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFCUL))
/**@}*/
 
 
/include/neorv32_cpu.h
64,7 → 64,7
 
register uint32_t csr_data;
 
asm volatile ("csrrw %[result], %[input_i], zero" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));
asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));
return csr_data;
}
80,7 → 80,7
 
register uint32_t csr_data = data;
 
asm volatile ("csrrw zero, %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
}
 
#endif // neorv32_cpu_h
/include/neorv32_rte.h
44,7 → 44,8
 
// prototypes
void neorv32_rte_enable_debug_mode(void);
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void));
int neorv32_rte_exception_uninstall(uint8_t exc_id);
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void));
int neorv32_rte_exception_uninstall(uint8_t exc_id);
void neorv32_rte_print_hw_config(void);
 
#endif // neorv32_rte_h
/source/neorv32_rte.c
43,8 → 43,10
#include "neorv32_rte.h"
 
// Privates
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
static void __neorv32_rte_print_hw_version(void) __attribute__((unused));
 
 
/**********************************************************************//**
151,11 → 153,13
**************************************************************************/
static void __neorv32_rte_debug_exc_handler(void) {
 
neorv32_uart_printf("\n\n\n<<< NEORV32 Runtime Environment >>>\n");
neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");
 
neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));
 
uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
register uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC);
register uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST);
 
if (exc_cause & 0x80000000) {
neorv32_uart_printf("INTERRUPT");
162,8 → 166,14
}
else {
neorv32_uart_printf("EXCEPTION");
if ((trans_cmd & (1 << 1)) == 0) {
return_addr -= 4;
}
else {
return_addr -= 2;
}
}
neorv32_uart_printf(" at instruction address: 0x%x\n", neorv32_cpu_csr_read(CSR_MEPC));
neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr);
 
neorv32_uart_printf("Cause: ");
switch (exc_cause) {
190,18 → 200,179
neorv32_uart_printf("\nFaulting address");
}
neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST);
neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd);
 
if (trans_cmd & (1 << 1)) {
neorv32_uart_printf("(uncompr.)\n");
if ((trans_cmd & (1 << 1)) == 0) {
neorv32_uart_printf("(decompressed)\n");
}
 
neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
 
neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n");
}
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Print hardware configuration information via UART
**************************************************************************/
void neorv32_rte_print_hw_config(void) {
 
uint32_t tmp;
int i;
char c;
 
neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
 
// CPU configuration
neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
// Hart ID
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
 
// HW version
neorv32_uart_printf("Hardware version: ");
__neorv32_rte_print_hw_version();
neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
 
// CPU architecture
neorv32_uart_printf("Architecture: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
tmp = (tmp >> 30) & 0x03;
if (tmp == 0) {
neorv32_uart_printf("unknown");
}
if (tmp == 1) {
neorv32_uart_printf("RV32");
}
if (tmp == 2) {
neorv32_uart_printf("RV64");
}
if (tmp == 3) {
neorv32_uart_printf("RV128");
}
// CPU extensions
neorv32_uart_printf("\nCPU extensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
for (i=0; i<26; i++) {
if (tmp & (1 << i)) {
c = (char)('A' + i);
neorv32_uart_putc(c);
neorv32_uart_putc(' ');
}
}
neorv32_uart_printf("(0x%x)\n", tmp);
 
// Performance counters
neorv32_uart_printf("CNT & time CSRs: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));
 
// Clock speed
neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));
 
// Memory configuration
neorv32_uart_printf("\n-- Memory Configuration --\n");
 
uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);
uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);
neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
neorv32_uart_printf("Internal IMEM: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));
neorv32_uart_printf("Internal IMEM as ROM: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));
 
size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);
base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
neorv32_uart_printf("Internal DMEM: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));
 
neorv32_uart_printf("Bootloader: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));
 
neorv32_uart_printf("External interface: ");
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));
 
// peripherals
neorv32_uart_printf("\n-- Peripherals --\n");
tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
 
neorv32_uart_printf("GPIO: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
 
neorv32_uart_printf("MTIME: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
 
neorv32_uart_printf("UART: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
 
neorv32_uart_printf("SPI: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
 
neorv32_uart_printf("TWI: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
 
neorv32_uart_printf("PWM: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
 
neorv32_uart_printf("WDT: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
 
neorv32_uart_printf("CLIC: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
 
neorv32_uart_printf("TRNG: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
 
neorv32_uart_printf("DEVNULL: ");
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
}
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Private function to print true or false.
* @note This function is used by neorv32_rte_print_hw_config(void) only.
*
* @param[in] state Print TRUE when !=0, print FALSE when 0
**************************************************************************/
static void __neorv32_rte_print_true_false(int state) {
 
if (state) {
neorv32_uart_printf("True\n");
}
else {
neorv32_uart_printf("(compr.)\n");
neorv32_uart_printf("False\n");
}
}
 
neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MSCRATCH));
 
neorv32_uart_printf("\n<<</NEORV32 Runtime Environment >>>\n\n\n");
/**********************************************************************//**
* NEORV32 runtime environment: Private function to show the processor version in human-readable format.
* @note This function is used by neorv32_rte_print_hw_config(void) only.
**************************************************************************/
static void __neorv32_rte_print_hw_version(void) {
 
uint32_t i;
char tmp, cnt;
uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
 
for (i=0; i<4; i++) {
 
tmp = (char)(version >> (24 - 8*i));
 
// serial division
cnt = 0;
while (tmp >= 10) {
tmp = tmp - 10;
cnt++;
}
 
if (cnt) {
neorv32_uart_putc('0' + cnt);
}
neorv32_uart_putc('0' + tmp);
if (i < 3) {
neorv32_uart_putc('.');
}
}
}
 

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