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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

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    /neorv32/trunk/sw/lib
    from Rev 73 to Rev 74
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Rev 73 → Rev 74

/include/neorv32.h
502,35 → 502,35
* Trap codes from mcause CSR.
**************************************************************************/
enum NEORV32_EXCEPTION_CODES_enum {
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */
TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */
TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */
TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */
TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */
TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */
TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */
TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
TRAP_CODE_FIRQ_3 = 0x80000013, /**< 1.19: Fast interrupt channel 3 */
TRAP_CODE_FIRQ_4 = 0x80000014, /**< 1.20: Fast interrupt channel 4 */
TRAP_CODE_FIRQ_5 = 0x80000015, /**< 1.21: Fast interrupt channel 5 */
TRAP_CODE_FIRQ_6 = 0x80000016, /**< 1.22: Fast interrupt channel 6 */
TRAP_CODE_FIRQ_7 = 0x80000017, /**< 1.23: Fast interrupt channel 7 */
TRAP_CODE_FIRQ_8 = 0x80000018, /**< 1.24: Fast interrupt channel 8 */
TRAP_CODE_FIRQ_9 = 0x80000019, /**< 1.25: Fast interrupt channel 9 */
TRAP_CODE_FIRQ_10 = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */
TRAP_CODE_FIRQ_11 = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */
TRAP_CODE_FIRQ_12 = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */
TRAP_CODE_FIRQ_13 = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */
TRAP_CODE_FIRQ_14 = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */
TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */
TRAP_CODE_I_MISALIGNED = 0x00000000UL, /**< 0.0: Instruction address misaligned */
TRAP_CODE_I_ACCESS = 0x00000001UL, /**< 0.1: Instruction (bus) access fault */
TRAP_CODE_I_ILLEGAL = 0x00000002UL, /**< 0.2: Illegal instruction */
TRAP_CODE_BREAKPOINT = 0x00000003UL, /**< 0.3: Breakpoint (EBREAK instruction) */
TRAP_CODE_L_MISALIGNED = 0x00000004UL, /**< 0.4: Load address misaligned */
TRAP_CODE_L_ACCESS = 0x00000005UL, /**< 0.5: Load (bus) access fault */
TRAP_CODE_S_MISALIGNED = 0x00000006UL, /**< 0.6: Store address misaligned */
TRAP_CODE_S_ACCESS = 0x00000007UL, /**< 0.7: Store (bus) access fault */
TRAP_CODE_UENV_CALL = 0x00000008UL, /**< 0.8: Environment call from user mode (ECALL instruction) */
TRAP_CODE_MENV_CALL = 0x0000000bUL, /**< 0.11: Environment call from machine mode (ECALL instruction) */
TRAP_CODE_MSI = 0x80000003UL, /**< 1.3: Machine software interrupt */
TRAP_CODE_MTI = 0x80000007UL, /**< 1.7: Machine timer interrupt */
TRAP_CODE_MEI = 0x8000000bUL, /**< 1.11: Machine external interrupt */
TRAP_CODE_FIRQ_0 = 0x80000010UL, /**< 1.16: Fast interrupt channel 0 */
TRAP_CODE_FIRQ_1 = 0x80000011UL, /**< 1.17: Fast interrupt channel 1 */
TRAP_CODE_FIRQ_2 = 0x80000012UL, /**< 1.18: Fast interrupt channel 2 */
TRAP_CODE_FIRQ_3 = 0x80000013UL, /**< 1.19: Fast interrupt channel 3 */
TRAP_CODE_FIRQ_4 = 0x80000014UL, /**< 1.20: Fast interrupt channel 4 */
TRAP_CODE_FIRQ_5 = 0x80000015UL, /**< 1.21: Fast interrupt channel 5 */
TRAP_CODE_FIRQ_6 = 0x80000016UL, /**< 1.22: Fast interrupt channel 6 */
TRAP_CODE_FIRQ_7 = 0x80000017UL, /**< 1.23: Fast interrupt channel 7 */
TRAP_CODE_FIRQ_8 = 0x80000018UL, /**< 1.24: Fast interrupt channel 8 */
TRAP_CODE_FIRQ_9 = 0x80000019UL, /**< 1.25: Fast interrupt channel 9 */
TRAP_CODE_FIRQ_10 = 0x8000001aUL, /**< 1.26: Fast interrupt channel 10 */
TRAP_CODE_FIRQ_11 = 0x8000001bUL, /**< 1.27: Fast interrupt channel 11 */
TRAP_CODE_FIRQ_12 = 0x8000001cUL, /**< 1.28: Fast interrupt channel 12 */
TRAP_CODE_FIRQ_13 = 0x8000001dUL, /**< 1.29: Fast interrupt channel 13 */
TRAP_CODE_FIRQ_14 = 0x8000001eUL, /**< 1.30: Fast interrupt channel 14 */
TRAP_CODE_FIRQ_15 = 0x8000001fUL /**< 1.31: Fast interrupt channel 15 */
};
 
 
664,7 → 664,7
 
 
// ############################################################################################################################
// On-Chip Debugger (should NOT be used by application software)
// On-Chip Debugger (should NOT be used by application software at all!)
// ############################################################################################################################
/**@{*/
/** on-chip debugger - debug module prototype */
678,8 → 678,11
const uint32_t reserved3[31]; /**< offset 388..508: reserved */
} neorv32_dm_t;
 
/** on-chip debugger debug module base address */
#define NEORV32_DM_BASE (0XFFFFF800UL)
 
/** on-chip debugger debug module hardware access (#neorv32_dm_t) */
#define NEORV32_DM (*((volatile neorv32_dm_t*) (0XFFFFF800UL)))
#define NEORV32_DM (*((volatile neorv32_dm_t*) (NEORV32_DM_BASE)))
 
/** on-chip debugger debug module control and status register bits */
enum NEORV32_OCD_DM_SREG_enum {
730,8 → 733,11
uint32_t REG[32]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */
} neorv32_cfs_t;
 
/** CFS base address */
#define NEORV32_CFS_BASE (0xFFFFFE00UL)
 
/** CFS module hardware access (#neorv32_cfs_t) */
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (0xFFFFFE00UL)))
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE)))
/**@}*/
 
 
745,8 → 751,11
uint32_t DUTY[15]; /**< offset 4..60: duty cycle register 0..14 */
} neorv32_pwm_t;
 
/** PWM module base address */
#define NEORV32_PWM_BASE (0xFFFFFE80UL)
 
/** PWM module hardware access (#neorv32_pwm_t) */
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (0xFFFFFE80UL)))
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (NEORV32_PWM_BASE)))
 
/** PWM control register bits */
enum NEORV32_PWM_CTRL_enum {
773,8 → 782,11
uint32_t DATA[8]; /**< offset 32..60: stream link data channel 0..7 */
} neorv32_slink_t;
 
/** SLINK module base address */
#define NEORV32_SLINK_BASE (0xFFFFFEC0UL)
 
/** SLINK module hardware access (#neorv32_slink_t) */
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (0xFFFFFEC0UL)))
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (NEORV32_SLINK_BASE)))
 
/** SLINK control register bits */
enum NEORV32_SLINK_CTRL_enum {
885,8 → 897,11
uint32_t DATA_HI; /**< offset 12: SPI data register high */
} neorv32_xip_t;
 
/** XIP module base address */
#define NEORV32_XIP_BASE (0xFFFFFF40UL)
 
/** XIP module hardware access (#neorv32_xip_t) */
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (0xFFFFFF40UL)))
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (NEORV32_XIP_BASE)))
 
/** XIP control/data register bits */
enum NEORV32_XIP_CTRL_enum {
926,8 → 941,11
const uint32_t reserved; /**< offset 12: reserved */
} neorv32_gptmr_t;
 
/** GPTMR module base address */
#define NEORV32_GPTMR_BASE (0xFFFFFF60UL)
 
/** GPTMR module hardware access (#neorv32_gptmr_t) */
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (0xFFFFFF60UL)))
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (NEORV32_GPTMR_BASE)))
 
/** GPTMR control/data register bits */
enum NEORV32_GPTMR_CTRL_enum {
949,8 → 967,11
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
} neorv32_buskeeper_t;
 
/** BUSKEEPER module base address */
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF7CUL)
 
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE)))
 
/** BUSKEEPER control/data register bits */
enum NEORV32_BUSKEEPER_CTRL_enum {
972,8 → 993,11
const uint32_t reserved; /**< offset 12: reserved */
} neorv32_xirq_t;
 
/** XIRQ module base address */
#define NEORV32_XIRQ_BASE (0xFFFFFF80UL)
 
/** XIRQ module hardware access (#neorv32_xirq_t) */
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (0xFFFFFF80UL)))
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (NEORV32_XIRQ_BASE)))
/**@}*/
 
 
989,8 → 1013,11
uint32_t TIMECMP_HI; /**< offset 12: compare register high word */
} neorv32_mtime_t;
 
/** MTIME module base address */
#define NEORV32_MTIME_BASE (0xFFFFFF90UL)
 
/** MTIME module hardware access (#neorv32_mtime_t) */
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (0xFFFFFF90UL)))
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (NEORV32_MTIME_BASE)))
/**@}*/
 
 
1004,8 → 1031,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */
} neorv32_uart0_t;
 
/** UART0 module base address */
#define NEORV32_UART0_BASE (0xFFFFFFA0UL)
 
/** UART0 module hardware access (#neorv32_uart0_t) */
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (0xFFFFFFA0UL)))
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (NEORV32_UART0_BASE)))
 
/** UART1 module prototype */
typedef struct __attribute__((packed,aligned(4))) {
1013,8 → 1043,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */
} neorv32_uart1_t;
 
/** UART1 module base address */
#define NEORV32_UART1_BASE (0xFFFFFFD0UL)
 
/** UART1 module hardware access (#neorv32_uart1_t) */
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (0xFFFFFFD0UL)))
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (NEORV32_UART1_BASE)))
 
/** UART0/UART1 control register bits */
enum NEORV32_UART_CTRL_enum {
1090,8 → 1123,11
uint32_t DATA; /**< offset 4: data register */
} neorv32_spi_t;
 
/** SPI module base address */
#define NEORV32_SPI_BASE (0xFFFFFFA8UL)
 
/** SPI module hardware access (#neorv32_spi_t) */
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (0xFFFFFFA8UL)))
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE)))
 
/** SPI control register bits */
enum NEORV32_SPI_CTRL_enum {
1128,8 → 1164,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */
} neorv32_twi_t;
 
/** TWI module base address */
#define NEORV32_TWI_BASE (0xFFFFFFB0UL)
 
/** TWI module hardware access (#neorv32_twi_t) */
#define NEORV32_TWI (*((volatile neorv32_twi_t*) (0xFFFFFFB0UL)))
#define NEORV32_TWI (*((volatile neorv32_twi_t*) (NEORV32_TWI_BASE)))
 
/** TWI control register bits */
enum NEORV32_TWI_CTRL_enum {
1162,8 → 1201,11
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */
} neorv32_trng_t;
 
/** TRNG module base address */
#define NEORV32_TRNG_BASE (0xFFFFFFB8UL)
 
/** TRNG module hardware access (#neorv32_trng_t) */
#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (0xFFFFFFB8UL)))
#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (NEORV32_TRNG_BASE)))
 
/** TRNG control/data register bits */
enum NEORV32_TRNG_CTRL_enum {
1185,8 → 1227,11
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */
} neorv32_wdt_t;
 
/** WDT module base address */
#define NEORV32_WDT_BASE (0xFFFFFFBCUL)
 
/** WDT module hardware access (#neorv32_wdt_t) */
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (0xFFFFFFBCUL)))
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (NEORV32_WDT_BASE)))
 
/** WTD control register bits */
enum NEORV32_WDT_CTRL_enum {
1217,8 → 1262,11
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */
} neorv32_gpio_t;
 
/** GPIO module base address */
#define NEORV32_GPIO_BASE (0xFFFFFFC0UL)
 
/** GPIO module hardware access (#neorv32_gpio_t) */
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (0xFFFFFFC0UL)))
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (NEORV32_GPIO_BASE)))
/**@}*/
 
 
1232,8 → 1280,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
} neorv32_neoled_t;
 
/** NEOLED module base address */
#define NEORV32_NEOLED_BASE (0xFFFFFFD8UL)
 
/** NEOLED module hardware access (#neorv32_neoled_t) */
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (0xFFFFFFD8UL)))
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (NEORV32_NEOLED_BASE)))
 
/** NEOLED control register bits */
enum NEORV32_NEOLED_CTRL_enum {
1292,8 → 1343,11
const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */
} neorv32_sysinfo_t;
 
/** SYSINFO module base address */
#define NEORV32_SYSINFO_BASE (0xFFFFFFE0UL)
 
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL)))
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)))
 
/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */
enum NEORV32_SYSINFO_SOC_enum {
/include/neorv32_cfs.h
35,11 → 35,10
 
/**********************************************************************//**
* @file neorv32_cfs.h
* @author Stephan Nolting
* @brief Custom Functions Subsystem (CFS)) HW driver header file.
*
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware.
* @warning Hence, the CFS designer has to provide the actual driver functions.
* @warning The CFS designer has to provide the actual driver functions.
*
* @note These functions should only be used if the CFS was synthesized (IO_CFS_EN = true).
**************************************************************************/
/include/neorv32_cpu.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_cpu.h
* @author Stephan Nolting
* @brief CPU Core Functions HW driver header file.
**************************************************************************/
 
43,17 → 42,17
#define neorv32_cpu_h
 
// prototypes
int neorv32_cpu_irq_enable(uint8_t irq_sel);
int neorv32_cpu_irq_disable(uint8_t irq_sel);
int neorv32_cpu_irq_enable(uint8_t irq_sel);
int neorv32_cpu_irq_disable(uint8_t irq_sel);
uint64_t neorv32_cpu_get_cycle(void);
void neorv32_cpu_set_mcycle(uint64_t value);
void neorv32_cpu_set_mcycle(uint64_t value);
uint64_t neorv32_cpu_get_instret(void);
void neorv32_cpu_set_minstret(uint64_t value);
void neorv32_cpu_set_minstret(uint64_t value);
uint64_t neorv32_cpu_get_systime(void);
void neorv32_cpu_delay_ms(uint32_t time_ms);
void neorv32_cpu_delay_ms(uint32_t time_ms);
uint32_t neorv32_cpu_pmp_get_num_regions(void);
uint32_t neorv32_cpu_pmp_get_granularity(void);
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config);
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config);
uint32_t neorv32_cpu_hpm_get_counters(void);
uint32_t neorv32_cpu_hpm_get_size(void);
 
/include/neorv32_cpu_cfu.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_cpu_cfu.h
* @author Stephan Nolting
* @brief CPU Core custom functions unit HW driver header file.
**************************************************************************/
 
47,7 → 46,7
 
 
/**********************************************************************//**
* @name CFU custom instructions (intrinsic)
* @name CFU custom instructions ("intrinsics")
**************************************************************************/
/**@{*/
/** CFU custom instruction 0 (funct3 = 000) */
/include/neorv32_gpio.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_gpio.h
* @author Stephan Nolting
* @brief General purpose input/output port unit (GPIO) HW driver header file.
*
* @note These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true).
/include/neorv32_gptmr.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_gptmr.h
* @author Stephan Nolting
* @brief General purpose timer (GPTMR) HW driver header file.
*
* @note These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true).
45,7 → 44,7
#define neorv32_gptmr_h
 
// prototypes
int neorv32_gptmr_available(void);
int neorv32_gptmr_available(void);
void neorv32_gptmr_setup(uint8_t prsc, uint8_t mode, uint32_t threshold);
void neorv32_gptmr_disable(void);
void neorv32_gptmr_enable(void);
/include/neorv32_intrinsics.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_intrinsics.h
* @author Stephan Nolting, SaxonSoc contributors, Google-CFU
* @brief Helper functions and macros for custom "intrinsics" / instructions.
**************************************************************************/
 
/include/neorv32_mtime.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_mtime.h
* @author Stephan Nolting
* @brief Machine System Timer (MTIME) HW driver header file.
*
* @note These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true).
45,10 → 44,10
#define neorv32_mtime_h
 
// prototypes
int neorv32_mtime_available(void);
void neorv32_mtime_set_time(uint64_t time);
int neorv32_mtime_available(void);
void neorv32_mtime_set_time(uint64_t time);
uint64_t neorv32_mtime_get_time(void);
void neorv32_mtime_set_timecmp(uint64_t timecmp);
void neorv32_mtime_set_timecmp(uint64_t timecmp);
uint64_t neorv32_mtime_get_timecmp(void);
 
#endif // neorv32_mtime_h
/include/neorv32_neoled.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_neoled.h
* @author Stephan Nolting
* @brief Smart LED Interface (NEOLED) HW driver header file.
*
* @note These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true).
45,15 → 44,15
#define neorv32_neoled_h
 
// prototypes
int neorv32_neoled_available(void);
void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one);
void neorv32_neoled_setup_ws2812(void);
void neorv32_neoled_set_mode(uint32_t mode);
void neorv32_neoled_strobe_blocking(void);
void neorv32_neoled_strobe_nonblocking(void);
void neorv32_neoled_enable(void);
void neorv32_neoled_disable(void);
void neorv32_neoled_write_blocking(uint32_t data);
int neorv32_neoled_available(void);
void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one);
void neorv32_neoled_setup_ws2812(void);
void neorv32_neoled_set_mode(uint32_t mode);
void neorv32_neoled_strobe_blocking(void);
void neorv32_neoled_strobe_nonblocking(void);
void neorv32_neoled_enable(void);
void neorv32_neoled_disable(void);
void neorv32_neoled_write_blocking(uint32_t data);
uint32_t neorv32_neoled_get_buffer_size(void);
 
 
/include/neorv32_pwm.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_pwm.h
* @author Stephan Nolting
* @brief Pulse-Width Modulation Controller (PWM) HW driver header file.
*
* @note These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true).
45,12 → 44,12
#define neorv32_pwm_h
 
// prototypes
int neorv32_pwm_available(void);
void neorv32_pwm_setup(uint8_t prsc);
void neorv32_pwm_disable(void);
void neorv32_pwm_enable(void);
int neorv32_pmw_get_num_channels(void);
void neorv32_pwm_set(uint8_t channel, uint8_t duty);
int neorv32_pwm_available(void);
void neorv32_pwm_setup(uint8_t prsc);
void neorv32_pwm_disable(void);
void neorv32_pwm_enable(void);
int neorv32_pmw_get_num_channels(void);
void neorv32_pwm_set(uint8_t channel, uint8_t duty);
uint8_t neorv32_pwm_get(uint8_t channel);
 
#endif // neorv32_pwm_h
/include/neorv32_rte.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_rte.h
* @author Stephan Nolting
* @brief NEORV32 Runtime Environment.
**************************************************************************/
 
96,6 → 95,6
void neorv32_rte_print_license(void);
 
uint32_t neorv32_rte_get_compiler_isa(void);
int neorv32_rte_check_isa(int silent);
int neorv32_rte_check_isa(int silent);
 
#endif // neorv32_rte_h
/include/neorv32_slink.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_slink.h
* @author Stephan Nolting
* @brief Stream Link Interface HW driver header file.
**************************************************************************/
 
43,35 → 42,35
#define neorv32_slink_h
 
// prototypes
int neorv32_slink_available(void);
int neorv32_slink_available(void);
void neorv32_slink_enable(void);
void neorv32_slink_disable(void);
void neorv32_slink_rx_irq_config(int link_id, int irq_en, int irq_type);
void neorv32_slink_tx_irq_config(int link_id, int irq_en, int irq_type);
int neorv32_slink_get_rx_num(void);
int neorv32_slink_get_tx_num(void);
int neorv32_slink_get_rx_depth(void);
int neorv32_slink_get_tx_depth(void);
int neorv32_slink_check_rx_half_full(int link_id);
int neorv32_slink_check_tx_half_full(int link_id);
int neorv32_slink_get_rx_num(void);
int neorv32_slink_get_tx_num(void);
int neorv32_slink_get_rx_depth(void);
int neorv32_slink_get_tx_depth(void);
int neorv32_slink_check_rx_half_full(int link_id);
int neorv32_slink_check_tx_half_full(int link_id);
// non-blocking transmit
int neorv32_slink_tx0_nonblocking(uint32_t tx_data);
int neorv32_slink_tx1_nonblocking(uint32_t tx_data);
int neorv32_slink_tx2_nonblocking(uint32_t tx_data);
int neorv32_slink_tx3_nonblocking(uint32_t tx_data);
int neorv32_slink_tx4_nonblocking(uint32_t tx_data);
int neorv32_slink_tx5_nonblocking(uint32_t tx_data);
int neorv32_slink_tx6_nonblocking(uint32_t tx_data);
int neorv32_slink_tx7_nonblocking(uint32_t tx_data);
int neorv32_slink_tx0_nonblocking(uint32_t tx_data);
int neorv32_slink_tx1_nonblocking(uint32_t tx_data);
int neorv32_slink_tx2_nonblocking(uint32_t tx_data);
int neorv32_slink_tx3_nonblocking(uint32_t tx_data);
int neorv32_slink_tx4_nonblocking(uint32_t tx_data);
int neorv32_slink_tx5_nonblocking(uint32_t tx_data);
int neorv32_slink_tx6_nonblocking(uint32_t tx_data);
int neorv32_slink_tx7_nonblocking(uint32_t tx_data);
// non-blocking receive
int neorv32_slink_rx0_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx1_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx2_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx3_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx4_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx5_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx6_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx7_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx0_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx1_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx2_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx3_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx4_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx5_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx6_nonblocking(uint32_t *rx_data);
int neorv32_slink_rx7_nonblocking(uint32_t *rx_data);
 
 
/**********************************************************************//**
/include/neorv32_spi.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_spi.h
* @author Stephan Nolting
* @brief Serial peripheral interface controller (SPI) HW driver header file.
*
* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).
45,17 → 44,17
#define neorv32_spi_h
 
// prototypes
int neorv32_spi_available(void);
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size);
void neorv32_spi_disable(void);
void neorv32_spi_enable(void);
void neorv32_spi_highspeed_enable(void);
void neorv32_spi_highspeed_disable(void);
void neorv32_spi_cs_en(uint8_t cs);
void neorv32_spi_cs_dis(uint8_t cs);
int neorv32_spi_available(void);
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size);
void neorv32_spi_disable(void);
void neorv32_spi_enable(void);
void neorv32_spi_highspeed_enable(void);
void neorv32_spi_highspeed_disable(void);
void neorv32_spi_cs_en(uint8_t cs);
void neorv32_spi_cs_dis(uint8_t cs);
uint32_t neorv32_spi_trans(uint32_t tx_data);
void neorv32_spi_put_nonblocking(uint32_t tx_data);
void neorv32_spi_put_nonblocking(uint32_t tx_data);
uint32_t neorv32_spi_get_nonblocking(void);
int neorv32_spi_busy(void);
int neorv32_spi_busy(void);
 
#endif // neorv32_spi_h
/include/neorv32_trng.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_trng.h
* @author Stephan Nolting
* @brief True Random Number Generator (TRNG) HW driver header file.
*
* @note These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true).
45,9 → 44,9
#define neorv32_trng_h
 
// prototypes
int neorv32_trng_available(void);
int neorv32_trng_available(void);
void neorv32_trng_enable(void);
void neorv32_trng_disable(void);
int neorv32_trng_get(uint8_t *data);
int neorv32_trng_get(uint8_t *data);
 
#endif // neorv32_trng_h
/include/neorv32_twi.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_twi.h
* @author Stephan Nolting
* @brief Two-Wire Interface Controller (TWI) HW driver header file.
*
* @note These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true).
45,17 → 44,17
#define neorv32_twi_h
 
// prototypes
int neorv32_twi_available(void);
void neorv32_twi_setup(uint8_t prsc);
void neorv32_twi_disable(void);
void neorv32_twi_enable(void);
void neorv32_twi_mack_enable(void);
void neorv32_twi_mack_disable(void);
int neorv32_twi_busy(void);
int neorv32_twi_start_trans(uint8_t a);
int neorv32_twi_trans(uint8_t d);
int neorv32_twi_available(void);
void neorv32_twi_setup(uint8_t prsc);
void neorv32_twi_disable(void);
void neorv32_twi_enable(void);
void neorv32_twi_mack_enable(void);
void neorv32_twi_mack_disable(void);
int neorv32_twi_busy(void);
int neorv32_twi_start_trans(uint8_t a);
int neorv32_twi_trans(uint8_t d);
uint8_t neorv32_twi_get_data(void);
void neorv32_twi_generate_stop(void);
void neorv32_twi_generate_start(void);
void neorv32_twi_generate_stop(void);
void neorv32_twi_generate_start(void);
 
#endif // neorv32_twi_h
/include/neorv32_uart.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_uart.h
* @author Stephan Nolting
* @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file
*
* @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions.
/include/neorv32_wdt.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_wdt.h
* @author Stephan Nolting
* @brief Watchdog Timer (WDT) HW driver header file.
*
* @note These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true).
45,11 → 44,11
#define neorv32_wdt_h
 
// prototypes
int neorv32_wdt_available(void);
int neorv32_wdt_available(void);
void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock);
int neorv32_wdt_disable(void);
int neorv32_wdt_disable(void);
void neorv32_wdt_reset(void);
int neorv32_wdt_get_cause(void);
int neorv32_wdt_get_cause(void);
void neorv32_wdt_force(void);
 
#endif // neorv32_wdt_h
/include/neorv32_xip.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_xip.h
* @author Stephan Nolting
* @brief Execute in place module (XIP) HW driver header file.
*
* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
45,11 → 44,11
#define neorv32_xip_h
 
// prototypes
int neorv32_xip_available(void);
int neorv32_xip_init(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd);
int neorv32_xip_start(uint8_t abytes, uint32_t page_base);
int neorv32_xip_available(void);
int neorv32_xip_init(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd);
int neorv32_xip_start(uint8_t abytes, uint32_t page_base);
void neorv32_xip_highspeed_enable(void);
void neorv32_xip_highspeed_disable(void);
int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data);
int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data);
 
#endif // neorv32_xip_h
/include/neorv32_xirq.h
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_xirq.h
* @author Stephan Nolting
* @brief External Interrupt controller HW driver header file.
**************************************************************************/
 
43,17 → 42,16
#define neorv32_xirq_h
 
// prototypes
int neorv32_xirq_available(void);
int neorv32_xirq_setup(void);
int neorv32_xirq_available(void);
int neorv32_xirq_setup(void);
void neorv32_xirq_global_enable(void);
void neorv32_xirq_global_disable(void);
int neorv32_xirq_get_num(void);
int neorv32_xirq_get_num(void);
void neorv32_xirq_clear_pending(uint8_t ch);
void neorv32_xirq_channel_enable(uint8_t ch);
void neorv32_xirq_channel_disable(uint8_t ch);
int neorv32_xirq_install(uint8_t ch, void (*handler)(void));
int neorv32_xirq_uninstall(uint8_t ch);
 
int neorv32_xirq_install(uint8_t ch, void (*handler)(void));
int neorv32_xirq_uninstall(uint8_t ch);
 
 
#endif // neorv32_xirq_h
/source/neorv32_cfs.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_cfs.c
* @author Stephan Nolting
* @brief Custom Functions Subsystem (CFS) HW driver source file.
*
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware.
/source/neorv32_cpu.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_cpu.c
* @author Stephan Nolting
* @brief CPU Core Functions HW driver source file.
**************************************************************************/
 
/source/neorv32_cpu_cfu.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_cpu_cfu.c
* @author Stephan Nolting
* @brief CPU Core custom functions unit HW driver source file.
**************************************************************************/
 
/source/neorv32_gpio.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_gpio.c
* @author Stephan Nolting
* @brief General purpose input/output port unit (GPIO) HW driver source file.
*
* @note These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true).
/source/neorv32_gptmr.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_gptmr.c
* @author Stephan Nolting
* @brief General purpose timer (GPTMR) HW driver source file.
*
* @note These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true).
/source/neorv32_mtime.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_mtime.c
* @author Stephan Nolting
* @brief Machine System Timer (MTIME) HW driver source file.
*
* @note These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true).
/source/neorv32_neoled.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_neoled.c
* @author Stephan Nolting
* @brief Smart LED Interface (NEOLED) HW driver source file.
*
* @note These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true).
/source/neorv32_pwm.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_pwm.c
* @author Stephan Nolting
* @brief Pulse-Width Modulation Controller (PWM) HW driver source file.
*
* @note These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true).
/source/neorv32_rte.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_rte.c
* @author Stephan Nolting
* @brief NEORV32 Runtime Environment.
**************************************************************************/
 
67,14 → 66,20
// configure trap handler base address
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&__neorv32_rte_core));
 
// disable all IRQ channels
neorv32_cpu_csr_write(CSR_MIE, 0);
 
// clear all pending IRQs
neorv32_cpu_csr_write(CSR_MIP, 0);
 
// clear BUSKEEPER error flags
NEORV32_BUSKEEPER.CTRL = 0;
 
// install debug handler for all sources
uint8_t id;
for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
neorv32_rte_exception_uninstall(id); // this will configure the debug handler
}
 
// clear BUSKEEPER error flags
NEORV32_BUSKEEPER.CTRL = 0;
}
 
 
131,7 → 136,7
static void __attribute__((__interrupt__)) __attribute__((aligned(4))) __neorv32_rte_core(void) {
 
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // backup for later
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
 
// compute return address
140,12 → 145,12
// get low half word of faulting instruction
register uint32_t rte_trap_inst = neorv32_cpu_load_unsigned_half(rte_mepc);
 
if ((rte_trap_inst & 3) == 3) { // faulting instruction is uncompressed instruction
rte_mepc += 4;
rte_mepc += 4; // default: faulting instruction is uncompressed
if (neorv32_cpu_csr_read(CSR_MISA) & (1 << CSR_MISA_C)) { // C extension implemented?
if ((rte_trap_inst & 3) != 3) { // faulting instruction is compressed instruction
rte_mepc -= 2;
}
}
else { // faulting instruction is compressed instruction
rte_mepc += 2;
}
 
// store new return address
neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
746,7 → 751,6
// mask hardware features that are not used by software
uint32_t check = misa_hw & misa_sw;
 
//
if (check == misa_sw) {
return 0;
}
/source/neorv32_slink.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_slink.c
* @author Stephan Nolting
* @brief Stream Link Interface HW driver source file.
**************************************************************************/
 
/source/neorv32_spi.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_spi.c
* @author Stephan Nolting
* @brief Serial peripheral interface controller (SPI) HW driver source file.
*
* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).
/source/neorv32_trng.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_trng.c
* @author Stephan Nolting
* @brief True Random Number Generator (TRNG) HW driver source file.
*
* @note These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true).
/source/neorv32_twi.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_twi.c
* @author Stephan Nolting
* @brief Two-Wire Interface Controller (TWI) HW driver source file.
*
* @note These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true).
/source/neorv32_uart.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_uart.c
* @author Stephan Nolting
* @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver source file.
*
* @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions.
/source/neorv32_wdt.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_wdt.c
* @author Stephan Nolting
* @brief Watchdog Timer (WDT) HW driver source file.
*
* @note These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true).
/source/neorv32_xip.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_xip.c
* @author Stephan Nolting
* @brief Execute in place module (XIP) HW driver source file.
*
* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
/source/neorv32_xirq.c
35,7 → 35,6
 
/**********************************************************************//**
* @file neorv32_xirq.c
* @author Stephan Nolting
* @brief External Interrupt controller HW driver source file.
**************************************************************************/
 
/source/syscalls.c
19,7 → 19,6
 
/**********************************************************************//**
* @file syscalls.c
* @author Modified for the NEORV32 RISC-V Processor by Stephan Nolting
* @brief Newlib system calls
*
* @warning UART0 (if available) is used to read/write console data (STDIN, STDOUT, STDERR, ...).

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