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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw
    from Rev 10 to Rev 11
    ↔ Reverse comparison
  •

Rev 10 → Rev 11

/bootloader/bootloader.c
67,7 → 67,7
/** Bootloader status LED at GPIO output port (0..15) */
#define STATUS_LED (0)
/** SPI flash boot image base address */
#define SPI_FLASH_BOOT_ADR (0x00040000)
#define SPI_FLASH_BOOT_ADR (0x00800000)
/** SPI flash chip select at spi_csn_o */
#define SPI_FLASH_CS (0)
/** Default SPI flash clock prescaler for serial peripheral interface */
171,6 → 171,9
// Processor hardware initialization
// ------------------------------------------------
 
// reset system time
neorv32_mtime_set_time(0);
 
// deactivate unused IO devices
neorv32_clic_disable();
neorv32_pwm_disable();
/common/crt0.S
218,10 → 218,10
// Go to endless sleep mode if main returns
// *********************************************************
__crt0_this_is_the_end:
wfi // in case Ziscr is not available -> processor should stall here
csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
wfi
j .
__crt0_this_is_the_end_end:
j __crt0_this_is_the_end_end // in case Ziscr is not available
 
 
// *********************************************************
/example/cpu_test/main.c
119,6 → 119,12
int cnt_ok = 0;
int cnt_test = 0;
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cpu_systime;
 
 
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0;
139,6 → 145,7
neorv32_uart_setup(BAUD_RATE, 0, 0);
 
 
neorv32_mtime_set_time(0);
// set CMP of machine system timer MTIME to max to prevent an IRQ
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFL;
neorv32_mtime_set_timecmp(mtime_cmp_max);
146,11 → 153,14
// intro
neorv32_uart_printf("\n\n------ CPU TEST ------\n\n");
 
// show project credits
neorv32_rte_print_credits();
 
// show full HW config report
neorv32_rte_print_hw_config();
 
// intro2
neorv32_uart_printf("\n\nNEORV32 exceptions and interrupts test program\n\n");
neorv32_uart_printf("\n\nStarting tests...\n\n");
 
// install exception handler functions
int install_err = 0;
197,8 → 207,72
 
 
// ----------------------------------------------------------
// Test counter CSR access for mcycle[h]
// ----------------------------------------------------------
neorv32_uart_printf("MCYCLE[H]: ");
cnt_test++;
 
neorv32_cpu_csr_write(CSR_MCYCLE, 0x1BCD1234);
neorv32_cpu_csr_write(CSR_MCYCLEH, 0x22334455);
 
if (((neorv32_cpu_csr_read(CSR_MCYCLE) & 0xffff0000L) == 0x1BCD0000) &&
(neorv32_cpu_csr_read(CSR_MCYCLEH) == 0x22334455)) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
else {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
 
 
// ----------------------------------------------------------
// Test counter CSR access for minstret[h]
// ----------------------------------------------------------
neorv32_uart_printf("MINSTRET[H]: ");
cnt_test++;
 
neorv32_cpu_csr_write(CSR_MINSTRET, 0x11224499);
neorv32_cpu_csr_write(CSR_MINSTRETH, 0x00110011);
 
if (((neorv32_cpu_csr_read(CSR_MINSTRET) & 0xffff0000L) == 0x11220000) &&
(neorv32_cpu_csr_read(CSR_MINSTRETH) == 0x00110011)) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
else {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
 
 
// ----------------------------------------------------------
// Test time[h] (must be == MTIME)
// ----------------------------------------------------------
neorv32_uart_printf("TIME[H]: ");
cnt_test++;
 
cpu_systime.uint32[0] = neorv32_cpu_csr_read(CSR_TIME);
cpu_systime.uint32[1] = neorv32_cpu_csr_read(CSR_TIMEH);
cpu_systime.uint64 &= 0xFFFFFFFFFFFF0000LL;
 
uint64_t mtime_systime = neorv32_mtime_get_time() & 0xFFFFFFFFFFFF0000LL;
 
if (cpu_systime.uint64 == mtime_systime) {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
else {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
 
 
// ----------------------------------------------------------
// Test fence instructions - make sure CPU does not crash here and throws no exception
// a more complex test is provided by the RISC-V compliance test
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("FENCE(.I): ");
cnt_test++;
asm volatile ("fence");
212,12 → 286,12
neorv32_uart_printf("ok\n");
cnt_ok++;
}
exception_handler_answer = 0;
 
 
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC I_ALIGN: ");
 
// skip if C-mode is not implemented
237,11 → 311,10
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
}
else {
neorv32_uart_printf("skipped (no EXC I_ALIGN possible in C-mode)\n");
neorv32_uart_printf("skipped (not possible when C-EXT enabled)\n");
}
 
 
248,6 → 321,7
// ----------------------------------------------------------
// Instruction access fault
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC I_ACC: ");
cnt_test++;
 
263,7 → 337,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
270,6 → 343,7
// ----------------------------------------------------------
// Illegal instruction
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC I_ILLEG: ");
cnt_test++;
 
291,7 → 365,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
298,6 → 371,7
// ----------------------------------------------------------
// Breakpoint instruction
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC BREAK: ");
cnt_test++;
 
312,7 → 386,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
319,6 → 392,7
// ----------------------------------------------------------
// Unaligned load address
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC L_ALIGN: ");
cnt_test++;
 
334,7 → 408,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
341,6 → 414,7
// ----------------------------------------------------------
// Load access fault
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC L_ACC: ");
cnt_test++;
 
356,7 → 430,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
363,6 → 436,7
// ----------------------------------------------------------
// Unaligned store address
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC S_ALIGN: ");
cnt_test++;
 
378,7 → 452,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
385,6 → 458,7
// ----------------------------------------------------------
// Store access fault
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC S_ACC: ");
cnt_test++;
 
400,7 → 474,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
407,6 → 480,7
// ----------------------------------------------------------
// Environment call
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("EXC ENVCALL: ");
cnt_test++;
 
421,7 → 495,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
428,6 → 501,7
// ----------------------------------------------------------
// Machine software interrupt
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("IRQ MSI: ");
cnt_test++;
 
443,7 → 517,6
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
450,6 → 523,7
// ----------------------------------------------------------
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("IRQ MTI: ");
cnt_test++;
 
471,13 → 545,16
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
// no more mtime interrupts
neorv32_mtime_set_timecmp(-1);
 
 
// ----------------------------------------------------------
// Machine external interrupt (via CLIC)
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("IRQ MEI: ");
cnt_test++;
 
499,10 → 576,36
neorv32_uart_printf("fail\n");
cnt_fail++;
}
exception_handler_answer = 0;
#endif
 
 
// ----------------------------------------------------------
// Test WFI ("sleep") instructions
// ----------------------------------------------------------
exception_handler_answer = 0;
neorv32_uart_printf("WFI: ");
cnt_test++;
 
// program timer to wake up
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 1000);
 
// put CPU into sleep mode
asm volatile ("wfi");
 
if (exception_handler_answer != ANSWER_MTI) {
neorv32_uart_printf("fail\n");
cnt_fail++;
}
else {
neorv32_uart_printf("ok\n");
cnt_ok++;
}
 
 
 
 
 
 
// error report
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail);
 
/lib/include/neorv32.h
71,17 → 71,17
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
 
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/-): Machine cycle counter low word */
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/-): Machine instructions-retired counter low word */
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/-): Machine cycle counter high word */
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/-): Machine instructions-retired counter high word */
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
 
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word */
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word*/
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME) */
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word */
 
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word */
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word*/
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME) */
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */
 
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
129,10 → 129,10
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MISA_enum {
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-), can be switched on/off */
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-), can be switched on/off */
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
324,17 → 324,17
* @name IO Device: Machine System Timer (MTIME)
**************************************************************************/
/**@{*/
/** MTIME (time register) low word (r/-) */
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL))
/** MTIME (time register) high word (r/-) */
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL))
/** MTIME (time register) low word (r/w) */
#define MTIME_LO (*(IO_REG32 0xFFFFFF90UL))
/** MTIME (time register) high word (r/w) */
#define MTIME_HI (*(IO_REG32 0xFFFFFF94UL))
/** MTIMECMP (time compare register) low word (r/w) */
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
/** MTIMECMP (time register) high word (r/w) */
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
 
/** MTIME (time register) 64-bit access (r/-) */
#define MTIME (*(IO_ROM64 (&MTIME_LO)))
/** MTIME (time register) 64-bit access (r/w) */
#define MTIME (*(IO_REG64 (&MTIME_LO)))
/** MTIMECMP (time compare register) low word (r/w) */
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO)))
/**@}*/
/lib/include/neorv32_cpu.h
43,7 → 43,6
#define neorv32_cpu_h
 
// prototypes
int neorv32_cpu_switch_extension(int sel, int state);
int neorv32_cpu_irq_enable(uint8_t irq_sel);
int neorv32_cpu_irq_disable(uint8_t irq_sel);
void neorv32_cpu_delay_ms(uint32_t time_ms);
/lib/include/neorv32_mtime.h
46,6 → 46,7
 
// prototypes
int neorv32_mtime_available(void);
void neorv32_mtime_set_time(uint64_t time);
uint64_t neorv32_mtime_get_time(void);
void neorv32_mtime_set_timecmp(uint64_t timecmp);
uint64_t neorv32_mtime_get_timecmp(void);
/lib/include/neorv32_rte.h
46,6 → 46,8
void neorv32_rte_enable_debug_mode(void);
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void));
int neorv32_rte_exception_uninstall(uint8_t exc_id);
 
void neorv32_rte_print_hw_config(void);
void neorv32_rte_print_credits(void);
 
#endif // neorv32_rte_h
/lib/source/neorv32_cpu.c
44,54 → 44,6
 
 
/**********************************************************************//**
* Enable/disable CPU extension during runtime via the 'misa' CSR.
*
* @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions.
*
* @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum.
* @param[in] state Set 1 to enable the selected extension, set 0 to disable it;
* return 0 if success, 1 if error (invalid sel or extension cannot be enabled).
**************************************************************************/
int neorv32_cpu_switch_extension(int sel, int state) {
 
// get current misa setting
uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA);
uint32_t misa_prev = misa_curr;
 
// abort if misa.z is cleared
if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) {
return 1;
}
 
// out of range?
if (sel > 25) {
return 1;
}
 
// enable/disable selected extension
if (state & 1) {
misa_curr |= (1 << sel);
}
else {
misa_curr &= ~(1 << sel);
}
 
// try updating misa
neorv32_cpu_csr_write(CSR_MISA, misa_curr);
asm volatile("fence.i"); // required to flush prefetch buffers
asm volatile("nop");
 
// dit it work?
if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) {
return 1; // nope
}
else {
return 0; // fine
}
}
 
 
/**********************************************************************//**
* Enable specific CPU interrupt.
*
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
/lib/source/neorv32_mtime.c
62,10 → 62,23
 
 
/**********************************************************************//**
* Get current system time since reset.
* Set current system time.
*
* @note The MTIME timer increments with the primary processor clock.
*
* @param[in] time New system time (uint64_t)
**************************************************************************/
void neorv32_mtime_set_time(uint64_t time) {
 
MTIME = time;
}
 
 
/**********************************************************************//**
* Get current system time.
*
* @note The MTIME timer increments with the primary processor clock.
*
* @return Current system time (uint64_t)
**************************************************************************/
uint64_t neorv32_mtime_get_time(void) {
/lib/source/neorv32_rte.c
373,3 → 373,16
}
}
}
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Print project credits
**************************************************************************/
void neorv32_rte_print_credits(void) {
 
neorv32_uart_print("\n\nThe NEORV32 Processor Project\n"
"by Stephan Nolting\n"
"https://github.com/stnolting/neorv32\n"
"made in Hannover, Germany\n\n");
}
 

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