OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/lib/include/neorv32.h
81,6 → 81,7
 
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
 
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word - only 20-bit wide!*/
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */
 
242,6 → 243,15
 
 
/**********************************************************************//**
* @name IO Device: Dummy Device (DEVNULL)
**************************************************************************/
/**@{*/
/** DEVNULL data register (r/w) */
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFF88UL))
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: Watchdog Timer (WDT)
**************************************************************************/
/**@{*/
455,15 → 465,6
 
 
/**********************************************************************//**
* @name IO Device: Dummy Device (DEVNULL)
**************************************************************************/
/**@{*/
/** DEVNULL data register (r/w) */
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFC8UL))
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: System Configuration Info Memory (SYSINFO)
**************************************************************************/
/**@{*/
/lib/source/neorv32_cpu.c
242,15 → 242,14
* Switch from privilege mode MACHINE to privilege mode USER.
*
* @note This function requires the U extension to be implemented.
* @note Maybe you should do a fencei after this.
* @note Maybe you should do a fence.i after this.
**************************************************************************/
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
 
register uint32_t mask = (1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L);
mask = ~mask;
asm volatile ("csrrc zero, mstatus, %[input_j]" : : [input_j] "r" (mask));
 
// return and switch to user mode
// return switching to user mode
asm volatile ("csrw mepc, ra");
asm volatile ("mret");
}
/lib/source/neorv32_rte.c
82,7 → 82,7
*
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
* return 0 if success, 1 if error (invalid id or targeted exception not supported).
* @return 0 if success, 1 if error (invalid id or targeted exception not supported).
**************************************************************************/
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
 
109,7 → 109,7
* and/or the global interrupt enable bit mstatus.mie via neorv32_cpu_dint(void).
*
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
* return 0 if success, 1 if error (invalid id or targeted exception not supported).
* @return 0 if success, 1 if error (invalid id or targeted exception not supported).
**************************************************************************/
int neorv32_rte_exception_uninstall(uint8_t id) {
 
201,19 → 201,19
case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint"); break;
case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break;
case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break;
case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break;
case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call from M-mode"); break;
case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call"); break;
case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt channel 0"); break;
case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt channel 1"); break;
case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break;
case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break;
case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt 0"); break;
case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt 1"); break;
case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt 2"); break;
case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt 3"); break;
default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
}
 
231,7 → 231,7
trap_addr -= 2;
}
}
neorv32_uart_printf(" @0x%x, MTVAL=0x%x </RTE>", trap_addr, neorv32_cpu_csr_read(CSR_MTVAL));
neorv32_uart_printf(" @ 0x%x, MTVAL=0x%x </RTE>", trap_addr, neorv32_cpu_csr_read(CSR_MTVAL));
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.