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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw
    from Rev 2 to Rev 3
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  •

Rev 2 → Rev 3

/common/crt0.S
84,6 → 84,8
addi x15, x14, 0
 
// the following registers do not exist in rv32e
// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when
// compiling for a rv32e architecture
#ifndef __RISCV_EMBEDDED_CPU__
addi x16, x15, 0
addi x17, x16, 0
/example/hw_analysis/main.c
150,33 → 150,36
neorv32_uart_printf("\n-- Peripherals --\n");
tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
 
neorv32_uart_printf("GPIO: ");
neorv32_uart_printf("GPIO: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
 
neorv32_uart_printf("MTIME: ");
neorv32_uart_printf("MTIME: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
 
neorv32_uart_printf("UART: ");
neorv32_uart_printf("UART: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
 
neorv32_uart_printf("SPI: ");
neorv32_uart_printf("SPI: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
 
neorv32_uart_printf("TWI: ");
neorv32_uart_printf("TWI: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
 
neorv32_uart_printf("PWM: ");
neorv32_uart_printf("PWM: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
 
neorv32_uart_printf("WDT: ");
neorv32_uart_printf("WDT: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
 
neorv32_uart_printf("CLIC: ");
neorv32_uart_printf("CLIC: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
 
neorv32_uart_printf("TRNG: ");
neorv32_uart_printf("TRNG: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
 
neorv32_uart_printf("DEVNULL: ");
print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
 
return 0;
}
 
/example/test_exceptions/main.c
143,13 → 143,11
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFL;
neorv32_mtime_set_timecmp(mtime_cmp_max);
 
#if (DETAILED_EXCEPTION_DEBUG==1)
// detailed intro
neorv32_uart_printf("NEORV32 exceptions and interrupts test program: ");
#endif
neorv32_uart_printf("NEORV32 EXC TESTS\n");
 
// intro
neorv32_uart_printf("\nNEORV32 exceptions and interrupts test program\n\n");
 
 
// install exception handler functions
int install_err = 0;
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, exc_handler_i_misalign);
197,7 → 195,7
// ----------------------------------------------------------
// Unaligned instruction address
// ----------------------------------------------------------
neorv32_uart_printf("I_ALIGN: ");
neorv32_uart_printf("EXC I_ALIGN: ");
cnt_test++;
 
// call unaligned address
219,7 → 217,7
// ----------------------------------------------------------
// Instruction access fault
// ----------------------------------------------------------
neorv32_uart_printf("I_ACC: ");
neorv32_uart_printf("EXC I_ACC: ");
cnt_test++;
 
// call unreachable aligned address
241,7 → 239,7
// ----------------------------------------------------------
// Illegal instruction
// ----------------------------------------------------------
neorv32_uart_printf("I_ILLEG: ");
neorv32_uart_printf("EXC I_ILLEG: ");
cnt_test++;
 
// create mini program in RAM
269,7 → 267,7
// ----------------------------------------------------------
// Breakpoint instruction
// ----------------------------------------------------------
neorv32_uart_printf("BREAK: ");
neorv32_uart_printf("EXC BREAK: ");
cnt_test++;
 
asm volatile("EBREAK");
290,7 → 288,7
// ----------------------------------------------------------
// Unaligned load address
// ----------------------------------------------------------
neorv32_uart_printf("L_ALIGN: ");
neorv32_uart_printf("EXC L_ALIGN: ");
cnt_test++;
 
// load from unaligned address
312,7 → 310,7
// ----------------------------------------------------------
// Load access fault
// ----------------------------------------------------------
neorv32_uart_printf("L_ACC: ");
neorv32_uart_printf("EXC L_ACC: ");
cnt_test++;
 
// load from unreachable aligned address
334,7 → 332,7
// ----------------------------------------------------------
// Unaligned store address
// ----------------------------------------------------------
neorv32_uart_printf("S_ALIGN: ");
neorv32_uart_printf("EXC S_ALIGN: ");
cnt_test++;
 
// store to unaligned address
356,7 → 354,7
// ----------------------------------------------------------
// Store access fault
// ----------------------------------------------------------
neorv32_uart_printf("S_ACC: ");
neorv32_uart_printf("EXC S_ACC: ");
cnt_test++;
 
// store to unreachable aligned address
378,7 → 376,7
// ----------------------------------------------------------
// Environment call
// ----------------------------------------------------------
neorv32_uart_printf("ENVCALL: ");
neorv32_uart_printf("EXC ENVCALL: ");
cnt_test++;
 
asm volatile("ECALL");
399,7 → 397,7
// ----------------------------------------------------------
// Machine software interrupt
// ----------------------------------------------------------
neorv32_uart_printf("MSI: ");
neorv32_uart_printf("IRQ MSI: ");
cnt_test++;
 
// trigger machine software interrupt
421,7 → 419,7
// ----------------------------------------------------------
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
neorv32_uart_printf("MTI: ");
neorv32_uart_printf("IRQ MTI: ");
cnt_test++;
 
// force MTIME IRQ
449,7 → 447,7
// ----------------------------------------------------------
// Machine external interrupt (via CLIC)
// ----------------------------------------------------------
neorv32_uart_printf("MEI: ");
neorv32_uart_printf("IRQ MEI: ");
cnt_test++;
 
// manually trigger CLIC channel (watchdog interrupt)
474,10 → 472,8
#endif
 
 
#if (DETAILED_EXCEPTION_DEBUG==1)
// error report
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail);
#endif
 
// final result
if (cnt_fail == 0) {
/lib/include/neorv32.h
144,7 → 144,8
CPU_MFEATURES_IO_PWM = 21, /**< CPU mfeatures CSR (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
CPU_MFEATURES_IO_WDT = 22, /**< CPU mfeatures CSR (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
CPU_MFEATURES_IO_CLIC = 23, /**< CPU mfeatures CSR (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */
CPU_MFEATURES_IO_TRNG = 24 /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
CPU_MFEATURES_IO_TRNG = 24, /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
CPU_MFEATURES_IO_DEVNULL = 25 /**< CPU mfeatures CSR (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
};
 
 
491,6 → 492,15
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: Dummy Device (DEVNULL)
**************************************************************************/
/**@{*/
/** TRNG data register (r/w) */
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFC))
/**@}*/
 
 
// ----------------------------------------------------------------------------
// Include all IO driver headers
// ----------------------------------------------------------------------------
/lib/source/neorv32_uart.c
130,14 → 130,21
* Send single char via UART.
*
* @note This function is blocking.
* @warning The 'SIMCOM_UART_OVERRIDE' compiler user flag will forward all UART TX data to the SIMCOM simulation console output.
*
* @param[in] c Char to be send.
**************************************************************************/
void neorv32_uart_putc(char c) {
 
#ifdef DEVNULL_UART_OVERRIDE
#warning UART OVERRIDE! Sending all UART.TX data to DEVNULL simulation output instead of UART transmitter. Use this for simulations only!
DEVNULL_DATA = (uint32_t)c;
#else
// wait for previous transfer to finish
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
#endif
 
}
 
 

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