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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/example/cpu_test/main.c
311,9 → 311,9
 
 
// ----------------------------------------------------------
// Test time[h] (must be == MTIME)
// Test time (must be == MTIME.TIME)
// ----------------------------------------------------------
neorv32_uart_printf("TIME[H]: ");
neorv32_uart_printf("TIME: ");
cnt_test++;
 
cpu_systime.uint64 = neorv32_cpu_get_systime();
322,7 → 322,7
// compute difference
mtime_systime = mtime_systime - cpu_systime.uint64;
 
if (mtime_systime < 100) { // diff should be pretty small
if (mtime_systime < 4096) { // diff should be pretty small depending on bus latency
test_ok();
}
else {
391,7 → 391,7
 
 
// ----------------------------------------------------------
// Write-access to read-only CSR (must not trigger an exception)
// Write-access to read-only CSR
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("Rd-only CSR: ");
398,20 → 398,32
 
cnt_test++;
 
neorv32_cpu_csr_write(CSR_CYCLE, 0); // cycle CSR is read-only
neorv32_cpu_csr_write(CSR_TIME, 0); // time CSR is read-only
 
if (neorv32_cpu_csr_read(CSR_CYCLE) < 100) {
neorv32_uart_printf("[CSR update error!] ");
}
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == TRAP_CODE_I_ILLEGAL) {
test_fail();
test_ok();
}
else if (neorv32_cpu_csr_read(CSR_CYCLE) < 100) {
else {
test_fail();
}
else if (exception_handler_answer == 0xFFFFFFFF) {
#endif
 
 
// ----------------------------------------------------------
// No "real" CSR write access (because rs1 = r0)
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("NotWrite CSR: ");
 
cnt_test++;
 
// time CSR is read-only, but no actual write is performed because rs1=r0
// -> should cause no exception
asm volatile("csrrs zero, time, zero");
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == 0xFFFFFFFF) {
test_ok();
}
else {
742,6 → 754,12
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
// backup current UART configuration
uint32_t uart_ct_backup = UART_CT;
 
// disable UART sim_mode if it is enabled
UART_CT &= ~(1 << UART_CT_SIM_MODE);
 
// enable UART TX done IRQ
UART_CT |= (1 << UART_CT_TX_IRQ);
 
757,6 → 775,12
asm volatile("nop");
asm volatile("nop");
 
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
// re-enable UART sim_mode if it was enabled and disable UART TX done IRQ
UART_CT = uart_ct_backup;
 
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == TRAP_CODE_FIRQ_2) {
test_ok();
765,11 → 789,6
test_fail();
}
#endif
// wait for UART to finish transmitting
while(neorv32_uart_tx_busy());
 
// disable UART TX done IRQ
UART_CT &= ~(1 << UART_CT_TX_IRQ);
}
else {
neorv32_uart_printf("skipped (UART not implemented)\n");
974,7 → 993,7
break;
}
}
neorv32_uart_printf("Regions: %u\n", i);
neorv32_uart_printf("Max regions: %u\n", i);
 
 
// check granulartiy
1029,13 → 1048,13
 
// Test access to protected region
// ---------------------------------------------
neorv32_uart_printf("Creating protected page (NAPOT, 64k) @ 0xFFFFA000, (!x, !w, r)...\n");
neorv32_uart_printf("Creating protected page (NAPOT, 64kB) @ 0xFFFFA000, [!x, !w, r]...\n");
neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffdfff); // 64k area @ 0xFFFFA000
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // NAPOT, read permission, NO write and execute permissions
 
 
// ------ LOAD: should work ------
neorv32_uart_printf("U-mode (!X,!W,R) load test: ");
neorv32_uart_printf("U-mode [!X,!W,R] load test: ");
cnt_test++;
exception_handler_answer = 0xFFFFFFFF;
 
1061,7 → 1080,7
 
 
// ------ STORE: should fail ------
neorv32_uart_printf("U-mode (!X,!W,R) store test: ");
neorv32_uart_printf("U-mode [!X,!W,R] store test: ");
cnt_test++;
exception_handler_answer = 0xFFFFFFFF;
 
/lib/include/neorv32.h
60,7 → 60,7
 
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/-): Machine trap cause */
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
 
242,12 → 242,23
 
 
/**********************************************************************//**
* @name IO Device: Dummy Device (DEVNULL)
* @name IO Device: True Random Number Generator (TRNG)
**************************************************************************/
/**@{*/
/** DEVNULL data register (r/w) */
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFF88UL))
/** TRNG control/data register (r/w) */
#define TRNG_CT (*(IO_REG32 0xFFFFFF88UL))
 
/** TRNG control/data register bits */
enum NEORV32_TRNG_CT_enum {
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data (8-bit) LSB */
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data (8-bit) MSB */
TRNG_CT_VALID = 15, /**< TRNG data/control register(15) (r/-): Random data output valid */
TRNG_CT_ERROR_0 = 16, /**< TRNG data/control register(16) (r/-): Stuck-at-zero error */
TRNG_CT_ERROR_1 = 17, /**< TRNG data/control register(17) (r/-): Stuck-at-one error */
TRNG_CT_EN = 31 /**< TRNG data/control register(31) (r/w): TRNG enable */
};
/**@}*/
/**@}*/
 
 
/**********************************************************************//**
307,27 → 318,29
 
/** UART control register bits */
enum NEORV32_UART_CT_enum {
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bi, bit 0) */
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bi, bit 1) */
UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bi, bit 2) */
UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bi, bit 3) */
UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bi, bit 4) */
UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bi, bit 4) */
UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bi, bit 5) */
UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bi, bit 6) */
UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bi, bit 7) */
UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bi, bit 8) */
UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0)*/
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bi, bit 0) */
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bi, bit 1) */
UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bi, bit 2) */
UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bi, bit 3) */
UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bi, bit 4) */
UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bi, bit 4) */
UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bi, bit 5) */
UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bi, bit 6) */
UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bi, bit 7) */
UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bi, bit 8) */
UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0) */
 
UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
UART_CT_RXOR = 27, /**< UART control register(27) (r/-): RX data overrun when set */
UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */
UART_CT_RX_IRQ = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
UART_CT_TX_IRQ = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
 
UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
UART_CT_RXOR = 27, /**< UART control register(27) (r/-): RX data overrun when set */
UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */
UART_CT_RX_IRQ = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
UART_CT_TX_IRQ = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
};
 
/** UART receive/transmit data register bits */
439,26 → 452,6
 
 
/**********************************************************************//**
* @name IO Device: True Random Number Generator (TRNG)
**************************************************************************/
/**@{*/
/** TRNG control/data register (r/w) */
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0UL))
 
/** TRNG control/data register bits */
enum NEORV32_TRNG_CT_enum {
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data (8-bit) LSB */
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data (8-bit) MSB */
TRNG_CT_VALID = 15, /**< TRNG data/control register(15) (r/-): Random data output valid */
TRNG_CT_ERROR_0 = 16, /**< TRNG data/control register(16) (r/-): Stuck-at-zero error */
TRNG_CT_ERROR_1 = 17, /**< TRNG data/control register(17) (r/-): Stuck-at-one error */
TRNG_CT_EN = 31 /**< TRNG data/control register(31) (r/w): TRNG enable */
};
/**@}*/
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: Custom Functions Unit (CFU)
**************************************************************************/
/**@{*/
514,8 → 507,7
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
SYSINFO_FEATURES_IO_CFU = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit implemented when 1 (via IO_CFU_USE generic) */
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
SYSINFO_FEATURES_IO_DEVNULL = 25 /**< SYSINFO_FEATURES (25) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
SYSINFO_FEATURES_IO_TRNG = 24 /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
};
 
 
/lib/source/neorv32_rte.c
254,22 → 254,20
neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
// ID
neorv32_uart_printf("Hart ID: %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
 
neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
 
tmp = neorv32_cpu_csr_read(CSR_MARCHID);
neorv32_uart_printf("Architecture ID: 0x%x", tmp);
neorv32_uart_printf("Architecture ID: 0x%x", tmp);
 
// Custom user code/ID
neorv32_uart_printf("\nUser ID: 0x%x\n", SYSINFO_USER_CODE);
 
// HW version
neorv32_uart_printf("Hardware version: ");
neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
neorv32_rte_print_hw_version();
neorv32_uart_printf(")\n");
 
// CPU architecture
neorv32_uart_printf("\nArchitecture: ");
neorv32_uart_printf("Architecture: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
tmp = (tmp >> 30) & 0x03;
if (tmp == 0) {
286,7 → 284,7
}
// CPU extensions
neorv32_uart_printf("\nExtensions: ");
neorv32_uart_printf("\nExtensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
for (i=0; i<26; i++) {
if (tmp & (1 << i)) {
307,8 → 305,9
 
 
// Misc
neorv32_uart_printf("\n\n-- System --\n");
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
neorv32_uart_printf("\n\n\n-- Processor --\n");
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE);
 
 
// Memory configuration
329,7 → 328,7
neorv32_uart_printf("Bootloader: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
 
neorv32_uart_printf("External interface: ");
neorv32_uart_printf("External M interface: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
 
// peripherals
337,34 → 336,31
 
tmp = SYSINFO_FEATURES;
 
neorv32_uart_printf("GPIO: ");
neorv32_uart_printf("GPIO: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
 
neorv32_uart_printf("MTIME: ");
neorv32_uart_printf("MTIME: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
 
neorv32_uart_printf("UART: ");
neorv32_uart_printf("UART: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
 
neorv32_uart_printf("SPI: ");
neorv32_uart_printf("SPI: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
 
neorv32_uart_printf("TWI: ");
neorv32_uart_printf("TWI: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
 
neorv32_uart_printf("PWM: ");
neorv32_uart_printf("PWM: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
 
neorv32_uart_printf("WDT: ");
neorv32_uart_printf("WDT: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
 
neorv32_uart_printf("TRNG: ");
neorv32_uart_printf("TRNG: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
 
neorv32_uart_printf("DEVNULL: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
 
neorv32_uart_printf("CFU: ");
neorv32_uart_printf("CFU: ");
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU));
}
 
/lib/source/neorv32_uart.c
71,6 → 71,8
/**********************************************************************//**
* Enable and configure UART.
*
* @warning The 'UART_SIM_MODE' compiler flag will redirect all UART TX data to the simulation output. Use this for simulations only!
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] rx_irq Enable RX interrupt (data received) when 1.
* @param[in] tx_irq Enable TX interrupt (transmission done) when 1.
112,7 → 114,16
uint32_t tx_irq_en = (uint32_t)(tx_irq & 1);
tx_irq_en = tx_irq_en << UART_CT_TX_IRQ;
 
UART_CT = prsc | baud | uart_en | rx_irq_en | tx_irq_en;
/* Enable the UART for SIM mode. */
/* Only use this for simulation! */
#ifdef UART_SIM_MODE
#warning UART_SIM_MODE enabled! Sending all UART.TX to text.io simulation output instead of real UART transmitter. Use this for simulations only!
uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
#else
uint32_t sim_mode = 0;
#endif
 
UART_CT = prsc | baud | uart_en | rx_irq_en | tx_irq_en | sim_mode;
}
 
 
129,21 → 140,18
* Send single char via UART.
*
* @note This function is blocking.
* @warning The 'DEVNULL_UART_OVERRIDE' compiler user flag will forward all UART TX data to the DEVNULL simulation console output.
*
* @param[in] c Char to be send.
**************************************************************************/
void neorv32_uart_putc(char c) {
 
#ifdef DEVNULL_UART_OVERRIDE
#warning UART OVERRIDE! Sending all UART.TX data to DEVNULL simulation output instead of UART transmitter. Use this for simulations only!
DEVNULL_DATA = (uint32_t)c;
#ifdef UART_SIM_MODE
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
#else
// wait for previous transfer to finish
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
UART_DATA = ((uint32_t)c) << UART_DATA_LSB;
#endif
 
}
 
 

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