URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw
- from Rev 30 to Rev 31
- ↔ Reverse comparison
Rev 30 → Rev 31
/common/neorv32.ld
55,7 → 55,7
/* "rom" section: first value of ORIGIN/LENGHT => bootloader ROM; second value of ORIGIN/LENGHT => instruction memory */ |
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rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 4*1024 : 16*1024 |
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024 |
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024 |
} |
/* ************************************************************************* */ |
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/example/cpu_test/main.c
1050,7 → 1050,7
// --------------------------------------------- |
neorv32_uart_printf("Creating protected page (NAPOT, 64kB) @ 0xFFFFA000, [!x, !w, r]...\n"); |
neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffdfff); // 64k area @ 0xFFFFA000 |
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // NAPOT, read permission, NO write and execute permissions |
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // NAPOT, read permission, NO write and NO execute permissions |
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// ------ LOAD: should work ------ |
1103,10 → 1103,29
test_fail(); |
} |
#endif |
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// ------ Lock test ------ |
neorv32_uart_printf("Locking pmpcfg0 [mode=off]: "); |
cnt_test++; |
exception_handler_answer = 0xFFFFFFFF; |
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0b10000001); // locked but entry is deactivated (mode = off) |
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// make sure a locked cfg cannot be written |
tmp_a = neorv32_cpu_csr_read(CSR_PMPCFG0); |
neorv32_cpu_csr_write(CSR_PMPCFG0, 0b00011001); // try to re-write CFG content |
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if ((tmp_a != neorv32_cpu_csr_read(CSR_PMPCFG0)) || (exception_handler_answer != 0xFFFFFFFF)) { |
test_fail(); |
} |
else { |
test_ok(); |
} |
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} |
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// ---------------------------------------------------------- |
// Final test reports |
// ---------------------------------------------------------- |
/lib/include/neorv32.h
158,17 → 158,17
* Trap codes from mcause CSR. |
**************************************************************************/ |
enum NEORV32_EXCEPTION_CODES_enum { |
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */ |
TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */ |
TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */ |
TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */ |
TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */ |
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */ |
TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */ |
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */ |
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */ |
TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */ |
TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */ |
TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */ |
TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */ |
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */ |
TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */ |
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */ |
TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */ |
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */ |
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */ |
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */ |
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */ |
TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */ |
TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */ |
TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */ |