URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/bootloader/bootloader.c
218,7 → 218,9
print_proc_version(); |
neorv32_uart_print("\nCLK: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MCLOCK)); |
neorv32_uart_print(" Hz\nMISA: "); |
neorv32_uart_print(" Hz\nMHID: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MHARTID)); |
neorv32_uart_print("\nMISA: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MISA)); |
neorv32_uart_print("\nCONF: "); |
print_hex_word(neorv32_cpu_csr_read(CSR_MFEATURES)); |
/common/crt0.S
1,7 → 1,7
/* ################################################################################################# */ |
/* # << NEORV32 - crt0.S - Application Start-Up Code >> # */ |
/* # << NEORV32 - crt0.S - Application Start-Up Code & Minimal Runtime Environment >> # */ |
/* # ********************************************************************************************* # */ |
/* # The start-up code provides a minimal runtime environment that catches all exceptions/ # */ |
/* # The start-up code provides a minimal runtime environment that catches all exceptions and # */ |
/* # interrupts and delegates them to the handler functions (installed by user via dedicated # */ |
/* # install function from the neorv32 runtime environment library). # */ |
/* # ********************************************************************************************* # */ |
117,8 → 117,8
// Setup stack pointer |
// ********************************************************* |
__crt0_stack_pointer_init: |
csrrw x11, CSR_MDSPACEBASE, zero // data memory space base address |
csrrw x12, CSR_MDSPACESIZE, zero // data memory space size |
csrr x11, CSR_MDSPACEBASE // data memory space base address |
csrr x12, CSR_MDSPACESIZE // data memory space size |
add sp, x11, x12 |
addi sp, sp, -4 // stack pointer = last entry |
addi fp, sp, 0 // frame pointer = stack pointer |
139,9 → 139,9
// ********************************************************* |
__crt0_neorv32_rte_init: |
la x11, __crt0_neorv32_rte |
csrrw zero, mtvec, x11 // set address of first-level exception handler |
csrw mtvec, x11 // set address of first-level exception handler |
|
csrrw x11, CSR_MDSPACEBASE, zero // data memory space base address |
csrr x11, CSR_MDSPACEBASE // data memory space base address |
la x12, __crt0_neorv32_rte_dummy_hanlder |
li x13, 2*16 // number of entries (16xEXC, 16xIRQ) |
|
278,14 → 278,14
// -------------------------------------------- |
// get cause and prepare jump into vector table |
// -------------------------------------------- |
csrrw t0, mcause, zero // get cause code |
csrr t0, mcause // get cause code |
|
andi t1, t0, 0x0f // isolate cause ID |
slli t1, t1, 2 // make address offset |
csrrw ra, CSR_MDSPACEBASE, zero // data memory space base address |
csrr ra, CSR_MDSPACEBASE // data memory space base address |
add t1, t1, ra // get vetor table entry address (EXC vectors) |
|
csrrw ra, mepc, zero // get return address |
csrr ra, mepc // get return address |
|
blt t0, zero, __crt0_neorv32_rte_is_irq // branch if this is an INTERRUPT |
|
296,11 → 296,11
__crt0_neorv32_rte_is_exc: |
|
// is faulting instruction compressed? |
csrrw t0, mtinst, zero |
andi t0, t0, 2 // get compression flag (bit #1): 0=compressed, 2=uncompressed |
csrr t0, mtinst |
andi t0, t0, 2 // get compression flag (bit #1): 0=compressed, 1=uncompressed |
|
addi ra, ra, +2 // only this for compressed instr |
add ra, ra, t0 // add another 2 (0+4) for uncompressed instr |
addi ra, ra, +2 // only this for compressed instructions |
add ra, ra, t0 // add another 2 (making +4) for uncompressed instructions |
j __crt0_neorv32_rte_execute |
|
|
320,7 → 320,6
// push ra |
addi sp, sp, -4 |
sw ra, 0(sp) |
csrrw zero, mscratch, ra |
|
jalr ra, t0 // call second-level handler |
|
328,7 → 327,7
lw ra, 0(sp) |
addi sp, sp, +4 |
|
csrrw zero, mepc, ra |
csrw mepc, ra |
|
|
// -------------------------------------------- |
/example/blink_led/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/example/coremark/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/example/cpu_test/main.c
0,0 → 1,586
// ################################################################################################# |
// # << NEORV32 - CPU Test Program >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file cpu_test/main.c |
* @author Stephan Nolting |
* @brief Simple CPU interrupts and exceptions test program. |
**************************************************************************/ |
|
#include <neorv32.h> |
|
|
/**********************************************************************//** |
* @name User configuration |
**************************************************************************/ |
/**@{*/ |
/** UART BAUD rate */ |
#define BAUD_RATE 19200 |
//** Set 1 for detailed exception debug information */ |
#define DETAILED_EXCEPTION_DEBUG 0 |
//** Reachable unaligned address */ |
#define ADDR_UNALIGNED 0x00000002 |
//** Unreachable aligned address */ |
#define ADDR_UNREACHABLE 0xFFFFFF00 |
/**@}*/ |
|
|
/**********************************************************************//** |
* @name Exception handler acknowledges |
**************************************************************************/ |
/**@{*/ |
/** Exception handler answers / identifiers */ |
enum EXC_HANDLER_ANSWERS { |
ANSWER_I_MISALIGN = 0x12345678, /**< Answer for misaligned instruction address excetion */ |
ANSWER_I_ACCESS = 0xAABB1133, /**< Answer for instruction access fault excetion */ |
ANSWER_I_ILLEGAL = 0x0199203B, /**< Answer for illegal instruction excetion */ |
ANSWER_BREAKPOINT = 0x12322330, /**< Answer for breakpoint excetion */ |
ANSWER_L_MISALIGN = 0xBABCCCCC, /**< Answer for misaligned load address excetion */ |
ANSWER_L_ACCESS = 0xDEF728AA, /**< Answer for load access fault excetion */ |
ANSWER_S_MISALIGN = 0xFF0927DD, /**< Answer for misaligned store address excetion */ |
ANSWER_S_ACCESS = 0x20091777, /**< Answer for store access fault excetion */ |
ANSWER_ENVCALL = 0x55662244, /**< Answer for environment call excetion */ |
ANSWER_MSI = 0xCDECDEA9, /**< Answer for machine software interrupt */ |
ANSWER_MTI = 0x0012FA53, /**< Answer for machine timer interrupt */ |
ANSWER_CLIC = 0xEEF33088 /**< Answer for machine external interrupt */ |
}; |
/** Gloabl volatile variable to store exception handler answer */ |
volatile uint32_t exception_handler_answer; |
/**@}*/ |
|
|
// Prototypes |
void exc_handler_i_misalign(void); |
void exc_handler_i_access(void); |
void exc_handler_i_illegal(void); |
void exc_handler_breakpoint(void); |
void exc_handler_l_misalign(void); |
void exc_handler_l_access(void); |
void exc_handler_s_misalign(void); |
void exc_handler_s_access(void); |
void exc_handler_envcall(void); |
void exc_handler_msi(void); |
void exc_handler_mti(void); |
void irq_handler_clic_ch0(); |
|
|
/**********************************************************************//** |
* Unreachable memory-mapped register that should be always available |
**************************************************************************/ |
#define MMR_UNREACHABLE (*(IO_REG32 (ADDR_UNREACHABLE))) |
|
|
/**********************************************************************//** |
* This program uses mostly synthetic case to trigger all implemented exceptions. |
* Each exception is captured and evaluated for correct detection. |
* |
* @note This program requires the UART, MTIME and CLIC to be synthesized. |
* |
* @return Irrelevant. |
**************************************************************************/ |
int main() { |
|
register uint32_t tmp_a; |
volatile uint32_t dummy_dst __attribute__((unused)); |
|
int cnt_fail = 0; |
int cnt_ok = 0; |
int cnt_test = 0; |
|
// check if UART unit is implemented at all |
if (neorv32_uart_available() == 0) { |
return 0; |
} |
|
// check if CLIC unit is implemented at all |
if (neorv32_clic_available() == 0) { |
return 0; |
} |
|
// check if MTIME unit is implemented at all |
if (neorv32_mtime_available() == 0) { |
return 0; |
} |
|
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
|
|
// set CMP of machine system timer MTIME to max to prevent an IRQ |
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFL; |
neorv32_mtime_set_timecmp(mtime_cmp_max); |
|
// intro |
neorv32_uart_printf("\n\n------ CPU TEST ------\n\n"); |
|
// show full HW config report |
neorv32_rte_print_hw_config(); |
|
// intro2 |
neorv32_uart_printf("\n\nNEORV32 exceptions and interrupts test program\n\n"); |
|
// install exception handler functions |
int install_err = 0; |
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, exc_handler_i_misalign); |
install_err += neorv32_rte_exception_install(EXCID_I_ACCESS, exc_handler_i_access); |
install_err += neorv32_rte_exception_install(EXCID_I_ILLEGAL, exc_handler_i_illegal); |
install_err += neorv32_rte_exception_install(EXCID_BREAKPOINT, exc_handler_breakpoint); |
install_err += neorv32_rte_exception_install(EXCID_L_MISALIGNED, exc_handler_l_misalign); |
install_err += neorv32_rte_exception_install(EXCID_L_ACCESS, exc_handler_l_access); |
install_err += neorv32_rte_exception_install(EXCID_S_MISALIGNED, exc_handler_s_misalign); |
install_err += neorv32_rte_exception_install(EXCID_S_ACCESS, exc_handler_s_access); |
install_err += neorv32_rte_exception_install(EXCID_MENV_CALL, exc_handler_envcall); |
install_err += neorv32_rte_exception_install(EXCID_MSI, exc_handler_msi); |
install_err += neorv32_rte_exception_install(EXCID_MTI, exc_handler_mti); |
//install_err += neorv32_rte_exception_install(EXCID_MEI, -); done by neorv32_clic_handler_install |
|
if (install_err) { |
neorv32_uart_printf("install error!\n"); |
return 0; |
} |
|
|
// install interrupt handler for clic WDT channel |
install_err += neorv32_clic_handler_install(CLIC_CH_WDT, irq_handler_clic_ch0); |
|
if (install_err) { |
neorv32_uart_printf("CLIC install error!\n"); |
return 0; |
} |
|
|
#if (DETAILED_EXCEPTION_DEBUG==1) |
// enable debug mode for uninitialized exception/interrupt vectors |
// and overwrite previous exception handler installations |
// -> any exception/interrupt will show a message from the neorv32 runtime environment |
neorv32_rte_enable_debug_mode(); |
#endif |
|
|
// enable global interrupts |
neorv32_cpu_eint(); |
|
exception_handler_answer = 0; |
|
|
// ---------------------------------------------------------- |
// Unaligned instruction address |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC I_ALIGN: "); |
cnt_test++; |
|
// skip if C-mode is not implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) | (1<<CPU_MISA_C_EXT)) == 0) { |
|
// call unaligned address |
((void (*)(void))ADDR_UNALIGNED)(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_I_MISALIGN) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
} |
else { |
neorv32_uart_printf("skipped (no EXC I_ALIGN possible in C-mode)\n"); |
} |
|
|
// ---------------------------------------------------------- |
// Instruction access fault |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC I_ACC: "); |
cnt_test++; |
|
// call unreachable aligned address |
((void (*)(void))ADDR_UNREACHABLE)(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_I_ACCESS) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Illegal instruction |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC I_ILLEG: "); |
cnt_test++; |
|
// create test program in RAM |
static const uint32_t dummy_sub_program[2] = { |
0xDEAD007F, // undefined 32-bit opcode -> illegal instruction exception |
0x00008067 // ret (32-bit) |
}; |
|
tmp_a = (uint32_t)&dummy_sub_program; // call the dummy sub program |
asm volatile ( "jalr ra, %0 " : "=r" (tmp_a) : "r" (tmp_a)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_I_ILLEGAL) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Breakpoint instruction |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC BREAK: "); |
cnt_test++; |
|
asm volatile("EBREAK"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_BREAKPOINT) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Unaligned load address |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC L_ALIGN: "); |
cnt_test++; |
|
// load from unaligned address |
asm volatile ("lw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_L_MISALIGN) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Load access fault |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC L_ACC: "); |
cnt_test++; |
|
// load from unreachable aligned address |
dummy_dst = MMR_UNREACHABLE; |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_L_ACCESS) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Unaligned store address |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC S_ALIGN: "); |
cnt_test++; |
|
// store to unaligned address |
asm volatile ("sw zero, %[input_i](zero)" : : [input_i] "i" (ADDR_UNALIGNED)); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_S_MISALIGN) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Store access fault |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC S_ACC: "); |
cnt_test++; |
|
// store to unreachable aligned address |
MMR_UNREACHABLE = 0; |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_S_ACCESS) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Environment call |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC ENVCALL: "); |
cnt_test++; |
|
asm volatile("ECALL"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_ENVCALL) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Machine software interrupt |
// ---------------------------------------------------------- |
neorv32_uart_printf("IRQ MSI: "); |
cnt_test++; |
|
// trigger machine software interrupt |
neorv32_cpu_sw_irq(); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_MSI) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Machine timer interrupt (MTIME) |
// ---------------------------------------------------------- |
neorv32_uart_printf("IRQ MTI: "); |
cnt_test++; |
|
// force MTIME IRQ |
neorv32_mtime_set_timecmp(0); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_MTI) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Machine external interrupt (via CLIC) |
// ---------------------------------------------------------- |
neorv32_uart_printf("IRQ MEI: "); |
cnt_test++; |
|
// manually trigger CLIC channel (watchdog interrupt) |
neorv32_clic_trigger_irq(CLIC_CH_WDT); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
#if (DETAILED_EXCEPTION_DEBUG==0) |
if (exception_handler_answer == ANSWER_CLIC) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// error report |
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail); |
|
// final result |
if (cnt_fail == 0) { |
neorv32_uart_printf("TEST OK!\n"); |
} |
else { |
neorv32_uart_printf("TEST FAILED!\n"); |
} |
|
return 0; |
} |
|
|
/**********************************************************************//** |
* Misaligned instruction address exception handler. |
**************************************************************************/ |
void exc_handler_i_misalign(void) { |
exception_handler_answer = ANSWER_I_MISALIGN; |
} |
|
/**********************************************************************//** |
* Instruction access fault exception handler. |
**************************************************************************/ |
void exc_handler_i_access(void) { |
exception_handler_answer = ANSWER_I_ACCESS; |
} |
|
/**********************************************************************//** |
* Illegal instruction exception handler. |
**************************************************************************/ |
void exc_handler_i_illegal(void) { |
exception_handler_answer = ANSWER_I_ILLEGAL; |
} |
|
/**********************************************************************//** |
* Breakpoint exception handler. |
**************************************************************************/ |
void exc_handler_breakpoint(void) { |
exception_handler_answer = ANSWER_BREAKPOINT; |
} |
|
/**********************************************************************//** |
* Misaligned load address exception handler. |
**************************************************************************/ |
void exc_handler_l_misalign(void) { |
exception_handler_answer = ANSWER_L_MISALIGN; |
} |
|
/**********************************************************************//** |
* Load instruction access fault exception handler. |
**************************************************************************/ |
void exc_handler_l_access(void) { |
exception_handler_answer = ANSWER_L_ACCESS; |
} |
|
/**********************************************************************//** |
* Misaligned store address exception handler. |
**************************************************************************/ |
void exc_handler_s_misalign(void) { |
exception_handler_answer = ANSWER_S_MISALIGN; |
} |
|
/**********************************************************************//** |
* Store address access fault exception handler. |
**************************************************************************/ |
void exc_handler_s_access(void) { |
exception_handler_answer = ANSWER_S_ACCESS; |
} |
|
/**********************************************************************//** |
* Environment call exception handler. |
**************************************************************************/ |
void exc_handler_envcall(void) { |
exception_handler_answer = ANSWER_ENVCALL; |
} |
|
/**********************************************************************//** |
* Machine software interrupt exception handler. |
**************************************************************************/ |
void exc_handler_msi(void) { |
exception_handler_answer = ANSWER_MSI; |
} |
|
/**********************************************************************//** |
* Machine timer interrupt exception handler. |
**************************************************************************/ |
void exc_handler_mti(void) { |
exception_handler_answer = ANSWER_MTI; |
// set CMP of machine system timer MTIME to max to prevent an IRQ |
neorv32_mtime_set_timecmp(-1); |
} |
|
/**********************************************************************//** |
* CLIC interrupt handler for channel 0. |
**************************************************************************/ |
void irq_handler_clic_ch0(void) { |
exception_handler_answer = ANSWER_CLIC; |
} |
|
/example/cpu_test/makefile
0,0 → 1,326
################################################################################################# |
# << NEORV32 - Application Makefile >> # |
# ********************************************************************************************* # |
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. # |
# ********************************************************************************************* # |
# BSD 3-Clause License # |
# # |
# Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
# # |
# Redistribution and use in source and binary forms, with or without modification, are # |
# permitted provided that the following conditions are met: # |
# # |
# 1. Redistributions of source code must retain the above copyright notice, this list of # |
# conditions and the following disclaimer. # |
# # |
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
# conditions and the following disclaimer in the documentation and/or other materials # |
# provided with the distribution. # |
# # |
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
# endorse or promote products derived from this software without specific prior written # |
# permission. # |
# # |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
# OF THE POSSIBILITY OF SUCH DAMAGE. # |
# ********************************************************************************************* # |
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
################################################################################################# |
|
|
# ***************************************************************************** |
# USER CONFIGURATION |
# ***************************************************************************** |
# Compiler effort |
EFFORT = -Os |
|
# User's application sources (add additional files here) |
APP_SRC = $(wildcard *.c) |
|
# User's application include folders (don't forget the '-I' before each entry) |
APP_INC = -I . |
|
# Compiler toolchain (use default if not set by user) |
RISCV_TOOLCHAIN ?= riscv32-unknown-elf |
|
# CPU architecture and ABI |
MARCH = -march=rv32i |
MABI = -mabi=ilp32 |
|
# Path to runtime c library (use default if not set by user) |
LIBC_PATH ?= $(dir $(shell which $(CC)))../$(RISCV_TOOLCHAIN)/lib/libc.a |
LIBGCC_PATH ?= $(dir $(shell which $(CC)))../lib/gcc/$(RISCV_TOOLCHAIN)/*/libgcc.a |
|
# Relative or absolute path to the NEORV32 home folder (use default if not set by user) |
NEORV32_HOME ?= ../../.. |
# ***************************************************************************** |
|
|
|
# ----------------------------------------------------------------------------- |
# NEORV32 framework |
# ----------------------------------------------------------------------------- |
# Path to NEORV32 linker script and startup file |
NEORV32_COM_PATH=$(NEORV32_HOME)/sw/common |
# Path to main NEORV32 library include files |
NEORV32_INC_PATH=$(NEORV32_HOME)/sw/lib/include |
# Path to main NEORV32 library source files |
NEORV32_SRC_PATH=$(NEORV32_HOME)/sw/lib/source |
# Path to NEORV32 executable generator |
NEORV32_EXG_PATH=$(NEORV32_HOME)/sw/image_gen |
# Path to NEORV32 core rtl folder |
NEORV32_RTL_PATH=$(NEORV32_HOME)/rtl/core |
# Marker file to verify NEORV32 home folder |
NEORV32_HOME_MARKER=$(NEORV32_INC_PATH)/neorv32.h |
|
|
# ----------------------------------------------------------------------------- |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.DEFAULT_GOAL := help |
|
|
# ----------------------------------------------------------------------------- |
# Application output definitions |
# ----------------------------------------------------------------------------- |
APP_EXE = neorv32_exe.bin |
APP_ASM = main.s |
|
compile: $(APP_ASM) $(APP_EXE) |
install: $(APP_ASM) neorv32_application_image.vhd |
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
# Tools and flags |
# ----------------------------------------------------------------------------- |
# compiler tools |
CC = $(RISCV_TOOLCHAIN)-gcc |
LD = $(RISCV_TOOLCHAIN)-ld |
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump |
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy |
SIZE = $(RISCV_TOOLCHAIN)-size |
|
# NEORV32 executable image generator |
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen |
|
# Compiler flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -lm |
|
# Linker flags |
LD_OPTS = $(EFFORT) --gc-sections |
|
# User flags for additional config |
USER_FLAGS = |
CC_OPTS += $(USER_FLAGS) |
|
# Use embedded RISC-V CPU extension? |
ifeq (,$(findstring rv32e,$(MARCH))) |
CC_OPTS += |
else |
CC_OPTS += -D__RISCV_EMBEDDED_CPU__ |
endif |
|
# ----------------------------------------------------------------------------- |
# Host native compiler |
# ----------------------------------------------------------------------------- |
CC_X86 = gcc -Wall -O -g |
|
|
# ----------------------------------------------------------------------------- |
# Tool targets |
# ----------------------------------------------------------------------------- |
# install/compile tools |
$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp |
@echo Compiling $(IMAGE_GEN) |
@$(CC_X86) $< -o $(IMAGE_GEN) |
|
|
# ----------------------------------------------------------------------------- |
# Application targets: Assemble, compile, link, dump |
# ----------------------------------------------------------------------------- |
# Assemble startup code |
crt0.elf: $(NEORV32_COM_PATH)/crt0.S |
@$(CC) $(CC_OPTS) -c $< -o $@ |
|
# Compile app sources |
$(OBJ): %.o : %.c crt0.elf |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ |
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(LD) $(LD_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) -T $(NEORV32_COM_PATH)/neorv32.ld $(OBJ) $(LIBC_PATH) $(LIBGCC_PATH) -o $@ |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
|
|
# ----------------------------------------------------------------------------- |
# Application targets: Generate binary executable, install (as VHDL file) |
# ----------------------------------------------------------------------------- |
# Generate final executable: text, rodata, data (in THIS order!) |
main.bin: main.elf |
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.bin |
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.bin |
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.bin |
@cat text.bin rodata.bin data.bin > $@ |
@rm -f text.bin rodata.bin data.bin |
|
# Generate NEORV32 executable image for bootloader update |
$(APP_EXE): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -app_bin $< $@ $(shell basename $(CURDIR)) |
@echo "Executable ($(APP_EXE)) size in bytes:" |
@wc -c < $(APP_EXE) |
|
# Generate NEORV32 executable VHDL boot image |
neorv32_application_image.vhd: main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -app_img $< $@ $(shell basename $(CURDIR)) |
@echo "Installing application image to $(NEORV32_RTL_PATH)/neorv32_application_image.vhd" |
@cp neorv32_application_image.vhd $(NEORV32_RTL_PATH)/. |
@rm -f neorv32_application_image.vhd |
|
|
# ----------------------------------------------------------------------------- |
# Bootloader targets |
# ----------------------------------------------------------------------------- |
# Assemble startup code |
bootloader_crt0.elf: $(NEORV32_COM_PATH)/bootloader_crt0.S |
@$(CC) $(CC_OPTS) -c $< -o $@ |
|
# Compile and install bootloader |
bootloader: bootloader_crt0.elf $(OBJ) $(IMAGE_GEN) |
@set -e |
@$(LD) $(LD_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) -T $(NEORV32_COM_PATH)/bootloader_neorv32.ld $(OBJ) $(LIBC_PATH) $(LIBGCC_PATH) -o bootloader.elf |
@echo "Memory utilization:" |
@$(SIZE) bootloader.elf |
@$(OBJDUMP) -D -S -z bootloader.elf > bootloader.s |
@$(OBJCOPY) -I elf32-little bootloader.elf -j .text -O binary text.bin |
@$(OBJCOPY) -I elf32-little bootloader.elf -j .rodata -O binary rodata.bin |
@$(OBJCOPY) -I elf32-little bootloader.elf -j .data -O binary data.bin |
@cat text.bin rodata.bin data.bin > bootloader.bin |
@$(IMAGE_GEN) -bld_img bootloader.bin neorv32_bootloader_image.vhd $(shell basename $(CURDIR)) |
@echo "Installing bootloader image to $(NEORV32_RTL_PATH)/neorv32_bootloader_image.vhd" |
@cp neorv32_bootloader_image.vhd $(NEORV32_RTL_PATH)/. |
@rm -f neorv32_bootloader_image.vhd text.bin rodata.bin data.bin |
|
|
# ----------------------------------------------------------------------------- |
# Check toolchain |
# ----------------------------------------------------------------------------- |
check: $(IMAGE_GEN) |
@echo "---------------- Check: NEORV32_HOME folder ----------------" |
ifneq ($(shell [ -e $(NEORV32_HOME_MARKER) ] && echo 1 || echo 0 ), 1) |
$(error NEORV32_HOME folder not found!) |
endif |
@echo "NEORV32_HOME: $(NEORV32_HOME)" |
@echo "---------------- Check: $(CC) ----------------" |
@$(CC) -v |
@echo "---------------- Check: $(LD) ----------------" |
@$(LD) -V |
@echo "---------------- Check: $(OBJDUMP) ----------------" |
@$(OBJDUMP) -V |
@echo "---------------- Check: $(OBJCOPY) ----------------" |
@$(OBJCOPY) -V |
@echo "---------------- Check: $(SIZE) ----------------" |
@$(SIZE) -V |
@echo "---------------- Check: NEORV32 image_gen ----------------" |
@$(IMAGE_GEN) -help |
@echo "---------------- Check: native gcc ----------------" |
@$(CC_X86) -v |
@echo |
@echo "Toolchain check OK" |
|
|
# ----------------------------------------------------------------------------- |
# Show configuration |
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
@echo "---------------- Info: RISC-V Toolchain ----------------" |
@echo "Toolchain: $(RISCV_TOLLCHAIN)" |
@echo "CC: $(CC)" |
@echo "LD: $(LD)" |
@echo "OBJDUMP: $(OBJDUMP)" |
@echo "OBJCOPY: $(OBJCOPY)" |
@echo "SIZE: $(SIZE)" |
@echo "---------------- Info: C Lib ----------------" |
@echo "CLIB: $(LIBC_PATH)" |
@echo "GCCLIB: $(LIBGCC_PATH)" |
@echo "---------------- Info: Flags ----------------" |
@echo "CC_OPTS: $(CC_OPTS)" |
@echo "LD_OPTS: $(LD_OPTS)" |
@echo "---------------- Info: Host Native GCC ----------------" |
@echo "CC_X86: $(CC_X86)" |
|
|
# ----------------------------------------------------------------------------- |
# Show final ELF details (just for debugging) |
# ----------------------------------------------------------------------------- |
elf_info: main.elf |
@$(OBJDUMP) -x main.elf |
|
|
# ----------------------------------------------------------------------------- |
# Help |
# ----------------------------------------------------------------------------- |
help: |
@echo "<<< NEORV32 Application Makefile >>>" |
@echo "Make sure to add the bin folder of RISC-V GCC to your PATH variable." |
@echo "Targets:" |
@echo " help - show this text" |
@echo " check - check toolchain" |
@echo " info - show makefile/toolchain configuration" |
@echo " compile - compile and generate <neorv32_exe.bin> executable for upload via bootloader" |
@echo " install - compile, generate and install VHDL IMEM boot image" |
@echo " all - compile and generate <neorv32_exe.bin> executable for upload via bootloader and generate and install VHDL IMEM boot image" |
@echo " clean - clean up project" |
@echo " clean_all - clean up project, core libraries and image generator" |
@echo " bootloader - compile, generate and install VHDL BOOTROM bott image (for bootloader only!)" |
|
|
# ----------------------------------------------------------------------------- |
# Clean up |
# ----------------------------------------------------------------------------- |
clean: |
@rm -f *.elf *.o *.bin *.out *.s |
|
clean_all: clean |
@rm -f $(OBJ) $(IMAGE_GEN) |
|
/example/demo_pwm/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/example/demo_trng/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/example/demo_twi/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/example/demo_wdt/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/example/game_of_life/makefile
82,16 → 82,14
|
|
# ----------------------------------------------------------------------------- |
# Add NEORV32 sources to input SRCs |
# NEORV32 core sources |
# ----------------------------------------------------------------------------- |
APP_SRC += $(wildcard $(NEORV32_SRC_PATH)/*.c) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
|
|
# ----------------------------------------------------------------------------- |
# Make defaults |
# ----------------------------------------------------------------------------- |
.SUFFIXES: |
.PHONY: all |
.DEFAULT_GOAL := help |
|
|
106,7 → 104,8
all: $(APP_ASM) $(APP_EXE) neorv32_application_image.vhd |
|
# define all object files |
OBJ = $(APP_SRC:.c=.o) |
OBJ = $(APP_SRC:.c=.o) |
OBJ += $(CORE_SRC:.c=.o) |
|
|
# ----------------------------------------------------------------------------- |
259,13 → 258,18
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project: $(shell basename $(CURDIR))" |
@echo "Project source files: $(APP_SRC)" |
@echo "Project include folders: $(NEORV32_INC_PATH) $(APP_INC)" |
@echo "Project object files: $(OBJ)" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
/lib/include/neorv32.h
60,10 → 60,10
* Available CPU Control and Status Registers (CSRs) |
**************************************************************************/ |
enum NEORV32_CPU_CSRS_enum { |
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions */ |
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ |
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */ |
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions */ |
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ |
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */ |
|
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */ |
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */ |
127,6 → 127,21
|
|
/**********************************************************************//** |
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MISA_enum { |
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */ |
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */ |
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension available (r/-) */ |
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */ |
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */ |
}; |
|
|
/**********************************************************************//** |
* CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM) |
**************************************************************************/ |
enum NEORV32_CPU_MFEATURES_enum { |
135,6 → 150,7
CPU_MFEATURES_MEM_INT_IMEM = 2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */ |
CPU_MFEATURES_MEM_INT_IMEM_ROM = 3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */ |
CPU_MFEATURES_MEM_INT_DMEM = 4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */ |
CPU_MFEATURES_CSR_COUNTERS = 5, /**< CPU mfeatures CSR (5) (r/-): RISC-V performance counters implemented when 1 (via CSR_COUNTERS_USE generic) */ |
|
CPU_MFEATURES_IO_GPIO = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */ |
CPU_MFEATURES_IO_MTIME = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */ |
211,13 → 227,13
**************************************************************************/ |
/**@{*/ |
/** instruction memory base address (r/w/x) */ |
#define INSTR_MEM_BASE_ADDR 0x00000000 |
// -> use value from MEM_ISPACE_BASE CSR |
/** data memory base address (r/w/x) */ |
#define DATA_MEM_BASE_ADDR 0x80000000 |
// -> use value from MEM_DSPACE_BASE CSR |
/** bootloader memory base address (r/-/x) */ |
#define BOOTLOADER_BASE_ADDRESS 0xFFFF0000 |
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL) |
/** peripheral/IO devices memory base address (r/w/x) */ |
#define IO_BASE_ADDRESS 0xFFFFFF80 |
#define IO_BASE_ADDRESS (0xFFFFFF80UL) |
/**@}*/ |
|
|
226,9 → 242,9
**************************************************************************/ |
/**@{*/ |
/** GPIO parallel input port (r/-) */ |
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80)) |
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80UL)) |
/** GPIO parallel output port (r/w) */ |
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84)) |
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL)) |
/**@}*/ |
|
|
237,7 → 253,7
**************************************************************************/ |
/**@{*/ |
/** CLIC control register (r/w) */ |
#define CLIC_CT (*(IO_REG32 0xFFFFFF88)) |
#define CLIC_CT (*(IO_REG32 0xFFFFFF88UL)) |
|
/** CLIC control register bits */ |
enum NEORV32_CLIC_CT_enum { |
284,7 → 300,7
**************************************************************************/ |
/**@{*/ |
/** Watchdog control register (r/w) */ |
#define WDT_CT (*(IO_REG32 0xFFFFFF8C)) |
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL)) |
|
/** WTD control register bits */ |
enum NEORV32_WDT_CT_enum { |
310,13 → 326,13
**************************************************************************/ |
/**@{*/ |
/** MTIME (time register) low word (r/-) */ |
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90)) |
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL)) |
/** MTIME (time register) high word (r/-) */ |
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94)) |
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL)) |
/** MTIMECMP (time compare register) low word (r/w) */ |
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98)) |
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL)) |
/** MTIMECMP (time register) high word (r/w) */ |
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9C)) |
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL)) |
|
/** MTIME (time register) 64-bit access (r/-) */ |
#define MTIME (*(IO_ROM64 (&MTIME_LO))) |
330,9 → 346,9
**************************************************************************/ |
/**@{*/ |
/** UART control register (r/w) */ |
#define UART_CT (*(IO_REG32 0xFFFFFFA0)) |
#define UART_CT (*(IO_REG32 0xFFFFFFA0UL)) |
/** UART receive/transmit data register (r/w) */ |
#define UART_DATA (*(IO_REG32 0xFFFFFFA4)) |
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL)) |
|
/** UART control register bits */ |
enum NEORV32_UART_CT_enum { |
373,9 → 389,9
**************************************************************************/ |
/**@{*/ |
/** SPI control register (r/w) */ |
#define SPI_CT (*(IO_REG32 0xFFFFFFA8)) |
#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL)) |
/** SPI receive/transmit data register (r/w) */ |
#define SPI_DATA (*(IO_REG32 0xFFFFFFAC)) |
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL)) |
|
/** SPI control register bits */ |
enum NEORV32_SPI_CT_enum { |
409,9 → 425,9
**************************************************************************/ |
/**@{*/ |
/** TWI control register (r/w) */ |
#define TWI_CT (*(IO_REG32 0xFFFFFFB0)) |
#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL)) |
/** TWI receive/transmit data register (r/w) */ |
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4)) |
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL)) |
|
/** TWI control register bits */ |
enum NEORV32_TWI_CT_enum { |
441,9 → 457,9
**************************************************************************/ |
/**@{*/ |
/** PWM control register (r/w) */ |
#define PWM_CT (*(IO_REG32 0xFFFFFFB8)) // r/w: control register |
#define PWM_CT (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register |
/** PWM duty cycle register (4-channels) (r/w) */ |
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBC)) // r/w: duty cycle channel 1 and 0 |
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0 |
|
/** PWM control register bits */ |
enum NEORV32_PWM_CT_enum { |
472,9 → 488,9
**************************************************************************/ |
/**@{*/ |
/** TRNG control register (r/w) */ |
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0)) |
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0UL)) |
/** TRNG data register (r/-) */ |
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4)) |
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4UL)) |
|
/** TRNG control register bits */ |
enum NEORV32_TRNG_CT_enum { |
496,8 → 512,8
* @name IO Device: Dummy Device (DEVNULL) |
**************************************************************************/ |
/**@{*/ |
/** TRNG data register (r/w) */ |
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFC)) |
/** DEVNULL data register (r/w) */ |
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFCUL)) |
/**@}*/ |
|
|
/lib/include/neorv32_cpu.h
64,7 → 64,7
|
register uint32_t csr_data; |
|
asm volatile ("csrrw %[result], %[input_i], zero" : [result] "=r" (csr_data) : [input_i] "i" (csr_id)); |
asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id)); |
|
return csr_data; |
} |
80,7 → 80,7
|
register uint32_t csr_data = data; |
|
asm volatile ("csrrw zero, %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data)); |
asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data)); |
} |
|
#endif // neorv32_cpu_h |
/lib/include/neorv32_rte.h
44,7 → 44,8
|
// prototypes |
void neorv32_rte_enable_debug_mode(void); |
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)); |
int neorv32_rte_exception_uninstall(uint8_t exc_id); |
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)); |
int neorv32_rte_exception_uninstall(uint8_t exc_id); |
void neorv32_rte_print_hw_config(void); |
|
#endif // neorv32_rte_h |
/lib/source/neorv32_rte.c
43,8 → 43,10
#include "neorv32_rte.h" |
|
// Privates |
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_print_true_false(int state) __attribute__((unused)); |
static void __neorv32_rte_print_hw_version(void) __attribute__((unused)); |
|
|
/**********************************************************************//** |
151,11 → 153,13
**************************************************************************/ |
static void __neorv32_rte_debug_exc_handler(void) { |
|
neorv32_uart_printf("\n\n\n<<< NEORV32 Runtime Environment >>>\n"); |
neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n"); |
|
neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME)); |
|
uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
register uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC); |
register uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST); |
|
if (exc_cause & 0x80000000) { |
neorv32_uart_printf("INTERRUPT"); |
162,8 → 166,14
} |
else { |
neorv32_uart_printf("EXCEPTION"); |
if ((trans_cmd & (1 << 1)) == 0) { |
return_addr -= 4; |
} |
else { |
return_addr -= 2; |
} |
} |
neorv32_uart_printf(" at instruction address: 0x%x\n", neorv32_cpu_csr_read(CSR_MEPC)); |
neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr); |
|
neorv32_uart_printf("Cause: "); |
switch (exc_cause) { |
190,18 → 200,179
neorv32_uart_printf("\nFaulting address"); |
} |
neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL)); |
uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST); |
neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd); |
|
if (trans_cmd & (1 << 1)) { |
neorv32_uart_printf("(uncompr.)\n"); |
if ((trans_cmd & (1 << 1)) == 0) { |
neorv32_uart_printf("(decompressed)\n"); |
} |
|
neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC)); |
|
neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n"); |
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print hardware configuration information via UART |
**************************************************************************/ |
void neorv32_rte_print_hw_config(void) { |
|
uint32_t tmp; |
int i; |
char c; |
|
neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n"); |
|
// CPU configuration |
neorv32_uart_printf("\n-- Central Processing Unit --\n"); |
|
// Hart ID |
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID)); |
|
// HW version |
neorv32_uart_printf("Hardware version: "); |
__neorv32_rte_print_hw_version(); |
neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID)); |
|
// CPU architecture |
neorv32_uart_printf("Architecture: "); |
tmp = neorv32_cpu_csr_read(CSR_MISA); |
tmp = (tmp >> 30) & 0x03; |
if (tmp == 0) { |
neorv32_uart_printf("unknown"); |
} |
if (tmp == 1) { |
neorv32_uart_printf("RV32"); |
} |
if (tmp == 2) { |
neorv32_uart_printf("RV64"); |
} |
if (tmp == 3) { |
neorv32_uart_printf("RV128"); |
} |
|
// CPU extensions |
neorv32_uart_printf("\nCPU extensions: "); |
tmp = neorv32_cpu_csr_read(CSR_MISA); |
for (i=0; i<26; i++) { |
if (tmp & (1 << i)) { |
c = (char)('A' + i); |
neorv32_uart_putc(c); |
neorv32_uart_putc(' '); |
} |
} |
neorv32_uart_printf("(0x%x)\n", tmp); |
|
// Performance counters |
neorv32_uart_printf("CNT & time CSRs: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS)); |
|
// Clock speed |
neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK)); |
|
// Memory configuration |
neorv32_uart_printf("\n-- Memory Configuration --\n"); |
|
uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE); |
uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE); |
neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base); |
neorv32_uart_printf("Internal IMEM: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM)); |
neorv32_uart_printf("Internal IMEM as ROM: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM)); |
|
size = neorv32_cpu_csr_read(CSR_MDSPACESIZE); |
base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); |
neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base); |
neorv32_uart_printf("Internal DMEM: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM)); |
|
neorv32_uart_printf("Bootloader: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER)); |
|
neorv32_uart_printf("External interface: "); |
__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT)); |
|
// peripherals |
neorv32_uart_printf("\n-- Peripherals --\n"); |
tmp = neorv32_cpu_csr_read(CSR_MFEATURES); |
|
neorv32_uart_printf("GPIO: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO)); |
|
neorv32_uart_printf("MTIME: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME)); |
|
neorv32_uart_printf("UART: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART)); |
|
neorv32_uart_printf("SPI: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI)); |
|
neorv32_uart_printf("TWI: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI)); |
|
neorv32_uart_printf("PWM: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM)); |
|
neorv32_uart_printf("WDT: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT)); |
|
neorv32_uart_printf("CLIC: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC)); |
|
neorv32_uart_printf("TRNG: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG)); |
|
neorv32_uart_printf("DEVNULL: "); |
__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL)); |
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Private function to print true or false. |
* @note This function is used by neorv32_rte_print_hw_config(void) only. |
* |
* @param[in] state Print TRUE when !=0, print FALSE when 0 |
**************************************************************************/ |
static void __neorv32_rte_print_true_false(int state) { |
|
if (state) { |
neorv32_uart_printf("True\n"); |
} |
else { |
neorv32_uart_printf("(compr.)\n"); |
neorv32_uart_printf("False\n"); |
} |
} |
|
neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MSCRATCH)); |
|
neorv32_uart_printf("\n<<</NEORV32 Runtime Environment >>>\n\n\n"); |
/**********************************************************************//** |
* NEORV32 runtime environment: Private function to show the processor version in human-readable format. |
* @note This function is used by neorv32_rte_print_hw_config(void) only. |
**************************************************************************/ |
static void __neorv32_rte_print_hw_version(void) { |
|
uint32_t i; |
char tmp, cnt; |
uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID); |
|
for (i=0; i<4; i++) { |
|
tmp = (char)(version >> (24 - 8*i)); |
|
// serial division |
cnt = 0; |
while (tmp >= 10) { |
tmp = tmp - 10; |
cnt++; |
} |
|
if (cnt) { |
neorv32_uart_putc('0' + cnt); |
} |
neorv32_uart_putc('0' + tmp); |
if (i < 3) { |
neorv32_uart_putc('.'); |
} |
} |
} |
|