OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw
    from Rev 59 to Rev 60
    ↔ Reverse comparison
  •

Rev 59 → Rev 60

/bootloader/bootloader.c
2,9 → 2,10
// # << NEORV32 - Bootloader >> #
// # ********************************************************************************************* #
// # In order to run the bootloader on *any* CPU configuration, the bootloader should be compiled #
// # unsing the base ISA (rv32i/rv32e) only. #
// # using the base ISA (rv32i/rv32e) only. #
// # ********************************************************************************************* #
// # Boot from (internal) instruction memory, UART or SPI Flash. #
// # Bootloader executables (neorv32_exe.bin) are LITTLE-ENDIAN! #
// # #
// # The bootloader uses the primary UART (UART0) for user console interface. #
// # #
226,7 → 227,7
// Configure machine system timer interrupt for ~2Hz
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4));
 
// confiure trap handler (bare-metal, no neorv32 rte available)
// configure trap handler (bare-metal, no neorv32 rte available)
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler));
 
// active timer IRQ
250,7 → 251,7
neorv32_uart_print("\n");
start_app();
 
return 0;
return 1; // bootloader should never return
#endif
 
 
343,7 → 344,7
}
}
 
return 0; // bootloader should never return
return 1; // bootloader should never return
}
 
 
599,10 → 600,10
uint32_t i;
for (i=0; i<4; i++) {
if (src == EXE_STREAM_UART) {
data.uint8[3-i] = (uint8_t)neorv32_uart_getc();
data.uint8[i] = (uint8_t)neorv32_uart_getc();
}
else {
data.uint8[3-i] = spi_flash_read_byte(addr + i);
data.uint8[i] = spi_flash_read_byte(addr + i);
}
}
 
712,7 → 713,7
 
int i;
for (i=0; i<4; i++) {
spi_flash_write_byte(addr + i, data.uint8[3-i]);
spi_flash_write_byte(addr + i, data.uint8[i]);
}
}
 
/common/neorv32.ld
60,7 → 60,7
 
rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 4*1024 : 16*1024
ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024
iodev (rw) : ORIGIN = 0xFFFFFF00, LENGTH = 256
iodev (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512
 
}
/* ************************************************************************* */
/example/bit_manipulation/main.c File deleted
/example/bit_manipulation/neorv32_b_extension_intrinsics.h File deleted \ No newline at end of file
/example/bit_manipulation/README.md File deleted
/example/bit_manipulation/makefile File deleted
/example/blink_led/main.c
69,7 → 69,7
*
* @note This program requires the GPIO controller to be synthesized (the UART is optional).
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
/example/coremark/core_portme.c
51,7 → 51,7
#error \
"You must implement a method to measure time in barebones_clock()! This function should return current time.\n"
*/
return 0;
return 1;
}
/* Define : TIMER_RES_DIVIDER
Divider to trade off timer resolution and total time that can be
/example/demo_freeRTOS/main.c
234,6 → 234,6
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
neorv32_uart_print("ERROR! FreeRTOS has not been compiled. Use >>make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe<< to compile it.\n");
return 0;
return 1;
}
#endif
/example/demo_gpio_irq/main.c
65,7 → 65,7
* @note This program assumes high-active buttons connected to gpio.in(7:0).
* @note This program assumes high-active LEDS connected to gpio.out(7:0).
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
82,7 → 82,7
// check if GPIO unit is implemented at all
if (neorv32_gpio_available() == 0) {
neorv32_uart_print("ERROR! GPIO unit not synthesized!\n");
return 0;
return 1;
}
 
// say hello
113,7 → 113,7
 
if (install_err) {
neorv32_uart_printf("RTE install error!\n");
return 0;
return 1;
}
 
// activate fast interrupt channel 8 (which is GPIO_PIN_CHANGE)
121,7 → 121,7
 
if (install_err) {
neorv32_uart_printf("IRQ enable error!\n");
return 0;
return 1;
}
 
// activate GPIO pin-change irq only for input pins 0 to 7
/example/demo_nco/main.c
63,7 → 63,7
*
* @note This program requires the NCO and the UART modules.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
83,7 → 83,7
// check if NCO unit is implemented at all
if (neorv32_nco_available() == 0) {
neorv32_uart_printf("ERROR! NCO unit not synthesized!\n");
return 0;
return 1;
}
 
// say hello
/example/demo_neopixel/main.c
62,7 → 62,7
* @note This program requires the NEOLED controller to be synthesized (UART0 is optional).
* @note NeoPixel stripe connection: NEORV32.neoled_o -> Stripe A ("NUM_LEDS_24BIT" RGB-LEDs) -> Stripe B ("NUM_LEDS_32BIT" RGBW LEDs)
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
80,7 → 80,7
// check if NEOLED unit is implemented at all, abort if not
if (neorv32_neoled_available() == 0) {
neorv32_uart_printf("Error! No NEOLED unit synthesized!\n");
return 0;
return 1;
}
 
 
/example/demo_pwm/main.c
58,13 → 58,13
*
* @note This program requires the PWM controller to be synthesized (the UART is optional).
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
// check if PWM unit is implemented at all
if (neorv32_pwm_available() == 0) {
return 0;
return 1;
}
 
 
/example/demo_trng/main.c
61,13 → 61,13
*
* @note This program requires the UART and the TRNG to be synthesized.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main(void) {
 
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0;
return 1;
}
 
// capture all exceptions and give debug info via UART
87,7 → 87,7
// check if TRNG unit is implemented at all
if (neorv32_trng_available() == 0) {
neorv32_uart_printf("No TRNG implemented.");
return 0;
return 1;
}
 
// enable TRNG
/example/demo_twi/main.c
64,7 → 64,7
*
* @note This program requires the UART and the PWM to be synthesized.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
74,7 → 74,7
 
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0;
return 1;
}
 
 
96,7 → 96,7
// check if TWI unit is implemented at all
if (neorv32_twi_available() == 0) {
neorv32_uart_printf("No TWI unit implemented.");
return 0;
return 1;
}
 
 
/example/demo_wdt/main.c
56,18 → 56,18
*
* @note This program requires the WDT and the UART to be synthesized.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
// check if WDT unit is implemented at all
if (neorv32_wdt_available() == 0) {
return 0; // nope, no WDT unit synthesized
return 1; // nope, no WDT unit synthesized
}
 
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0; // nope, no UART unit synthesized
return 1; // nope, no UART unit synthesized
}
 
 
/example/floating_point_test/main.c
99,7 → 99,7
*
* @note This program requires the Zfinx CPU extension.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
123,20 → 123,20
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
// check if Zfinx extension is implemented at all
if (neorv32_check_zextension(CSR_MZEXT_ZFINX) == 0) {
if (neorv32_cpu_check_zext(CSR_MZEXT_ZFINX) == 0) {
neorv32_uart_print("Error! <Zfinx> extension not synthesized!\n");
return 0;
return 1;
}
 
 
// Disable compilation by default
#ifndef RUN_TEST
#warning Program HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_TEST clean_all exe<< to compile it.
#ifndef RUN_CHECK
#warning Program HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
 
// inform the user if you are actually executing this
neorv32_uart_printf("ERROR! Program has not been compiled. Use >>make USER_FLAGS+=-DRUN_TEST clean_all exe<< to compile it.\n");
neorv32_uart_printf("ERROR! Program has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");
 
return 0;
return 1;
#endif
 
 
813,12 → 813,13
if (err_cnt_total != 0) {
neorv32_uart_printf("\n%c[1m[ZFINX EXTENSION VERIFICATION FAILED!]%c[0m\n", 27, 27);
neorv32_uart_printf("%u errors in %u test cases\n", err_cnt_total, test_cnt*(uint32_t)NUM_TEST_CASES);
return 1;
}
else {
neorv32_uart_printf("\n%c[1m[Zfinx extension verification successful!]%c[0m\n", 27, 27);
return 0;
}
 
return 0;
}
 
 
/example/game_of_life/main.c
82,13 → 82,13
*
* @note This program requires the UART to be synthesized (the TRNG is optional).
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main(void) {
 
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0;
return 1;
}
 
 
/example/hello_world/main.c
57,7 → 57,7
*
* @note This program requires the UART interface to be synthesized.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
/example/hex_viewer/main.c
65,7 → 65,7
*
* @note This program requires the UART to be synthesized.
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
74,7 → 74,7
 
// check if UART unit is implemented at all
if (neorv32_uart_available() == 0) {
return 0;
return 1;
}
 
 
/example/processor_check/check.sh
0,0 → 1,38
#!/bin/bash
 
# Compiles and generates executables for all example projects from `sw/example/`, compiles and installs the default
# bootloader and compiles and installs the `sw/example/processor_check` CPU test program.
 
# Abort if any command returns != 0
set -e
 
cd $(dirname "$0")
 
# List files
#ls -al ..
#ls -al ../../bootloader
 
# Check toolchain
make check
 
# Generate executables for all example projects
make -C .. \
clean_all \
exe
 
# Compile and install bootloader
make -C ../../bootloader \
clean_all \
info \
bootloader
 
# Compile and install test application
# Redirect UART0 TX to text.io simulation output via <UART0_SIM_MODE> user flag
echo "Compiling and installing CPU (/Processor) test application"
make \
clean_all \
USER_FLAGS+=-DRUN_CHECK \
USER_FLAGS+=-DUART0_SIM_MODE \
MARCH=-march=rv32imac \
info \
all
/example/processor_check/main.c
83,7 → 83,7
*
* @note Applications has to be compiler with <USER_FLAGS+=-DRUN_CPUTEST>
*
* @return Irrelevant.
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
103,7 → 103,7
// inform the user if you are actually executing this
neorv32_uart_printf("ERROR! processor_check has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");
 
return 0;
return 1;
#endif
 
// check if this is a simulation (using primary UART0)
166,7 → 166,7
 
if (install_err) {
neorv32_uart_printf("RTE install error (%i)!\n", install_err);
return 0;
return 1;
}
 
// enable interrupt sources
789,7 → 789,7
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MTI (machine timer) IRQ: ", cnt_test);
neorv32_uart_printf("[%i] MTI (via MTIME): ", cnt_test);
 
if (neorv32_mtime_available()) {
cnt_test++;
828,7 → 828,7
// Machine software interrupt (MSI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MSI (via testbench) IRQ: ", cnt_test);
neorv32_uart_printf("[%i] MSI (via testbench): ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
cnt_test++;
856,7 → 856,7
// Machine external interrupt (MEI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MEI (via testbench) IRQ: ", cnt_test);
neorv32_uart_printf("[%i] MEI (via testbench): ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
cnt_test++;
884,7 → 884,7
// Non-maskable interrupt (NMI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] NMI (via testbench) IRQ: ", cnt_test);
neorv32_uart_printf("[%i] NMI (via testbench): ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
cnt_test++;
1691,12 → 1691,13
// final result
if (cnt_fail == 0) {
neorv32_uart_printf("%c[1m[CPU TEST COMPLETED SUCCESSFULLY!]%c[0m\n", 27, 27);
return 0;
}
else {
neorv32_uart_printf("%c[1m[CPU TEST FAILED!]%c[0m\n", 27, 27);
return 1;
}
 
return 0;
}
 
 
/image_gen/image_gen.cpp
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
47,7 → 47,7
"by Stephan Nolting\n"
"Three arguments are required.\n"
"1st: Option\n"
" -app_bin : Generate application executable binary (with header!) \n"
" -app_bin : Generate application executable binary (little-endian; with header!) \n"
" -app_img : Generate application raw executable memory image (vhdl file, no header!)\n"
" -bld_img : Generate bootloader raw executable memory image (vdhl file, no header!)\n"
"2nd: Input file (raw binary image)\n"
139,30 → 139,30
tmp |= (uint32_t)(buffer[2] << 16);
tmp |= (uint32_t)(buffer[3] << 24);
checksum += tmp; // checksum: sum complement
fputc(buffer[0], output);
fputc(buffer[1], output);
fputc(buffer[2], output);
fputc(buffer[3], output);
fputc(buffer[2], output);
fputc(buffer[1], output);
fputc(buffer[0], output);
size += 4;
}
 
rewind(output);
// header: signature
fputc((unsigned char)((signature >> 0) & 0xFF), output);
fputc((unsigned char)((signature >> 8) & 0xFF), output);
fputc((unsigned char)((signature >> 16) & 0xFF), output);
fputc((unsigned char)((signature >> 24) & 0xFF), output);
fputc((unsigned char)((signature >> 16) & 0xFF), output);
fputc((unsigned char)((signature >> 8) & 0xFF), output);
fputc((unsigned char)((signature >> 0) & 0xFF), output);
// header: size
fputc((unsigned char)((size >> 0) & 0xFF), output);
fputc((unsigned char)((size >> 8) & 0xFF), output);
fputc((unsigned char)((size >> 16) & 0xFF), output);
fputc((unsigned char)((size >> 24) & 0xFF), output);
fputc((unsigned char)((size >> 16) & 0xFF), output);
fputc((unsigned char)((size >> 8) & 0xFF), output);
fputc((unsigned char)((size >> 0) & 0xFF), output);
// header: checksum (sum complement)
checksum = (~checksum) + 1;
fputc((unsigned char)((checksum >> 0) & 0xFF), output);
fputc((unsigned char)((checksum >> 8) & 0xFF), output);
fputc((unsigned char)((checksum >> 16) & 0xFF), output);
fputc((unsigned char)((checksum >> 24) & 0xFF), output);
fputc((unsigned char)((checksum >> 16) & 0xFF), output);
fputc((unsigned char)((checksum >> 8) & 0xFF), output);
fputc((unsigned char)((checksum >> 0) & 0xFF), output);
}
 
 
172,7 → 172,7
if (option == 2) {
 
// header
sprintf(tmp_string, "-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32\n"
sprintf(tmp_string, "-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32\n"
"-- Auto-generated memory init file (for APPLICATION) from source file <%s/%s>\n"
"\n"
"library ieee;\n"
221,7 → 221,7
if (option == 3) {
 
// header
sprintf(tmp_string, "-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32\n"
sprintf(tmp_string, "-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32\n"
"-- Auto-generated memory init file (for BOOTLOADER) from source file <%s/%s>\n"
"\n"
"library ieee;\n"
/lib/include/neorv32.h
62,7 → 62,6
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */
 
CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
 
99,7 → 98,7
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */
CSR_MIP = 0x344, /**< 0x344 - mip (r/-): Machine interrupt pending register */
 
CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
332,7 → 331,6
**************************************************************************/
enum NEORV32_CSR_MSTATUS_enum {
CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
CSR_MSTATUS_UBE = 6, /**< CPU mstatus CSR (6): UBE - User-mode endianness (little-endian=0, big-endian=1) (r/-) */
CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
CSR_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
340,14 → 338,6
 
 
/**********************************************************************//**
* CPU <b>mstatush</b> CSR (r/-): Machine status - high word (RISC-V spec.)
**************************************************************************/
enum NEORV32_CSR_MSTATUSH_enum {
CSR_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine-mode endianness (little-endian=0, big-endian=1) (r/-) */
};
 
 
/**********************************************************************//**
* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
**************************************************************************/
enum NEORV32_CSR_MCOUNTEREN_enum {
506,9 → 496,9
enum NEORV32_CSR_MZEXT_enum {
CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension (I sub-extension) available when set (r/-) */
CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension (I sub-extension) available when set (r/-) */
CSR_MZEXT_ZBB = 2, /**< CPU mzext CSR (2): Zbb extension (B sub-extension) available when set (r/-) */
CSR_MZEXT_ZBS = 3, /**< CPU mzext CSR (3): Zbs extension (B sub-extension) available when set (r/-) */
CSR_MZEXT_ZBA = 4, /**< CPU mzext CSR (4): Zba extension (B sub-extension) available when set (r/-) */
//CSR_MZEXT_ZBB = 2, /**< CPU mzext CSR (2): Zbb extension (B sub-extension) available when set (r/-) */
//CSR_MZEXT_ZBS = 3, /**< CPU mzext CSR (3): Zbs extension (B sub-extension) available when set (r/-) */
//CSR_MZEXT_ZBA = 4, /**< CPU mzext CSR (4): Zba extension (B sub-extension) available when set (r/-) */
CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
CSR_MZEXT_ZXNOCNT = 7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
635,89 → 625,156
/** bootloader memory base address (r/-/x) */
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
/** peripheral/IO devices memory base address (r/w/x) */
#define IO_BASE_ADDRESS (0xFFFFFF00UL)
#define IO_BASE_ADDRESS (0xFFFFFE00UL)
/**@}*/
 
 
// ############################################################################################################################
// Peripheral/IO Devices - IO Address Space
// ############################################################################################################################
 
 
/**********************************************************************//**
* @name IO Device: Custom Functions Subsystem (CFS)
**************************************************************************/
/**@{*/
/** CFS base address */
#define CFS_BASE (0xFFFFFE00UL) // /**< CFS base address */
/** CFS address space size in bytes */
#define CFS_SIZE (64*4) // /**< CFS address space size in bytes */
 
/** custom CFS register 0 */
#define CFS_REG_0 (*(IO_REG32 0xFFFFFF00UL)) // /**< (r)/(w): CFS register 0, user-defined */
#define CFS_REG_0 (*(IO_REG32 (CFS_BASE + 0))) // /**< (r)/(w): CFS register 0, user-defined */
/** custom CFS register 1 */
#define CFS_REG_1 (*(IO_REG32 0xFFFFFF04UL)) // /**< (r)/(w): CFS register 1, user-defined */
#define CFS_REG_1 (*(IO_REG32 (CFS_BASE + 4))) // /**< (r)/(w): CFS register 1, user-defined */
/** custom CFS register 2 */
#define CFS_REG_2 (*(IO_REG32 0xFFFFFF08UL)) // /**< (r)/(w): CFS register 2, user-defined */
#define CFS_REG_2 (*(IO_REG32 (CFS_BASE + 8))) // /**< (r)/(w): CFS register 2, user-defined */
/** custom CFS register 3 */
#define CFS_REG_3 (*(IO_REG32 0xFFFFFF0CUL)) // /**< (r)/(w): CFS register 3, user-defined */
#define CFS_REG_3 (*(IO_REG32 (CFS_BASE + 12))) // /**< (r)/(w): CFS register 3, user-defined */
/** custom CFS register 4 */
#define CFS_REG_4 (*(IO_REG32 0xFFFFFF10UL)) // /**< (r)/(w): CFS register 4, user-defined */
#define CFS_REG_4 (*(IO_REG32 (CFS_BASE + 16))) // /**< (r)/(w): CFS register 4, user-defined */
/** custom CFS register 5 */
#define CFS_REG_5 (*(IO_REG32 0xFFFFFF14UL)) // /**< (r)/(w): CFS register 5, user-defined */
#define CFS_REG_5 (*(IO_REG32 (CFS_BASE + 20))) // /**< (r)/(w): CFS register 5, user-defined */
/** custom CFS register 6 */
#define CFS_REG_6 (*(IO_REG32 0xFFFFFF18UL)) // /**< (r)/(w): CFS register 6, user-defined */
#define CFS_REG_6 (*(IO_REG32 (CFS_BASE + 24))) // /**< (r)/(w): CFS register 6, user-defined */
/** custom CFS register 7 */
#define CFS_REG_7 (*(IO_REG32 0xFFFFFF1CUL)) // /**< (r)/(w): CFS register 7, user-defined */
#define CFS_REG_7 (*(IO_REG32 (CFS_BASE + 28))) // /**< (r)/(w): CFS register 7, user-defined */
/** custom CFS register 8 */
#define CFS_REG_8 (*(IO_REG32 0xFFFFFF20UL)) // /**< (r)/(w): CFS register 8, user-defined */
#define CFS_REG_8 (*(IO_REG32 (CFS_BASE + 32))) // /**< (r)/(w): CFS register 8, user-defined */
/** custom CFS register 9 */
#define CFS_REG_9 (*(IO_REG32 0xFFFFFF24UL)) // /**< (r)/(w): CFS register 9, user-defined */
#define CFS_REG_9 (*(IO_REG32 (CFS_BASE + 36))) // /**< (r)/(w): CFS register 9, user-defined */
/** custom CFS register 10 */
#define CFS_REG_10 (*(IO_REG32 0xFFFFFF28UL)) // /**< (r)/(w): CFS register 10, user-defined */
#define CFS_REG_10 (*(IO_REG32 (CFS_BASE + 40))) // /**< (r)/(w): CFS register 10, user-defined */
/** custom CFS register 11 */
#define CFS_REG_11 (*(IO_REG32 0xFFFFFF2CUL)) // /**< (r)/(w): CFS register 11, user-defined */
#define CFS_REG_11 (*(IO_REG32 (CFS_BASE + 44))) // /**< (r)/(w): CFS register 11, user-defined */
/** custom CFS register 12 */
#define CFS_REG_12 (*(IO_REG32 0xFFFFFF30UL)) // /**< (r)/(w): CFS register 12, user-defined */
#define CFS_REG_12 (*(IO_REG32 (CFS_BASE + 48))) // /**< (r)/(w): CFS register 12, user-defined */
/** custom CFS register 13 */
#define CFS_REG_13 (*(IO_REG32 0xFFFFFF34UL)) // /**< (r)/(w): CFS register 13, user-defined */
#define CFS_REG_13 (*(IO_REG32 (CFS_BASE + 52))) // /**< (r)/(w): CFS register 13, user-defined */
/** custom CFS register 14 */
#define CFS_REG_14 (*(IO_REG32 0xFFFFFF38UL)) // /**< (r)/(w): CFS register 14, user-defined */
#define CFS_REG_14 (*(IO_REG32 (CFS_BASE + 56))) // /**< (r)/(w): CFS register 14, user-defined */
/** custom CFS register 15 */
#define CFS_REG_15 (*(IO_REG32 0xFFFFFF3CUL)) // /**< (r)/(w): CFS register 15, user-defined */
#define CFS_REG_15 (*(IO_REG32 (CFS_BASE + 60))) // /**< (r)/(w): CFS register 15, user-defined */
/** custom CFS register 16 */
#define CFS_REG_16 (*(IO_REG32 0xFFFFFF40UL)) // /**< (r)/(w): CFS register 16, user-defined */
#define CFS_REG_16 (*(IO_REG32 (CFS_BASE + 64))) // /**< (r)/(w): CFS register 16, user-defined */
/** custom CFS register 17 */
#define CFS_REG_17 (*(IO_REG32 0xFFFFFF44UL)) // /**< (r)/(w): CFS register 17, user-defined */
#define CFS_REG_17 (*(IO_REG32 (CFS_BASE + 68))) // /**< (r)/(w): CFS register 17, user-defined */
/** custom CFS register 18 */
#define CFS_REG_18 (*(IO_REG32 0xFFFFFF48UL)) // /**< (r)/(w): CFS register 18, user-defined */
#define CFS_REG_18 (*(IO_REG32 (CFS_BASE + 72))) // /**< (r)/(w): CFS register 18, user-defined */
/** custom CFS register 19 */
#define CFS_REG_19 (*(IO_REG32 0xFFFFFF4CUL)) // /**< (r)/(w): CFS register 19, user-defined */
#define CFS_REG_19 (*(IO_REG32 (CFS_BASE + 76))) // /**< (r)/(w): CFS register 19, user-defined */
/** custom CFS register 20 */
#define CFS_REG_20 (*(IO_REG32 0xFFFFFF50UL)) // /**< (r)/(w): CFS register 20, user-defined */
#define CFS_REG_20 (*(IO_REG32 (CFS_BASE + 80))) // /**< (r)/(w): CFS register 20, user-defined */
/** custom CFS register 21 */
#define CFS_REG_21 (*(IO_REG32 0xFFFFFF54UL)) // /**< (r)/(w): CFS register 21, user-defined */
#define CFS_REG_21 (*(IO_REG32 (CFS_BASE + 84))) // /**< (r)/(w): CFS register 21, user-defined */
/** custom CFS register 22 */
#define CFS_REG_22 (*(IO_REG32 0xFFFFFF58UL)) // /**< (r)/(w): CFS register 22, user-defined */
#define CFS_REG_22 (*(IO_REG32 (CFS_BASE + 88))) // /**< (r)/(w): CFS register 22, user-defined */
/** custom CFS register 23 */
#define CFS_REG_23 (*(IO_REG32 0xFFFFFF5CUL)) // /**< (r)/(w): CFS register 23, user-defined */
#define CFS_REG_23 (*(IO_REG32 (CFS_BASE + 92))) // /**< (r)/(w): CFS register 23, user-defined */
/** custom CFS register 24 */
#define CFS_REG_24 (*(IO_REG32 0xFFFFFF60UL)) // /**< (r)/(w): CFS register 24, user-defined */
#define CFS_REG_24 (*(IO_REG32 (CFS_BASE + 96))) // /**< (r)/(w): CFS register 24, user-defined */
/** custom CFS register 25 */
#define CFS_REG_25 (*(IO_REG32 0xFFFFFF64UL)) // /**< (r)/(w): CFS register 25, user-defined */
#define CFS_REG_25 (*(IO_REG32 (CFS_BASE + 100))) // /**< (r)/(w): CFS register 25, user-defined */
/** custom CFS register 26 */
#define CFS_REG_26 (*(IO_REG32 0xFFFFFF68UL)) // /**< (r)/(w): CFS register 26, user-defined */
#define CFS_REG_26 (*(IO_REG32 (CFS_BASE + 104))) // /**< (r)/(w): CFS register 26, user-defined */
/** custom CFS register 27 */
#define CFS_REG_27 (*(IO_REG32 0xFFFFFF6CUL)) // /**< (r)/(w): CFS register 27, user-defined */
#define CFS_REG_27 (*(IO_REG32 (CFS_BASE + 108))) // /**< (r)/(w): CFS register 27, user-defined */
/** custom CFS register 28 */
#define CFS_REG_28 (*(IO_REG32 0xFFFFFF70UL)) // /**< (r)/(w): CFS register 28, user-defined */
#define CFS_REG_28 (*(IO_REG32 (CFS_BASE + 112))) // /**< (r)/(w): CFS register 28, user-defined */
/** custom CFS register 29 */
#define CFS_REG_29 (*(IO_REG32 0xFFFFFF74UL)) // /**< (r)/(w): CFS register 29, user-defined */
#define CFS_REG_29 (*(IO_REG32 (CFS_BASE + 116))) // /**< (r)/(w): CFS register 29, user-defined */
/** custom CFS register 30 */
#define CFS_REG_30 (*(IO_REG32 0xFFFFFF78UL)) // /**< (r)/(w): CFS register 30, user-defined */
#define CFS_REG_30 (*(IO_REG32 (CFS_BASE + 120))) // /**< (r)/(w): CFS register 30, user-defined */
/** custom CFS register 31 */
#define CFS_REG_31 (*(IO_REG32 0xFFFFFF7CUL)) // /**< (r)/(w): CFS register 31, user-defined */
#define CFS_REG_31 (*(IO_REG32 (CFS_BASE + 124))) // /**< (r)/(w): CFS register 31, user-defined */
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: Pulse Width Modulation Controller (PWM)
**************************************************************************/
/**@{*/
/** PWM base address */
#define PWM_BASE (0XFFFFFF80UL) // /**< PWM base address */
/** PWM address space size in bytes */
#define PWM_SIZE (16*4) // /**< PWM address space size in bytes */
 
/** PWM control register (r/w) */
#define PWM_CT (*(IO_REG32 (PWM_BASE + 0))) // r/w: control register
/** PWM duty cycle register 0 (r/w) */
#define PWM_DUTY0 (*(IO_REG32 (PWM_BASE + 4))) // r/w: duty cycle channel 3:0
/** PWM duty cycle register 1 (r/w) */
#define PWM_DUTY1 (*(IO_REG32 (PWM_BASE + 8))) // r/w: duty cycle channel 7:4
/** PWM duty cycle register 2 (r/w) */
#define PWM_DUTY2 (*(IO_REG32 (PWM_BASE + 12))) // r/w: duty cycle channel 11:8
/** PWM duty cycle register 3 (r/w) */
#define PWM_DUTY3 (*(IO_REG32 (PWM_BASE + 16))) // r/w: duty cycle channel 15:12
/** PWM duty cycle register 4 (r/w) */
#define PWM_DUTY4 (*(IO_REG32 (PWM_BASE + 20))) // r/w: duty cycle channel 19:16
/** PWM duty cycle register 5 (r/w) */
#define PWM_DUTY5 (*(IO_REG32 (PWM_BASE + 24))) // r/w: duty cycle channel 23:20
/** PWM duty cycle register 6 (r/w) */
#define PWM_DUTY6 (*(IO_REG32 (PWM_BASE + 28))) // r/w: duty cycle channel 27:24
/** PWM duty cycle register 7 (r/w) */
#define PWM_DUTY7 (*(IO_REG32 (PWM_BASE + 32))) // r/w: duty cycle channel 31:28
/** PWM duty cycle register 8 (r/w) */
#define PWM_DUTY8 (*(IO_REG32 (PWM_BASE + 36))) // r/w: duty cycle channel 35:32
/** PWM duty cycle register 9 (r/w) */
#define PWM_DUTY9 (*(IO_REG32 (PWM_BASE + 40))) // r/w: duty cycle channel 39:36
/** PWM duty cycle register 10 (r/w) */
#define PWM_DUTY10 (*(IO_REG32 (PWM_BASE + 44))) // r/w: duty cycle channel 43:40
/** PWM duty cycle register 11 (r/w) */
#define PWM_DUTY11 (*(IO_REG32 (PWM_BASE + 48))) // r/w: duty cycle channel 47:44
/** PWM duty cycle register 12 (r/w) */
#define PWM_DUTY12 (*(IO_REG32 (PWM_BASE + 52))) // r/w: duty cycle channel 51:48
/** PWM duty cycle register 13 (r/w) */
#define PWM_DUTY13 (*(IO_REG32 (PWM_BASE + 56))) // r/w: duty cycle channel 55:52
/** PWM duty cycle register 14 (r/w) */
#define PWM_DUTY14 (*(IO_REG32 (PWM_BASE + 60))) // r/w: duty cycle channel 59:56
 
/** PWM control register bits */
enum NEORV32_PWM_CT_enum {
PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
PWM_CT_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
PWM_CT_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
};
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
**************************************************************************/
/**@{*/
/** GPIO base address */
#define GPIO_BASE (0xFFFFFF80UL) // /**< GPIO base address */
/** GPIO address space size in bytes */
#define GPIO_SIZE (2*4) // /**< GPIO address space size in bytes */
 
/** read access: GPIO parallel input port 32-bit (r/-), write_access: pin-change IRQ for each input pin (-/w) */
#define GPIO_INPUT (*(IO_REG32 0xFFFFFF80UL))
#define GPIO_INPUT (*(IO_REG32 (GPIO_BASE + 0)))
/** GPIO parallel output port 32-bit (r/w) */
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
#define GPIO_OUTPUT (*(IO_REG32 (GPIO_BASE + 4)))
/**@}*/
 
 
725,8 → 782,13
* @name IO Device: True Random Number Generator (TRNG)
**************************************************************************/
/**@{*/
/** TRNG base address */
#define TRNG_BASE (0xFFFFFF88UL) // /**< TRNG base address */
/** TRNG address space size in bytes */
#define TRNG_SIZE (1*4) // /**< TRNG address space size in bytes */
 
/** TRNG control/data register (r/w) */
#define TRNG_CT (*(IO_REG32 0xFFFFFF88UL))
#define TRNG_CT (*(IO_REG32 (TRNG_BASE + 0)))
 
/** TRNG control/data register bits */
enum NEORV32_TRNG_CT_enum {
743,8 → 805,13
* @name IO Device: Watchdog Timer (WDT)
**************************************************************************/
/**@{*/
/** WDT base address */
#define WDT_BASE (0xFFFFFF8CUL) // /**< WDT base address */
/** WDT address space size in bytes */
#define WDT_SIZE (1*4) // /**< WDT address space size in bytes */
 
/** Watchdog control register (r/w) */
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
#define WDT_CT (*(IO_REG32 (WDT_BASE + 0)))
 
/** WTD control register bits */
enum NEORV32_WDT_CT_enum {
765,14 → 832,19
* @name IO Device: Machine System Timer (MTIME)
**************************************************************************/
/**@{*/
/** MTIME base address */
#define MTIME_BASE (0xFFFFFF90UL) // /**< MTIME base address */
/** MTIME address space size in bytes */
#define MTIME_SIZE (4*4) // /**< MTIME address space size in bytes */
 
/** MTIME (time register) low word (r/w) */
#define MTIME_LO (*(IO_REG32 0xFFFFFF90UL))
#define MTIME_LO (*(IO_REG32 (MTIME_BASE + 0)))
/** MTIME (time register) high word (r/w) */
#define MTIME_HI (*(IO_REG32 0xFFFFFF94UL))
#define MTIME_HI (*(IO_REG32 (MTIME_BASE + 4)))
/** MTIMECMP (time compare register) low word (r/w) */
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
#define MTIMECMP_LO (*(IO_REG32 (MTIME_BASE + 8)))
/** MTIMECMP (time register) high word (r/w) */
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
#define MTIMECMP_HI (*(IO_REG32 (MTIME_BASE + 12)))
 
/** MTIME (time register) 64-bit access (r/w) */
#define MTIME (*(IO_REG64 (&MTIME_LO)))
785,15 → 857,26
* @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
**************************************************************************/
/**@{*/
/** UART0 base address */
#define UART0_BASE (0xFFFFFFA0UL) // /**< UART0 base address */
/** UART0 address space size in bytes */
#define UART0_SIZE (2*4) // /**< UART0 address space size in bytes */
 
/** UART0 control register (r/w) */
#define UART0_CT (*(IO_REG32 0xFFFFFFA0UL))
#define UART0_CT (*(IO_REG32 (UART0_BASE + 0)))
/** UART0 receive/transmit data register (r/w) */
#define UART0_DATA (*(IO_REG32 0xFFFFFFA4UL))
#define UART0_DATA (*(IO_REG32 (UART0_BASE + 4)))
 
 
/** UART1 base address */
#define UART1_BASE (0xFFFFFFD0UL) // /**< UART1 base address */
/** UART1 address space size in bytes */
#define UART1_SIZE (2*4) // /**< UART1 address space size in bytes */
 
/** UART1 control register (r/w) */
#define UART1_CT (*(IO_REG32 0xFFFFFFD0UL))
#define UART1_CT (*(IO_REG32 (UART1_BASE + 0)))
/** UART1 receive/transmit data register (r/w) */
#define UART1_DATA (*(IO_REG32 0xFFFFFFD4UL))
#define UART1_DATA (*(IO_REG32 (UART1_BASE + 4)))
 
/** UART0/UART1 control register bits */
enum NEORV32_UART_CT_enum {
856,10 → 939,15
* @name IO Device: Serial Peripheral Interface Controller (SPI)
**************************************************************************/
/**@{*/
/** SPI base address */
#define SPI_BASE (0xFFFFFFA8UL) // /**< SPI base address */
/** SPI address space size in bytes */
#define SPI_SIZE (2*4) // /**< SPI address space size in bytes */
 
/** SPI control register (r/w) */
#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL))
#define SPI_CT (*(IO_REG32 (SPI_BASE + 0)))
/** SPI receive/transmit data register (r/w) */
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
#define SPI_DATA (*(IO_REG32 (SPI_BASE + 4)))
 
/** SPI control register bits */
enum NEORV32_SPI_CT_enum {
888,10 → 976,15
* @name IO Device: Two-Wire Interface Controller (TWI)
**************************************************************************/
/**@{*/
/** TWI base address */
#define TWI_BASE (0xFFFFFFB0UL) // /**< TWI base address */
/** TWI address space size in bytes */
#define TWI_SIZE (2*4) // /**< TWI address space size in bytes */
 
/** TWI control register (r/w) */
#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL))
#define TWI_CT (*(IO_REG32 (TWI_BASE + 0)))
/** TWI receive/transmit data register (r/w) */
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
#define TWI_DATA (*(IO_REG32 (TWI_BASE + 4)))
 
/** TWI control register bits */
enum NEORV32_TWI_CT_enum {
917,48 → 1010,22
 
 
/**********************************************************************//**
* @name IO Device: Pulse Width Modulation Controller (PWM)
* @name IO Device: Numerically-Controlled Oscillator (NCO)
**************************************************************************/
/**@{*/
/** PWM control register (r/w) */
#define PWM_CT (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
/** PWM duty cycle register (4-channels) (r/w) */
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
/** NCO base address */
#define NCO_BASE (0xFFFFFFC0UL) // /**< NCO base address */
/** NCO address space size in bytes */
#define NCO_SIZE (4*4) // /**< NCO address space size in bytes */
 
/** PWM control register bits */
enum NEORV32_PWM_CT_enum {
PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
PWM_CT_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
PWM_CT_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
};
 
/**PWM duty cycle register bits */
enum NEORV32_PWM_DUTY_enum {
PWM_DUTY_CH0_LSB = 0, /**< PWM duty cycle register(0) (r/w): Channel 0 duty cycle (8-bit) LSB */
PWM_DUTY_CH0_MSB = 7, /**< PWM duty cycle register(7) (r/w): Channel 0 duty cycle (8-bit) MSB */
PWM_DUTY_CH1_LSB = 8, /**< PWM duty cycle register(8) (r/w): Channel 1 duty cycle (8-bit) LSB */
PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
PWM_DUTY_CH3_MSB = 31 /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
};
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: Numerically-Controlled Oscillator (NCO)
**************************************************************************/
/**@{*/
/** NCO control register (r/w) */
#define NCO_CT (*(IO_REG32 0xFFFFFFC0UL)) // r/w: control register
#define NCO_CT (*(IO_REG32 (NCO_BASE + 0))) // r/w: control register
/** NCO channel 0 tuning word (r/w) */
#define NCO_TUNE_CH0 (*(IO_REG32 0xFFFFFFC4UL)) // r/w: tuning word channel 0
#define NCO_TUNE_CH0 (*(IO_REG32 (NCO_BASE + 4))) // r/w: tuning word channel 0
/** NCO channel 1 tuning word (r/w) */
#define NCO_TUNE_CH1 (*(IO_REG32 0xFFFFFFC8UL)) // r/w: tuning word channel 1
#define NCO_TUNE_CH1 (*(IO_REG32 (NCO_BASE + 8))) // r/w: tuning word channel 1
/** NCO channel 2 tuning word (r/w) */
#define NCO_TUNE_CH2 (*(IO_REG32 0xFFFFFFCCUL)) // r/w: tuning word channel 2
#define NCO_TUNE_CH2 (*(IO_REG32 (NCO_BASE + 12))) // r/w: tuning word channel 2
 
/** NCO control register bits */
enum NEORV32_NCO_CT_enum {
1007,10 → 1074,15
* @name IO Device: Smart LED Hardware Interface (NEOLED)
**************************************************************************/
/**@{*/
/** NEOLED base address */
#define NEOLED_BASE (0xFFFFFFD8UL) // /**< NEOLED base address */
/** NEOLED address space size in bytes */
#define NEOLED_SIZE (2*4) // /**< NEOLED address space size in bytes */
 
/** NEOLED control register (r/w) */
#define NEOLED_CT (*(IO_REG32 0xFFFFFFD8UL)) // r/w: control register
#define NEOLED_CT (*(IO_REG32 (NEOLED_BASE + 0))) // r/w: control register
/** NEOLED TX data register (-/w) */
#define NEOLED_DATA (*(IO_REG32 0xFFFFFFDCUL)) // -/w: TX data register
#define NEOLED_DATA (*(IO_REG32 (NEOLED_BASE + 4))) // -/w: TX data register
 
/** NEOLED control register bits */
enum NEORV32_NEOLED_CT_enum {
1054,22 → 1126,27
* @name IO Device: System Configuration Info Memory (SYSINFO)
**************************************************************************/
/**@{*/
/** NEOLED base address */
#define SYSINFO_BASE (0xFFFFFFE0UL) // /**< SYSINFO base address */
/** NEOLED address space size in bytes */
#define SYSINFO_SIZE (8*4) // /**< SYSINFO address space size in bytes */
 
/** SYSINFO(0): Clock speed */
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
#define SYSINFO_CLK (*(IO_ROM32 (SYSINFO_BASE + 0)))
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
#define SYSINFO_USER_CODE (*(IO_ROM32 0xFFFFFFE4UL))
#define SYSINFO_USER_CODE (*(IO_ROM32 (SYSINFO_BASE + 4)))
/** SYSINFO(2): Clock speed */
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL))
#define SYSINFO_FEATURES (*(IO_ROM32 (SYSINFO_BASE + 8)))
/** SYSINFO(3): Cache configuration */
#define SYSINFO_CACHE (*(IO_ROM32 0xFFFFFFECUL))
#define SYSINFO_CACHE (*(IO_ROM32 (SYSINFO_BASE + 12)))
/** SYSINFO(4): Instruction memory address space base */
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 16)))
/** SYSINFO(5): Data memory address space base */
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 20)))
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 24)))
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 28)))
/**@}*/
 
/**********************************************************************//**
/lib/include/neorv32_cpu.h
57,7 → 57,7
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
uint32_t neorv32_cpu_hpm_get_counters(void);
uint32_t neorv32_cpu_hpm_get_size(void);
int neorv32_check_zextension(uint32_t);
int neorv32_cpu_check_zext(uint8_t flag_id);
 
 
/**********************************************************************//**
/lib/include/neorv32_pwm.h
48,6 → 48,8
int neorv32_pwm_available(void);
void neorv32_pwm_setup(uint8_t prsc);
void neorv32_pwm_disable(void);
int neorv32_pmw_get_num_channels(void);
void neorv32_pwm_set(uint8_t channel, uint8_t duty);
uint8_t neorv32_pwm_get(uint8_t channel);
 
#endif // neorv32_pwm_h
/lib/source/neorv32_cpu.c
47,7 → 47,7
* Unavailable extensions warning.
**************************************************************************/
#if defined __riscv_f || (__riscv_flen == 32)
#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and NOT FULLY OPERATIONAL yet!
#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and there is NO NATIVE SUPPORT BY THE COMPILER yet!
#endif
 
#if defined __riscv_d || (__riscv_flen == 64)
714,18 → 714,18
/**********************************************************************//**
* Check if certain Z* extension is available
*
* @param[in] flag Index of the Z-extension to check from #NEORV32_CSR_MZEXT_enum
* @param[in] flag_id Index of the Z-extension to check from #NEORV32_CSR_MZEXT_enum
* @return 0 if extension is NOT available, != 0 if extension is available.
**************************************************************************/
int neorv32_check_zextension(uint32_t flag) {
int neorv32_cpu_check_zext(uint8_t flag_id) {
 
// check if out of range
if (flag > 31) {
if (flag_id > 31) {
return 0;
}
 
uint32_t tmp = neorv32_cpu_csr_read(CSR_MZEXT);
if ((tmp & (1 << flag)) == 0) {
uint32_t mask = (uint32_t)(1 << flag_id);
if ((neorv32_cpu_csr_read(CSR_MZEXT) & mask) == 0) {
return 0;
}
else {
732,3 → 732,4
return 1;
}
}
 
/lib/source/neorv32_pwm.c
90,25 → 90,78
 
 
/**********************************************************************//**
* Set duty cycle for channel. The PWM duty cycle bits are listed in #NEORV32_PWM_DUTY_enum.
* Get number of implemented channels.
* @warning This function will override all duty cycle configuration registers.
*
* @param[in] channel Channel select (0..3).
* @return Number of implemented channels.
**************************************************************************/
int neorv32_pmw_get_num_channels(void) {
 
neorv32_pwm_disable();
 
uint8_t index = 0;
uint8_t cnt = 0;
 
for (index=0; index<60; index++) {
neorv32_pwm_set(index, 1);
cnt += neorv32_pwm_get(index);
}
 
return (int)cnt;
}
 
 
/**********************************************************************//**
* Set duty cycle for channel.
*
* @param[in] channel Channel select (0..59).
* @param[in] duty Duty cycle (0..255).
**************************************************************************/
void neorv32_pwm_set(uint8_t channel, uint8_t duty) {
 
channel = channel & 0x03;
if (channel > 59) {
return; // out-of-range
}
 
// compute duty-cycle offset
uint32_t reg_offset = (uint32_t)(channel / 4);
uint8_t byte_offset = channel % 4;
 
// read-modify-write
uint32_t duty_mask = 0xff;
uint32_t duty_new = (uint32_t)duty;
 
duty_mask = duty_mask << (channel * 8);
duty_new = duty_new << (channel * 8);
duty_mask = duty_mask << (byte_offset * 8);
duty_new = duty_new << (byte_offset * 8);
 
uint32_t duty_cycle = PWM_DUTY;
uint32_t duty_cycle = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
 
duty_cycle &= ~duty_mask; // clear previous duty cycle
duty_cycle |= duty_new; // set new duty cycle
 
PWM_DUTY = duty_cycle;
(*(IO_REG32 (&PWM_DUTY0 + reg_offset))) = duty_cycle;
}
 
 
/**********************************************************************//**
* Get duty cycle from channel.
*
* @param[in] channel Channel select (0..59).
* @return Duty cycle (0..255) of channel 'channel'.
**************************************************************************/
uint8_t neorv32_pwm_get(uint8_t channel) {
 
if (channel > 59) {
return 0; // out-of-range
}
 
// compute duty-cycle offset
uint32_t reg_offset = (uint32_t)(channel / 4);
uint8_t byte_offset = channel % 4;
 
// read
uint32_t tmp = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
tmp = tmp >> ((byte_offset * 8));
 
return (uint8_t)tmp;
}
/lib/source/neorv32_rte.c
296,36 → 296,21
// hardware version
neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
neorv32_rte_print_hw_version();
neorv32_uart_printf(")\n");
neorv32_uart_putc(')');
 
// CPU architecture
neorv32_uart_printf("Architecture: ");
// CPU architecture and endianness
neorv32_uart_printf("\nArchitecture: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
tmp = (tmp >> 30) & 0x03;
if (tmp == 0) {
neorv32_uart_printf("unknown");
}
if (tmp == 1) {
neorv32_uart_printf("rv32");
neorv32_uart_printf("rv32-little");
}
if (tmp == 2) {
neorv32_uart_printf("rv64");
}
if (tmp == 3) {
neorv32_uart_printf("rv128");
}
// CPU extensions
neorv32_uart_printf("\nEndianness: ");
if (neorv32_cpu_csr_read(CSR_MSTATUSH) & (1<<CSR_MSTATUSH_MBE)) {
neorv32_uart_printf("big\n");
}
else {
neorv32_uart_printf("little\n");
neorv32_uart_printf("unknown");
}
// CPU extensions
neorv32_uart_printf("Extensions: ");
neorv32_uart_printf("\nExtensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
for (i=0; i<26; i++) {
if (tmp & (1 << i)) {
343,15 → 328,7
if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
neorv32_uart_printf("Zifencei ");
}
if (tmp & (1<<CSR_MZEXT_ZBB)) {
neorv32_uart_printf("Zbb ");
}
if (tmp & (1<<CSR_MZEXT_ZBS)) {
neorv32_uart_printf("Zbs ");
}
if (tmp & (1<<CSR_MZEXT_ZBA)) {
neorv32_uart_printf("Zba ");
}
 
if (tmp & (1<<CSR_MZEXT_ZFINX)) {
neorv32_uart_printf("Zfinx ");
}
/ocd-firmware/park_loop.S
46,7 → 46,7
.equ SREG_EXECUTE_ACK, (1<<4) // -/w: CPU starts to execute program buffer
.equ SREG_EXCEPTION_ACK, (1<<5) // -/w: CPU has detected an exception
 
.file "debugger.S"
.file "park_loop.S"
.section .text
.balign 4
.option norvc
57,11 → 57,11
 
_start:
 
// entry location on ebreak in debug-mode, halt request, or return from single-stepped instruction
// BASE + 0: entry for ebreak in debug-mode, halt request, or return from single-stepped instruction
entry_normal:
jal zero, parking_loop_start
 
// entry location for exceptions - signal EXCEPTION to DM and restart parking loop
// BASE + 4: entry for exceptions - signal EXCEPTION to DM and restart parking loop
entry_exception:
csrw dscratch0, s0 // save s0 to dscratch0 so we have a general purpose register available
addi s0, zero, SREG_EXCEPTION_ACK // mask exception acknowledge flag

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