URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/common/crt0.S
42,9 → 42,6
.global _start |
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// standard CSRs |
.set mtinst, 0x34a |
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// custom CSRs |
.set CSR_MISPACEBASE, 0xfc4 // CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */ |
.set CSR_MDSPACEBASE, 0xfc5 // CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */ |
295,12 → 292,16
// -------------------------------------------- |
__crt0_neorv32_rte_is_exc: |
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// is faulting instruction compressed? |
csrr t0, mtinst |
andi t0, t0, 2 // get compression flag (bit #1): 0=compressed, 1=uncompressed |
// check if faulting instruction is compressed and adjust return address |
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lh t0, 0(ra) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception |
addi t2, zero, 3 // mask |
and t0, t0, t2 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions) |
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addi ra, ra, +2 // only this for compressed instructions |
add ra, ra, t0 // add another 2 (making +4) for uncompressed instructions |
bne t0, t2, __crt0_neorv32_rte_execute // jump if compressed instruction |
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addi ra, ra, +2 // add another 2 (making +4) for uncompressed instructions |
j __crt0_neorv32_rte_execute |
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/example/cpu_test/main.c
200,11 → 200,12
// Unaligned instruction address |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC I_ALIGN: "); |
cnt_test++; |
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// skip if C-mode is not implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) | (1<<CPU_MISA_C_EXT)) == 0) { |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_C_EXT)) == 0) { |
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cnt_test++; |
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// call unaligned address |
((void (*)(void))ADDR_UNALIGNED)(); |
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/lib/include/neorv32.h
70,7 → 70,6
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/-): Machine trap cause */ |
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
CSR_MTINST = 0x34a, /**< 0x34a - mtinst (r/-): Machine trap instruction (transformed) */ |
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/-): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/-): Machine instructions-retired counter low word */ |
/lib/source/neorv32_rte.c
157,26 → 157,29
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neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME)); |
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register uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC); |
register uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST); |
register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC); |
register uint32_t trap_inst; |
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if (exc_cause & 0x80000000) { |
// get faulting instruction |
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr)); |
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if (trap_cause & 0x80000000) { |
neorv32_uart_printf("INTERRUPT"); |
} |
else { |
neorv32_uart_printf("EXCEPTION"); |
if ((trans_cmd & (1 << 1)) == 0) { |
return_addr -= 4; |
if ((trap_inst & 3) == 3) { |
trap_addr -= 4; |
} |
else { |
return_addr -= 2; |
trap_addr -= 2; |
} |
} |
neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr); |
neorv32_uart_printf(" at instruction address: 0x%x\n", trap_addr); |
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neorv32_uart_printf("Cause: "); |
switch (exc_cause) { |
switch (trap_cause) { |
case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break; |
case 0x00000001: neorv32_uart_printf("Instruction access fault"); break; |
case 0x00000002: neorv32_uart_printf("Illegal instruction"); break; |
189,20 → 192,14
case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break; |
case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break; |
case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break; |
default: neorv32_uart_printf("Unknown (0x%x)", exc_cause); break; |
default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break; |
} |
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// fault address |
if (exc_cause == 0x00000002) { |
neorv32_uart_printf("\nFaulting instruction"); |
} |
else { |
neorv32_uart_printf("\nFaulting address"); |
} |
neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL)); |
neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd); |
neorv32_uart_printf("\nFaulting instruction: 0x%x\n", trap_inst); |
neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL)); |
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if ((trans_cmd & (1 << 1)) == 0) { |
if ((trap_inst & 3) != 3) { |
neorv32_uart_printf("(decompressed)\n"); |
} |
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