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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

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Rev 69 → Rev 70

/example/demo_xip/main.c
0,0 → 1,219
// #################################################################################################
// # << NEORV32 - Demo for the Execute In Place (XIP) Module >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file demo_xip/main.c
* @author Stephan Nolting
* @brief Demo for the the execute in place (XIP) module.
**************************************************************************/
 
#include <neorv32.h>
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE 19200
/**@}*/
 
 
/**********************************************************************//**
* @name Prototypes
**************************************************************************/
int program_xip_flash(void);
 
 
/**********************************************************************//**
* @name Simple program to be stored to the XIP flash.
* This is the "blink_led_asm" from the rv32i-version "blink_led" demo program.
**************************************************************************/
const uint32_t xip_program[] = {
0xfc800513,
0x00052023,
0x00000313,
0x0ff37313,
0x00652023,
0x00130313,
0x008000ef,
0xff1ff06f,
0x001003b7,
0xfff38393,
0x00038a63,
0xfff38393,
0x00000013,
0x00000013,
0xff1ff06f,
0x00008067
};
 
 
/**********************************************************************//**
* Main function: configure the XIP module, program a small program to the attached flash
* and run that program **from there**. The program shows an incrementing counter at the lowest
* 8-bits of the GPIO output port. This demo is meant for a SPI flash/EEPROM with 16-bit addresses.
*
* @note This program requires the XIP module, UART0 and the GPIO module.
*
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
// init UART at default baud rate, no parity bits, no HW flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// capture all exceptions and give debug info via UART
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// check if XIP module is implemented at all
if (neorv32_xip_available() == 0) {
neorv32_uart0_printf("Error! XIP module not synthesized!\n");
return 1;
}
 
 
// intro
neorv32_uart0_printf("<< XIP Demo Program >>\n\n");
 
 
// warning if i-cache is not implemented
if ((NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_ICACHE)) == 0) {
neorv32_uart0_printf("WARNING! No instruction cache implemented. The XIP program will run awfully slow...\n");
}
 
 
// reset XIP module and configure basic SPI properties
// * 1/64 clock divider
// * clock mode 0 (cpol = 0, cpha = 0)
// * flash read command = 0x03
// -> this function will also send 64 dummy clock cycles via the XIP's SPI port (with CS disabled)
if (neorv32_xip_init(CLK_PRSC_64, 0, 0, 0x03)) {
neorv32_uart0_printf("Error! XIP module setup error!\n");
return 1;
}
 
// use a helper function to store a small example program to the XIP flash
// NOTE: this (direct SPI access via the XIP module) has to be done before the actual XIP mode is enabled!
neorv32_uart0_printf("Programming XIP flash...\n");
if (program_xip_flash()) {
neorv32_uart0_printf("Error! XIP flash programming error!\n");
return 1;
}
 
// configure and enable the actual XIP mode
// * configure 2 address bytes send to the SPI flash for addressing
// * map the XIP flash to the address space starting at 0x20000000
if (neorv32_xip_start(2, 0x20000000)) {
neorv32_uart0_printf("Error! XIP mode configuration error!\n");
return 1;
}
 
// finally, jump to the XIP flash's base address we have configured to start execution **from there**
neorv32_uart0_printf("Starting Execute-In-Place program...\n");
asm volatile ("call %[dest]" : : [dest] "i" (0x20000000));
 
return 0;
}
 
 
/**********************************************************************//**
* Helper function to program the XIP flash via the direct SPI feature of the XIP module.
*
* @warning This function can only be used BEFORE the XIP-mode is activated!
* @note This function is blocking.
*
* @return Returns 0 if write was successful.
**************************************************************************/
int program_xip_flash(void) {
 
int error = 0;
uint32_t data_byte = 0;
uint32_t cnt = 0;
uint32_t flash_addr = 0;
uint32_t tmp = 0;
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} data;
 
while (1) {
 
// get data byte
data_byte = xip_program[cnt/4];
data_byte >>= (3-(cnt & 3)) * 8;
data_byte &= 0x000000FF;
 
//DEBUGGING
//neorv32_uart0_printf("Data byte %u: 0x%x\n", cnt, data_byte);
 
// set write-enable latch
// 1 byte command
data.uint32[0] = 0; // irrelevant, TX packet is MSB-aligned
data.uint32[1] = 0x06 << 24; // command: set write-enable latch
error += neorv32_xip_spi_trans(1, &data.uint64);
 
// write word
// 1 byte command, 2 bytes address, 1 byte data
tmp = 0x02 << 24; // command: byte write
tmp |= (flash_addr & 0x0000FFFF) << 8; // address
tmp |= data_byte << 0; // data byte
data.uint32[0] = 0; // irrelevant, TX packet is MSB-aligned
data.uint32[1] = tmp;
error += neorv32_xip_spi_trans(4, &data.uint64);
flash_addr++;
 
// check status register: WIP bit has to clear
while(1) {
tmp = 0x05 << 24; // read status register command
data.uint32[0] = 0; // irrelevant, TX packet is MSB-aligned
data.uint32[1] = tmp;
error += neorv32_xip_spi_trans(2, &data.uint64);
if ((data.uint32[0] & 0x01) == 0) { // WIP bit cleared?
break;
}
}
 
// done?
cnt++;
if ((cnt == ((uint32_t)sizeof(xip_program))) || (error != 0)) {
break;
}
}
 
return error;
}
/example/demo_xip/makefile
0,0 → 1,40
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include $(NEORV32_HOME)/sw/common/common.mk
/example/game_of_life/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
36,7 → 36,7
/**********************************************************************//**
* @file game_of_life/main.c
* @author Stephan Nolting
* @brief Simple blinking LED demo program using the lowest 8 bits of the GPIO.output port.
* @brief Conway's game of life in a UART terminal.
**************************************************************************/
 
#include <neorv32.h>
/example/hardware_info/main.c
0,0 → 1,85
// #################################################################################################
// # << NEORV32 - Show all available hardware configuration information >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file hardware_info/main.c
* @author Stephan Nolting
* @brief Show all available hardware configuration information.
**************************************************************************/
 
#include <neorv32.h>
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE 19200
/**@}*/
 
 
 
/**********************************************************************//**
* Main function
*
* @note This program requires the UART interface to be synthesized.
*
* @return 0 if execution was successful
**************************************************************************/
int main() {
 
// capture all exceptions and give debug info via UART
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// abort if UART0 is not implemented
if (neorv32_uart0_available() == 0) {
return 1;
}
 
// init UART at default baud rate, no parity bits, ho hw flow control
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
// show full HW config report
neorv32_rte_print_hw_config();
 
neorv32_uart0_printf("\nExecution completed.\n");
 
return 0;
}
/example/hardware_info/makefile
0,0 → 1,40
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
NEORV32_HOME ?= ../../..
 
include $(NEORV32_HOME)/sw/common/common.mk
/example/processor_check/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
55,6 → 55,8
#define ADDR_UNALIGNED_2 (0x00000002)
//** Unreachable word-aligned address */
#define ADDR_UNREACHABLE (IO_BASE_ADDRESS-4)
//**Read-only word-aligned address */
#define ADDR_READONLY ((uint32_t)&NEORV32_SYSINFO.CLK)
//** external memory base address */
#define EXT_MEM_BASE (0xF0000000)
/**@}*/
285,32 → 287,32
//}
 
 
// ----------------------------------------------------------
// Test standard RISC-V performance counter [m]instret[h]
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
PRINT_STANDARD("[%i] instret counter: ", cnt_test);
//// ----------------------------------------------------------
//// Test standard RISC-V performance counter [m]instret[h]
//// ----------------------------------------------------------
//neorv32_cpu_csr_write(CSR_MCAUSE, 0);
//PRINT_STANDARD("[%i] instret counter: ", cnt_test);
//
//cnt_test++;
//
//// make sure counter is enabled
//asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));
//
//// prepare overflow
//neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
//
//// get instruction counter HIGH
//tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);
//
//// make sure instruction counter high has incremented and there was no exception during access
//if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
// test_ok();
//}
//else {
// test_fail();
//}
 
cnt_test++;
 
// make sure counter is enabled
asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));
 
// prepare overflow
neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
 
// get instruction counter HIGH
tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);
 
// make sure instruction counter high has incremented and there was no exception during access
if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
test_ok();
}
else {
test_fail();
}
 
 
// ----------------------------------------------------------
// Test mcountinhibt: inhibit auto-inc of [m]cycle
// ----------------------------------------------------------
651,10 → 653,13
PRINT_STANDARD("[%i] L_ACC (load bus access) EXC: ", cnt_test);
cnt_test++;
 
tmp_a = (1 << BUSKEEPER_ERR_FLAG) | (1 << BUSKEEPER_ERR_TYPE);
 
// load from unreachable aligned address
neorv32_cpu_load_unsigned_word(ADDR_UNREACHABLE);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) {
if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) && // load bus access error exception
(NEORV32_BUSKEEPER.CTRL = tmp_a)) { // buskeeper: error flag + timeout error
test_ok();
}
else {
687,10 → 692,13
PRINT_STANDARD("[%i] S_ACC (store bus access) EXC: ", cnt_test);
cnt_test++;
 
tmp_a = (1 << BUSKEEPER_ERR_FLAG) | (0 << BUSKEEPER_ERR_TYPE);
 
// store to unreachable aligned address
neorv32_cpu_store_unsigned_word(ADDR_UNREACHABLE, 0);
neorv32_cpu_store_unsigned_word(ADDR_READONLY, 0);
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) && // store bus access error exception
(NEORV32_BUSKEEPER.CTRL == tmp_a)) { // buskeeper: error flag + device error
test_ok();
}
else {
1471,7 → 1479,6
}
else {
test_fail();
PRINT_STANDARD("answer: 0x%x", neorv32_cpu_csr_read(CSR_MCAUSE));
}
 
// restore original handler
1733,21 → 1740,21
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
PRINT_STANDARD("\n\n-- HPM reports LOW (%u HPMs available) --\n", num_hpm_cnts_global);
PRINT_STANDARD("#IR - Instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
//PRINT_STANDARD("#TM - Time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = "HPM_1"
PRINT_STANDARD("#CY - CLKs: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = "HPM_2"
PRINT_STANDARD("#03 - Compr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
PRINT_STANDARD("#04 - IF wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
PRINT_STANDARD("#05 - II wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
PRINT_STANDARD("#06 - ALU wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
PRINT_STANDARD("#07 - Loads: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
PRINT_STANDARD("#08 - Stores: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
PRINT_STANDARD("#09 - MEM wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
PRINT_STANDARD("#10 - Jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
PRINT_STANDARD("#11 - Branches: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
PRINT_STANDARD("#12 - Taken: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
PRINT_STANDARD("#13 - Traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
PRINT_STANDARD("#14 - Illegals: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
PRINT_STANDARD("#IR Instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
//PRINT_STANDARD("#TM Time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = "HPM_1"
PRINT_STANDARD("#CY CLKs: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = "HPM_2"
PRINT_STANDARD("#03 Compr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
PRINT_STANDARD("#04 IF wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
PRINT_STANDARD("#05 II wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
PRINT_STANDARD("#06 ALU wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
PRINT_STANDARD("#07 Loads: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
PRINT_STANDARD("#08 Stores: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
PRINT_STANDARD("#09 MEM wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
PRINT_STANDARD("#10 Jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
PRINT_STANDARD("#11 Branches: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
PRINT_STANDARD("#12 - Taken: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
PRINT_STANDARD("#13 Traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
PRINT_STANDARD("#14 Illegals: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
 
 
// ----------------------------------------------------------
/example/processor_check/run_check.sh
0,0 → 1,21
make USER_FLAGS+="-DRUN_CHECK -DUART0_SIM_MODE -DUART1_SIM_MODE -g" MARCH=rv32imac clean_all sim
/lib/include/neorv32.h
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
60,7 → 60,7
enum NEORV32_CSR_enum {
CSR_FFLAGS = 0x001, /**< 0x001 - fflags (r/w): Floating-point accrued exception flags */
CSR_FRM = 0x002, /**< 0x002 - frm (r/w): Floating-point dynamic rounding mode */
CSR_FCSR = 0x003, /**< 0x003 - fcsr (r/w): Floating-point control/staturs register (frm + fflags) */
CSR_FCSR = 0x003, /**< 0x003 - fcsr (r/w): Floating-point control/status register (frm + fflags) */
 
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
827,6 → 827,47
 
 
/**********************************************************************//**
* @name IO Device: Execute In Place Module (XIP)
**************************************************************************/
/**@{*/
/** XIP module prototype */
typedef struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_XIP_CTRL_enum) */
const uint32_t reserved; /**< offset 4: reserved */
uint32_t DATA_LO; /**< offset 8: SPI data register low */
uint32_t DATA_HI; /**< offset 12: SPI data register high */
} neorv32_xip_t;
 
/** XIP module hardware access (#neorv32_xip_t) */
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (0xFFFFFF40UL)))
 
/** XIP control/data register bits */
enum NEORV32_XIP_CTRL_enum {
XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
XIP_CTRL_PRSC1 = 2, /**< XIP control register( 2) (r/w): Clock prescaler select bit 1 */
XIP_CTRL_PRSC2 = 3, /**< XIP control register( 3) (r/w): Clock prescaler select bit 2 */
XIP_CTRL_CPOL = 4, /**< XIP control register( 4) (r/w): SPI (idle) clock polarity */
XIP_CTRL_CPHA = 5, /**< XIP control register( 5) (r/w): SPI clock phase */
XIP_CTRL_SPI_NBYTES_LSB = 6, /**< XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB */
XIP_CTRL_SPI_NBYTES_MSB = 9, /**< XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB */
XIP_CTRL_XIP_EN = 10, /**< XIP control register(10) (r/w): XIP access enable */
XIP_CTRL_XIP_ABYTES_LSB = 11, /**< XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB */
XIP_CTRL_XIP_ABYTES_MSB = 12, /**< XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB */
XIP_CTRL_RD_CMD_LSB = 13, /**< XIP control register(13) (r/w): SPI flash read command, LSB */
XIP_CTRL_RD_CMD_MSB = 20, /**< XIP control register(20) (r/w): SPI flash read command, MSB */
XIP_CTRL_PAGE_LSB = 21, /**< XIP control register(21) (r/w): XIP memory page, LSB */
XIP_CTRL_PAGE_MSB = 24, /**< XIP control register(24) (r/w): XIP memory page, MSB */
XIP_CTRL_SPI_CSEN = 25, /**< XIP control register(25) (r/w): SPI chip-select enable */
XIP_CTRL_HIGHSPEED = 26, /**< XIP control register(26) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) */
 
XIP_CTRL_PHY_BUSY = 30, /**< XIP control register(20) (r/-): SPI PHY is busy */
XIP_CTRL_XIP_BUSY = 31 /**< XIP control register(31) (r/-): XIP access in progress */
};
/**@}*/
 
 
/**********************************************************************//**
* @name IO Device: General Purpose Timer (GPTMR)
**************************************************************************/
/**@{*/
866,8 → 907,9
 
/** BUSKEEPER control/data register bits */
enum NEORV32_BUSKEEPER_CTRL_enum {
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read or write access */
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register( 0) (r/-): Bus error type: 0=device error, 1=access timeout */
BUSKEEPER_NULL_CHECK_EN = 16, /**< BUSKEEPER control register(16) (r/w): Enable NULL address check */
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/-): Sticky error flag, clears after read or write access */
};
/**@}*/
 
1007,24 → 1049,25
 
/** SPI control register bits */
enum NEORV32_SPI_CTRL_enum {
SPI_CTRL_CS0 = 0, /**< SPI control register(0) (r/w): Direct chip select line 0 (output is low when set) */
SPI_CTRL_CS1 = 1, /**< SPI control register(1) (r/w): Direct chip select line 1 (output is low when set) */
SPI_CTRL_CS2 = 2, /**< SPI control register(2) (r/w): Direct chip select line 2 (output is low when set) */
SPI_CTRL_CS3 = 3, /**< SPI control register(3) (r/w): Direct chip select line 3 (output is low when set) */
SPI_CTRL_CS4 = 4, /**< SPI control register(4) (r/w): Direct chip select line 4 (output is low when set) */
SPI_CTRL_CS5 = 5, /**< SPI control register(5) (r/w): Direct chip select line 5 (output is low when set) */
SPI_CTRL_CS6 = 6, /**< SPI control register(6) (r/w): Direct chip select line 6 (output is low when set) */
SPI_CTRL_CS7 = 7, /**< SPI control register(7) (r/w): Direct chip select line 7 (output is low when set) */
SPI_CTRL_EN = 8, /**< SPI control register(8) (r/w): SPI unit enable */
SPI_CTRL_CPHA = 9, /**< SPI control register(9) (r/w): Clock phase */
SPI_CTRL_PRSC0 = 10, /**< SPI control register(10) (r/w): Clock prescaler select bit 0 */
SPI_CTRL_PRSC1 = 11, /**< SPI control register(11) (r/w): Clock prescaler select bit 1 */
SPI_CTRL_PRSC2 = 12, /**< SPI control register(12) (r/w): Clock prescaler select bit 2 */
SPI_CTRL_SIZE0 = 13, /**< SPI control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
SPI_CTRL_SIZE1 = 14, /**< SPI control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
SPI_CTRL_CPOL = 15, /**< SPI control register(15) (r/w): Clock polarity */
SPI_CTRL_CS0 = 0, /**< SPI control register(0) (r/w): Direct chip select line 0 (output is low when set) */
SPI_CTRL_CS1 = 1, /**< SPI control register(1) (r/w): Direct chip select line 1 (output is low when set) */
SPI_CTRL_CS2 = 2, /**< SPI control register(2) (r/w): Direct chip select line 2 (output is low when set) */
SPI_CTRL_CS3 = 3, /**< SPI control register(3) (r/w): Direct chip select line 3 (output is low when set) */
SPI_CTRL_CS4 = 4, /**< SPI control register(4) (r/w): Direct chip select line 4 (output is low when set) */
SPI_CTRL_CS5 = 5, /**< SPI control register(5) (r/w): Direct chip select line 5 (output is low when set) */
SPI_CTRL_CS6 = 6, /**< SPI control register(6) (r/w): Direct chip select line 6 (output is low when set) */
SPI_CTRL_CS7 = 7, /**< SPI control register(7) (r/w): Direct chip select line 7 (output is low when set) */
SPI_CTRL_EN = 8, /**< SPI control register(8) (r/w): SPI unit enable */
SPI_CTRL_CPHA = 9, /**< SPI control register(9) (r/w): Clock phase */
SPI_CTRL_PRSC0 = 10, /**< SPI control register(10) (r/w): Clock prescaler select bit 0 */
SPI_CTRL_PRSC1 = 11, /**< SPI control register(11) (r/w): Clock prescaler select bit 1 */
SPI_CTRL_PRSC2 = 12, /**< SPI control register(12) (r/w): Clock prescaler select bit 2 */
SPI_CTRL_SIZE0 = 13, /**< SPI control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
SPI_CTRL_SIZE1 = 14, /**< SPI control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
SPI_CTRL_CPOL = 15, /**< SPI control register(15) (r/w): Clock polarity */
SPI_CTRL_HIGHSPEED = 16, /**< SPI control register(16) (r/w): SPI high-speed mode enable (ignoring SPI_CTRL_PRSC) */
 
SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
};
/**@}*/
 
1122,8 → 1165,8
/**@{*/
/** GPIO module prototype */
typedef struct __attribute__((packed,aligned(4))) {
const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit */
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit */
const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit, read-only */
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit, read-only */
uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */
} neorv32_gpio_t;
1191,7 → 1234,7
* @name IO Device: System Configuration Information Memory (SYSINFO)
**************************************************************************/
/**@{*/
/** SYSINFO module prototype */
/** SYSINFO module prototype - whole module is read-only */
typedef struct __attribute__((packed,aligned(4))) {
const uint32_t CLK; /**< offset 0: clock speed in Hz */
const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */
1249,7 → 1292,8
SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
SYSINFO_SOC_IO_XIRQ = 28, /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
SYSINFO_SOC_IO_GPTMR = 29 /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
SYSINFO_SOC_IO_GPTMR = 29, /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
SYSINFO_SOC_IO_XIP = 30 /**< SYSINFO_FEATURES (30) (r/-): Execute in place module implemented when 1 (via IO_XIP_EN generic) */
};
 
/** NEORV32_SYSINFO.CACHE (r/-): Cache configuration */
1302,6 → 1346,7
#include "neorv32_twi.h"
#include "neorv32_uart.h"
#include "neorv32_wdt.h"
#include "neorv32_xip.h"
#include "neorv32_xirq.h"
 
#ifdef __cplusplus
/lib/include/neorv32_spi.h
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
49,6 → 49,8
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size);
void neorv32_spi_disable(void);
void neorv32_spi_enable(void);
void neorv32_spi_highspeed_enable(void);
void neorv32_spi_highspeed_disable(void);
void neorv32_spi_cs_en(uint8_t cs);
void neorv32_spi_cs_dis(uint8_t cs);
uint32_t neorv32_spi_trans(uint32_t tx_data);
/lib/include/neorv32_xip.h
0,0 → 1,55
// #################################################################################################
// # << NEORV32: neorv32_xip.h - Execute In Place (XIP) Module HW Driver (Header) >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file neorv32_xip.h
* @author Stephan Nolting
* @brief Execute in place module (XIP) HW driver header file.
*
* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
**************************************************************************/
 
#ifndef neorv32_xip_h
#define neorv32_xip_h
 
// prototypes
int neorv32_xip_available(void);
int neorv32_xip_init(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd);
int neorv32_xip_start(uint8_t abytes, uint32_t page_base);
void neorv32_xip_highspeed_enable(void);
void neorv32_xip_highspeed_disable(void);
int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data);
 
#endif // neorv32_xip_h
/lib/source/neorv32_rte.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
272,7 → 272,7
// additional info
neorv32_uart0_print(", MTVAL=");
__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MTVAL));
neorv32_uart0_print(" </RTE>");
neorv32_uart0_print(" </RTE>\n");
}
 
 
479,6 → 479,7
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_NEOLED)); neorv32_uart0_printf(" NEOLED\n");
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_XIRQ)); neorv32_uart0_printf(" XIRQ\n");
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_GPTMR)); neorv32_uart0_printf(" GPTMR\n");
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_XIP)); neorv32_uart0_printf(" XIP\n");
}
 
 
/lib/source/neorv32_spi.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
111,6 → 111,28
 
 
/**********************************************************************//**
* Enable high-speed SPI mode (running at half of the processor clock).
*
* @note High-speed SPI mode ignores the programmed clock prescaler configuration.
**************************************************************************/
void neorv32_spi_highspeed_enable(void) {
 
NEORV32_SPI.CTRL |= 1 << SPI_CTRL_HIGHSPEED;
}
 
 
/**********************************************************************//**
* Disable high-speed SPI mode.
*
* @note High-speed SPI mode ignores the programmed clock prescaler configuration.
**************************************************************************/
void neorv32_spi_highspeed_disable(void) {
 
NEORV32_SPI.CTRL &= ~(1 << SPI_CTRL_HIGHSPEED);
}
 
 
/**********************************************************************//**
* Activate SPI chip select signal.
*
* @note The chip select output lines are LOW when activated.
/lib/source/neorv32_xip.c
0,0 → 1,216
// #################################################################################################
// # << NEORV32: neorv32_xip.c - Execute In Place (XIP) Module HW Driver (Source) >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file neorv32_xip.c
* @author Stephan Nolting
* @brief Execute in place module (XIP) HW driver source file.
*
* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
**************************************************************************/
 
#include "neorv32.h"
#include "neorv32_xip.h"
 
 
/**********************************************************************//**
* Check if XIP module was synthesized.
*
* @return 0 if XIP was not synthesized, 1 if XIP is available.
**************************************************************************/
int neorv32_xip_available(void) {
 
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_XIP)) {
return 1;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Configure XIP module: configure SPI properties.
*
* @warning This will reset the XIP module overriding the CTRL register.
* @note This function will also send 64 dummy clocks via the SPI port (with chip-select disabled).
*
* @param[in] prsc SPI clock prescaler select (0..7).
* @param[in] cpol SPI clock polarity (0/1).
* @param[in] cpha SPI clock phase(0/1).
* @param[in] rd_cmd SPI flash read command.
* @return 0 if configuration is OK, 1 if configuration error.
**************************************************************************/
int neorv32_xip_init(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd) {
 
// configuration check
if ((prsc > 7) || (cpol > 1) || (cpha > 1)) {
return 1;
}
 
// reset module
NEORV32_XIP.CTRL = 0;
 
uint32_t ctrl = 0;
 
ctrl |= ((uint32_t)(1 )) << XIP_CTRL_EN; // enable module
ctrl |= ((uint32_t)(prsc & 0x07)) << XIP_CTRL_PRSC0;
ctrl |= ((uint32_t)(cpol & 0x01)) << XIP_CTRL_CPOL;
ctrl |= ((uint32_t)(cpha & 0x01)) << XIP_CTRL_CPHA;
ctrl |= ((uint32_t)(8 )) << XIP_CTRL_SPI_NBYTES_LSB; // set 8 bytes transfer size as default
ctrl |= ((uint32_t)(rd_cmd & 0xff)) << XIP_CTRL_RD_CMD_LSB;
NEORV32_XIP.CTRL = ctrl;
 
// send 64 dummy clocks
NEORV32_XIP.DATA_LO = 0;
NEORV32_XIP.DATA_HI = 0; // trigger SPI transfer
 
// wait for transfer to complete
while(NEORV32_XIP.CTRL & (1 << XIP_CTRL_PHY_BUSY));
 
NEORV32_XIP.CTRL |= 1 << XIP_CTRL_SPI_CSEN; // finally enable SPI chip-select
 
return 0;
}
 
 
/**********************************************************************//**
* Enable XIP mode (to allow CPU to _transparently_ fetch instructions).
*
* @warning This function is blocking until the XIP mode is ready.
*
* @param[in] abytes Number of address bytes used to access the SPI flash (1,2,3,4).
* @param[in] page_base XIP memory page base address (top 4 address bits, 0..15).
* @return 0 if XIP configuration is OK, 1 if configuration error.
**************************************************************************/
int neorv32_xip_start(uint8_t abytes, uint32_t page_base) {
 
if ((abytes < 1) || (abytes > 4)) {
return 1;
}
 
if (page_base & 0x0FFFFFFF) {
return 1;
}
page_base >>= 28;
 
 
uint32_t ctrl = NEORV32_XIP.CTRL;
 
// address bytes send to SPI flash
ctrl &= ~(3 << XIP_CTRL_XIP_ABYTES_LSB); // clear old configuration
ctrl |= ((uint32_t)(abytes-1)) << XIP_CTRL_XIP_ABYTES_LSB; // set new configuration
 
// total number of bytes to transfer via SPI
// 'abytes' address bytes + 1 command byte + 4 bytes RX data (one 32-bit word)
ctrl &= ~(0xF << XIP_CTRL_SPI_NBYTES_LSB); // clear old configuration
ctrl |= ((uint32_t)(abytes+1+4)) << XIP_CTRL_SPI_NBYTES_LSB; // set new configuration
 
// XIP memory page
ctrl &= ~(0xF << XIP_CTRL_PAGE_LSB); // clear old configuration
ctrl |= ((uint32_t)(page_base & 0xf)) << XIP_CTRL_PAGE_LSB; // set new configuration
 
ctrl |= 1 << XIP_CTRL_XIP_EN; // enable XIP mode
 
NEORV32_XIP.CTRL = ctrl;
 
return 0;
}
 
 
/**********************************************************************//**
* Enable high-speed SPI mode (running at half of the processor clock).
*
* @note High-speed SPI mode ignores the programmed clock prescaler configuration.
**************************************************************************/
void neorv32_xip_highspeed_enable(void) {
 
NEORV32_XIP.CTRL |= 1 << XIP_CTRL_HIGHSPEED;
}
 
 
/**********************************************************************//**
* Disable high-speed SPI mode.
*
* @note High-speed SPI mode ignores the programmed clock prescaler configuration.
**************************************************************************/
void neorv32_xip_highspeed_disable(void) {
 
NEORV32_XIP.CTRL &= ~(1 << XIP_CTRL_HIGHSPEED);
}
 
 
/**********************************************************************//**
* Direct SPI access to the XIP flash.
*
* @warning This function can only be used BEFORE the XIP-mode is activated!
* @note This function is blocking.
*
* @param[in] nbytes Number of bytes to transfer (1..8).
* @param[in,out] rtx_data Pointer to 64-bit TX/RX data (MSB-aligned for sending, LSB-aligned for receiving (only 32-bit)).
* @return 0 if valid transfer, 1 if transfer configuration error.
**************************************************************************/
int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data) {
 
if ((nbytes == 0) || (nbytes > 8)) {
return 1;
}
 
// configure number of bytes to transfer
uint32_t ctrl = NEORV32_XIP.CTRL;
ctrl &= ~(0xF << XIP_CTRL_SPI_NBYTES_LSB); // clear old configuration
ctrl |= nbytes << XIP_CTRL_SPI_NBYTES_LSB; // set new configuration
NEORV32_XIP.CTRL = ctrl;
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} data;
 
data.uint64 = *rtx_data;
NEORV32_XIP.DATA_LO = data.uint32[0];
NEORV32_XIP.DATA_HI = data.uint32[1]; // trigger SPI transfer
 
// wait for transfer to complete
while(NEORV32_XIP.CTRL & (1 << XIP_CTRL_PHY_BUSY));
 
data.uint32[0] = NEORV32_XIP.DATA_LO;
data.uint32[1] = 0; // RX data is always 32-bit
*rtx_data = data.uint64;
 
return 0;
}
 
/svd/neorv32.svd
344,6 → 344,107
</registers>
</peripheral>
 
<!-- XIP -->
<peripheral>
<name>XIP</name>
<description>Execute In Place Module</description>
<groupName>CIP</groupName>
<baseAddress>0xFFFFFF40</baseAddress>
 
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
 
<registers>
<register>
<name>CTRL</name>
<description>Control register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>XIP_CTRL_EN</name>
<bitRange>[0:0]</bitRange>
<description>XIP module enable flag</description>
</field>
<field>
<name>XIP_CTRL_PRSC</name>
<bitRange>[3:1]</bitRange>
<description>SPI clock prescaler select</description>
</field>
<field>
<name>XIP_CTRL_CPOL</name>
<bitRange>[4:4]</bitRange>
<description>SPI clock (idle) polarity</description>
</field>
<field>
<name>XIP_CTRL_CPHA</name>
<bitRange>[5:5]</bitRange>
<description>SPI clock phase</description>
</field>
<field>
<name>XIP_CTRL_SPI_NBYTES</name>
<bitRange>[9:6]</bitRange>
<description>Number of bytes in SPI transmission</description>
</field>
<field>
<name>XIP_CTRL_XIP_EN</name>
<bitRange>[10:10]</bitRange>
<description>XIP mode enable</description>
</field>
<field>
<name>XIP_CTRL_XIP_ABYTES</name>
<bitRange>[12:11]</bitRange>
<description>Number of XIP address bytes (minus 1)</description>
</field>
<field>
<name>XIP_CTRL_RD_CMD</name>
<bitRange>[20:13]</bitRange>
<description>SPI flash read command</description>
</field>
<field>
<name>XIP_CTRL_XIP_PAGE</name>
<bitRange>[24:21]</bitRange>
<description>XIP memory page</description>
</field>
<field>
<name>XIP_CTRL_SPI_CSEN</name>
<bitRange>[25:25]</bitRange>
<description>SPI chip-select enable</description>
</field>
<field>
<name>XIP_CTRL_HIGHSPEED</name>
<bitRange>[26:26]</bitRange>
<description>SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)</description>
</field>
<field>
<name>XIP_CTRL_PHY_BUSY</name>
<bitRange>[30:30]</bitRange>
<access>read-only</access>
<description>SPI PHY busy</description>
</field>
<field>
<name>XIP_CTRL_XIP_BUSY</name>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
<description>XIP access in progress</description>
</field>
</fields>
</register>
<register>
<name>DATA_LO</name>
<description>Direct SPI access - data register low</description>
<addressOffset>0x08</addressOffset>
</register>
<register>
<name>DATA_HI</name>
<description>Direct SPI access - data register high</description>
<addressOffset>0x0C</addressOffset>
</register>
</registers>
</peripheral>
 
<!-- GPTMR -->
<peripheral>
<name>GPTMR</name>
421,6 → 522,11
<description>Bus error type: 0=device error, 1=access timeout</description>
</field>
<field>
<name>BUSKEEPER_NULL_CHECK_EN</name>
<bitRange>[16:16]</bitRange>
<description>Enable NULL address check when set</description>
</field>
<field>
<name>BUSKEEPER_ERR_FLAG</name>
<bitRange>[31:31]</bitRange>
<description>Sticky error flag, clears after read or write access</description>
732,6 → 838,11
<description>Clock polarity</description>
</field>
<field>
<name>SPI_CTRL_HIGHSPEED</name>
<bitRange>[16:16]</bitRange>
<description>SPI high-speed mode enable (ignoring SPI_CTRL_PRSC)</description>
</field>
<field>
<name>SPI_CTRL_BUSY</name>
<bitRange>[31:31]</bitRange>
<access>read-only</access>
1144,6 → 1255,7
<field><name>SYSINFO_SOC_IO_NEOLED</name><bitRange>[27:27]</bitRange><description>NeoPixel-compatible smart LED interface implemented</description></field>
<field><name>SYSINFO_SOC_IO_XIRQ</name><bitRange>[28:28]</bitRange><description>External interrupt controller implemented</description></field>
<field><name>SYSINFO_SOC_IO_GPTMR</name><bitRange>[29:29]</bitRange><description>General purpose timer implemented</description></field>
<field><name>SYSINFO_SOC_IO_XIP</name><bitRange>[30:30]</bitRange><description>Execute in place module implemented</description></field>
</fields>
</register>
<register>

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