URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/example/test_exceptions/makefile
File deleted
/example/test_exceptions/main.c
File deleted
/example/hw_analysis/makefile
File deleted
/example/hw_analysis/main.c
File deleted
/example/cpu_test/main.c
197,6 → 197,25
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// ---------------------------------------------------------- |
// Test fence instructions - make sure CPU does not crash here and throws no exception |
// ---------------------------------------------------------- |
neorv32_uart_printf("FENCE(.I): "); |
cnt_test++; |
asm volatile ("fence"); |
asm volatile ("fence.i"); |
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if (exception_handler_answer != 0) { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
else { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
exception_handler_answer = 0; |
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// ---------------------------------------------------------- |
// Unaligned instruction address |
// ---------------------------------------------------------- |
neorv32_uart_printf("EXC I_ALIGN: "); |
/lib/include/neorv32.h
134,7 → 134,7
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */ |
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension available (r/-) */ |
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */ |
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */ |
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */ |
}; |