URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw
- from Rev 73 to Rev 74
- ↔ Reverse comparison
Rev 73 → Rev 74
/isa-test/common.mk
File deleted
/isa-test/port-neorv32/README.md
File deleted
/isa-test/port-neorv32/link.imem_rom.ld
File deleted
/isa-test/port-neorv32/link.imem_ram.ld
File deleted
/isa-test/port-neorv32/model_test.h
File deleted
/bootloader/bootloader.c
565,7 → 565,8
PRINT_TEXT("Loading... "); |
|
// flash checks |
if (spi_flash_read_1st_id() == 0x00) { // check if flash ready (or available at all) |
if (((NEORV32_SYSINFO.SOC & (1<<SYSINFO_SOC_IO_SPI)) == 0x00) || // SPI module implemented? |
(spi_flash_read_1st_id() == 0x00)) { // check if flash ready (or available at all) |
system_error(ERROR_FLASH); |
} |
} |
/common/crt0.S
47,8 → 47,13
// ************************************************************************************************ |
// This is the very first instruction that is executed after hardware reset. It ensures that x0 is |
// written at least once - the CPU HW will ensure it is always set to zero on any write access. |
// |
// Furthermore, we have to disable ALL interrupts, which is required if this code is part of a |
// program uploaded by the on-chip debugger (potentionally taking control from the bootloader). |
// We setup a new stack pointer here and WE DO NOT WANT TO trap to an outdated trap handler with |
// a modified stack pointer. |
// ************************************************************************************************ |
lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all |
csrrci zero, mstatus, (1<<3) // disable global interrupt flag and write "anything" to x0 |
|
|
// ************************************************************************************************ |
/example/newlib_demo/makefile
File deleted
/example/newlib_demo/main.c
File deleted
/example/demo_newlib/main.c
0,0 → 1,142
// ################################################################################################# |
// # << NEORV32 - Newlib Demo/Test Program >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file demo_newlib/main.c |
* @author Stephan Nolting |
* @brief Demo/test program for NEORV32's newlib C standard library support. |
**************************************************************************/ |
#include <neorv32.h> |
#include <unistd.h> |
#include <stdlib.h> |
|
|
/**********************************************************************//** |
* @name User configuration |
**************************************************************************/ |
/**@{*/ |
/** UART BAUD rate */ |
#define BAUD_RATE 19200 |
/**@}*/ |
|
|
/**********************************************************************//** |
* Main function: Check some of newlib's core functions. |
* |
* @note This program requires UART0. |
* |
* @return 0 if execution was successful |
**************************************************************************/ |
int main() { |
|
// setup NEORV32 runtime environment to keep us safe |
// -> catch all traps and give debug information via UART0 |
neorv32_rte_setup(); |
|
// setup UART0 at default baud rate, no parity bits, no HW flow control |
neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE); |
|
// check if UART0 is implemented at all |
if (neorv32_uart0_available() == 0) { |
neorv32_uart0_printf("Error! UART0 not synthesized!\n"); |
return 1; |
} |
|
|
// say hello |
neorv32_uart0_printf("<<< Newlib demo/test program >>>\n\n"); |
|
|
// check if newlib is really available |
#ifndef __NEWLIB__ |
neorv32_uart0_printf("ERROR! Seems like the compiler toolchain does not support newlib...\n"); |
return -1; |
#endif |
|
neorv32_uart0_printf("newlib version %i.%i\n\n", (int32_t)__NEWLIB__, (int32_t)__NEWLIB_MINOR__); |
|
neorv32_uart0_printf("<rand> test... "); |
srand(neorv32_cpu_csr_read(CSR_CYCLE)); // set random seed |
neorv32_uart0_printf("%i, %i, %i, %i ", rand() % 100, rand() % 100, rand() % 100, rand() % 100); |
neorv32_uart0_printf("ok\n"); |
|
|
char *char_buffer; // pointer for dynamic memory allocation |
|
neorv32_uart0_printf("<malloc> test... "); |
char_buffer = (char *) malloc(4 * sizeof(char)); // 4 bytes |
neorv32_uart0_printf("ok\n"); |
|
// do not test read & write in simulation as there would be no UART RX input |
if (NEORV32_SYSINFO.SOC & (1<<SYSINFO_SOC_IS_SIM)) { |
neorv32_uart0_printf("Skipping <read> & <write> tests as this seems to be a simulation.\n"); |
} |
else { |
neorv32_uart0_printf("<read> test (waiting for 4 chars via UART0)... "); |
read((int)STDIN_FILENO, char_buffer, 4 * sizeof(char)); // get 4 chars from "STDIN" (UART0.RX) |
neorv32_uart0_printf("ok\n"); |
|
neorv32_uart0_printf("<write> test to 'STDOUT'... (outputting the chars you have send)\n"); |
write((int)STDOUT_FILENO, char_buffer, 4 * sizeof(char)); // send 4 chars to "STDOUT" (UART0.TX) |
neorv32_uart0_printf("\nok\n"); |
|
neorv32_uart0_printf("<write> test to 'STDERR'... (outputting the chars you have send)\n"); |
write((int)STDERR_FILENO, char_buffer, 4 * sizeof(char)); // send 4 chars to "STDERR" (UART0.TX) |
neorv32_uart0_printf("\nok\n"); |
} |
|
neorv32_uart0_printf("<free> test... "); |
free(char_buffer); |
neorv32_uart0_printf("ok\n"); |
|
|
// NOTE: exit is highly oversized as it also includes clean-up functions (destructors), which |
// is not required for bare-metal or RTOS applications... better use the simple 'return' or even better |
// make sure main never returns. however, let's test that 'exit' works. |
neorv32_uart0_printf("<exit> test..."); |
exit(0); |
|
return 0; // should never be reached |
} |
|
|
/**********************************************************************//** |
* "after-main" handler that is executed after the application's |
* main function returns (called by crt0.S start-up code) |
**************************************************************************/ |
void __neorv32_crt0_after_main(int32_t return_code) { |
|
neorv32_uart0_printf("\n<RTE> main function returned with exit code %i </RTE>\n", return_code); |
} |
/example/demo_newlib/makefile
0,0 → 1,40
################################################################################################# |
# << NEORV32 - Application Makefile >> # |
# ********************************************************************************************* # |
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # |
# ********************************************************************************************* # |
# BSD 3-Clause License # |
# # |
# Copyright (c) 2022, Stephan Nolting. All rights reserved. # |
# # |
# Redistribution and use in source and binary forms, with or without modification, are # |
# permitted provided that the following conditions are met: # |
# # |
# 1. Redistributions of source code must retain the above copyright notice, this list of # |
# conditions and the following disclaimer. # |
# # |
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
# conditions and the following disclaimer in the documentation and/or other materials # |
# provided with the distribution. # |
# # |
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
# endorse or promote products derived from this software without specific prior written # |
# permission. # |
# # |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
# OF THE POSSIBILITY OF SUCH DAMAGE. # |
# ********************************************************************************************* # |
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
################################################################################################# |
|
# Modify this variable to fit your NEORV32 setup (neorv32 home folder) |
NEORV32_HOME ?= ../../.. |
|
include $(NEORV32_HOME)/sw/common/common.mk |
/example/dhrystone/dhrystone.sh
1,2 → 1,6
#!/usr/bin/env bash |
|
set -e |
|
echo "Generating dhrystone executable..." |
make USER_FLAGS+="-DRUN_DHRYSTONE -DDHRY_ITERS=2000000 -DNOENUM" MARCH=rv32imc EFFORT=-O3 clean_all exe |
/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h
86,7 → 86,7
// ################################################################################################ |
|
/**********************************************************************//** |
* Flush to zero if denormal number. |
* Flush to zero if de-normal number. |
* |
* @warning Subnormal numbers are not supported yet! Flush them to zero. |
* |
97,6 → 97,7
|
float res = tmp; |
|
// flush to zero if subnormal |
if (fpclassify(tmp) == FP_SUBNORMAL) { |
if (signbit(tmp) != 0) { |
res = -0.0f; |
581,6 → 582,12
float opb = subnormal_flush(rs2); |
|
float res = opa + opb; |
|
// make NAN canonical |
if (fpclassify(res) == FP_NAN) { |
res = NAN; |
} |
|
return subnormal_flush(res); |
} |
|
598,6 → 605,12
float opb = subnormal_flush(rs2); |
|
float res = opa - opb; |
|
// make NAN canonical |
if (fpclassify(res) == FP_NAN) { |
res = NAN; |
} |
|
return subnormal_flush(res); |
} |
|
/example/processor_check/main.c
217,9 → 217,6
// test intro |
PRINT_STANDARD("\nStarting tests.\n\n"); |
|
// sync (test) |
asm volatile ("fence.i"); |
|
// enable global interrupts |
neorv32_cpu_eint(); |
|
230,12 → 227,26
|
|
// ---------------------------------------------------------- |
// Test fence instructions (just make sure CPU does not crash) |
// Test fence instructions |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
PRINT_STANDARD("[%i] FENCE(.I): ", cnt_test); |
|
cnt_test++; |
|
asm volatile ("fence"); |
asm volatile ("fence.i"); |
asm volatile ("fence"); |
asm volatile ("fence.i"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Test performance counter: setup as many events and counter as feasible |
// ---------------------------------------------------------- |
275,59 → 286,59
} |
|
|
//// ---------------------------------------------------------- |
//// Test standard RISC-V performance counter [m]cycle[h] |
//// ---------------------------------------------------------- |
//neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
//PRINT_STANDARD("[%i] cycle counter: ", cnt_test); |
// |
//cnt_test++; |
// |
//// make sure counter is enabled |
//asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_CY)); |
// |
//// prepare overflow |
//neorv32_cpu_set_mcycle(0x00000000FFFFFFFFULL); |
// |
//// get current cycle counter HIGH |
//tmp_a = neorv32_cpu_csr_read(CSR_MCYCLEH); |
// |
//// make sure cycle counter high has incremented and there was no exception during access |
//if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
// test_ok(); |
//} |
//else { |
// test_fail(); |
//} |
// ---------------------------------------------------------- |
// Test standard RISC-V performance counter [m]cycle[h] |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
PRINT_STANDARD("[%i] cycle counter: ", cnt_test); |
|
cnt_test++; |
|
//// ---------------------------------------------------------- |
//// Test standard RISC-V performance counter [m]instret[h] |
//// ---------------------------------------------------------- |
//neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
//PRINT_STANDARD("[%i] instret counter: ", cnt_test); |
// |
//cnt_test++; |
// |
//// make sure counter is enabled |
//asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR)); |
// |
//// prepare overflow |
//neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL); |
// |
//// get instruction counter HIGH |
//tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH); |
// |
//// make sure instruction counter high has incremented and there was no exception during access |
//if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
// test_ok(); |
//} |
//else { |
// test_fail(); |
//} |
// make sure counter is enabled |
asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_CY)); |
|
// prepare overflow |
neorv32_cpu_set_mcycle(0x00000000FFFFFFFFULL); |
|
// get current cycle counter HIGH |
tmp_a = neorv32_cpu_csr_read(CSR_MCYCLEH); |
|
// make sure cycle counter high has incremented and there was no exception during access |
if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Test standard RISC-V performance counter [m]instret[h] |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
PRINT_STANDARD("[%i] instret counter: ", cnt_test); |
|
cnt_test++; |
|
// make sure counter is enabled |
asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR)); |
|
// prepare overflow |
neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL); |
|
// get instruction counter HIGH |
tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH); |
|
// make sure instruction counter high has incremented and there was no exception during access |
if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Test mcountinhibt: inhibit auto-inc of [m]cycle |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
376,19 → 387,21
tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right |
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a); |
|
neorv32_cpu_csr_write(CSR_CYCLEH, 1); // make sure CSR is != 0 for this test |
neorv32_cpu_csr_write(CSR_MCYCLE, 0); |
neorv32_cpu_csr_write(CSR_MCYCLEH, 123); // make sure CSR is != 0 for this test |
|
// switch to user mode (hart will be back in MACHINE mode when trap handler returns) |
goto_user_mode(); |
{ |
// access to cycle CSR is no longer allowed |
asm volatile (" li %[result], 0xcc11aa22 \n" // initialize |
" rdcycleh %[result] " // read CSR_CYCLE, is not allowed and should not alter [result] |
: [result] "=r" (tmp_a) : ); |
asm volatile (" li %[result], 0xcc11aa22 \n" // initialize |
" csrrw %[result], cycleh, %[input] " // read and write CSR_CYCLE, not allowed and should not alter [result] nor CSR |
: [result] "=r" (tmp_a) : [input] "r" (tmp_a) ); |
} |
|
// make sure there was an illegal instruction trap |
if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) && |
(neorv32_cpu_csr_read(CSR_CYCLEH) == 123) && // csr not altered |
(tmp_a == 0xcc11aa22)) { // destination register not altered |
test_ok(); |
} |
499,26 → 512,26
} |
|
|
//// ---------------------------------------------------------- |
//// No "real" CSR write access (because rs1 = r0) |
//// ---------------------------------------------------------- |
//neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
//PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test); |
// |
//cnt_test++; |
// |
//// time CSR is read-only, but no actual write is performed because rs1=r0 |
//// -> should cause no exception |
//asm volatile("csrrs zero, time, zero"); |
// |
//if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { |
// test_ok(); |
//} |
//else { |
// test_fail(); |
//} |
// ---------------------------------------------------------- |
// No "real" CSR write access (because rs1 = r0) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
PRINT_STANDARD("[%i] Read-only CSR 'no-write' (rs1=0) access: ", cnt_test); |
|
cnt_test++; |
|
// time CSR is read-only, but no actual write is performed because rs1=r0 |
// -> should cause no exception |
asm volatile("csrrs zero, time, zero"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Unaligned instruction address |
// ---------------------------------------------------------- |
573,26 → 586,30
|
cnt_test++; |
|
// illegal 32-bit instruction (malformed SRA) |
// clear mstatus.mie and set mstatus.mpie |
tmp_a = neorv32_cpu_csr_read(CSR_MSTATUS); |
tmp_a &= ~(1 << CSR_MSTATUS_MIE); |
tmp_a |= (1 << CSR_MSTATUS_MPIE); |
neorv32_cpu_csr_write(CSR_MSTATUS, tmp_a); |
|
// illegal 32-bit instruction (MRET with incorrect opcode) |
asm volatile (".align 4 \n" |
".word 0xC0000033"); |
".word 0x3020007f"); |
|
// make sure this has cause an illegal exception |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) { |
// make sure this is really the instruction that caused the exception |
// -> for illegal instructions MTVAL contains the faulting instruction word |
if (neorv32_cpu_csr_read(CSR_MTVAL) == 0xC0000033) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) && // illegal instruction exception |
(neorv32_cpu_csr_read(CSR_MTVAL) == 0x3020007f) && // correct instruction word |
((neorv32_cpu_csr_read(CSR_MSTATUS) & (1 << CSR_MSTATUS_MIE)) == 0)) { // MIE should still be cleared |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
// clear mstatus.mie |
neorv32_cpu_dint(); |
|
|
// ---------------------------------------------------------- |
// Illegal compressed instruction |
// ---------------------------------------------------------- |
1439,7 → 1456,7
// Test WFI ("sleep") instruction (executed in user mode), wakeup via MTIME |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
PRINT_STANDARD("[%i] WFI (sleep instruction, wake-up via MTIME): ", cnt_test); |
PRINT_STANDARD("[%i] WFI (wake-up via MTIME): ", cnt_test); |
|
cnt_test++; |
|
1471,6 → 1488,31
|
|
// ---------------------------------------------------------- |
// Test unallowed WFI ("sleep") instruction (executed in user mode) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
PRINT_STANDARD("[%i] WFI (not allowed in u-mode): ", cnt_test); |
|
cnt_test++; |
|
// set mstatus.TW to disallow execution of WFI in user-mode |
neorv32_cpu_csr_write(CSR_MSTATUS, neorv32_cpu_csr_read(CSR_MSTATUS) | (1<<CSR_MSTATUS_TW)); |
|
// put CPU into sleep mode (from user mode) |
goto_user_mode(); |
{ |
asm volatile ("wfi"); // this has to fail |
} |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Test invalid CSR access in user mode |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
/example/processor_check/run_check.sh
1,2 → 1,6
#!/usr/bin/env bash |
|
set -e |
|
echo "Starting processor check simulation..." |
make USER_FLAGS+="-DRUN_CHECK -DUART0_SIM_MODE -DUART1_SIM_MODE -g" MARCH=rv32imac clean_all sim |
/image_gen/uart_upload.sh
1,4 → 1,4
#!/bin/sh |
#!/usr/bin/env bash |
|
set -e |
|
/lib/include/neorv32.h
502,35 → 502,35
* Trap codes from mcause CSR. |
**************************************************************************/ |
enum NEORV32_EXCEPTION_CODES_enum { |
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */ |
TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */ |
TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */ |
TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */ |
TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */ |
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */ |
TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */ |
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */ |
TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */ |
TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */ |
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */ |
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */ |
TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */ |
TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */ |
TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */ |
TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */ |
TRAP_CODE_FIRQ_3 = 0x80000013, /**< 1.19: Fast interrupt channel 3 */ |
TRAP_CODE_FIRQ_4 = 0x80000014, /**< 1.20: Fast interrupt channel 4 */ |
TRAP_CODE_FIRQ_5 = 0x80000015, /**< 1.21: Fast interrupt channel 5 */ |
TRAP_CODE_FIRQ_6 = 0x80000016, /**< 1.22: Fast interrupt channel 6 */ |
TRAP_CODE_FIRQ_7 = 0x80000017, /**< 1.23: Fast interrupt channel 7 */ |
TRAP_CODE_FIRQ_8 = 0x80000018, /**< 1.24: Fast interrupt channel 8 */ |
TRAP_CODE_FIRQ_9 = 0x80000019, /**< 1.25: Fast interrupt channel 9 */ |
TRAP_CODE_FIRQ_10 = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */ |
TRAP_CODE_FIRQ_11 = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */ |
TRAP_CODE_FIRQ_12 = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */ |
TRAP_CODE_FIRQ_13 = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */ |
TRAP_CODE_FIRQ_14 = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */ |
TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */ |
TRAP_CODE_I_MISALIGNED = 0x00000000UL, /**< 0.0: Instruction address misaligned */ |
TRAP_CODE_I_ACCESS = 0x00000001UL, /**< 0.1: Instruction (bus) access fault */ |
TRAP_CODE_I_ILLEGAL = 0x00000002UL, /**< 0.2: Illegal instruction */ |
TRAP_CODE_BREAKPOINT = 0x00000003UL, /**< 0.3: Breakpoint (EBREAK instruction) */ |
TRAP_CODE_L_MISALIGNED = 0x00000004UL, /**< 0.4: Load address misaligned */ |
TRAP_CODE_L_ACCESS = 0x00000005UL, /**< 0.5: Load (bus) access fault */ |
TRAP_CODE_S_MISALIGNED = 0x00000006UL, /**< 0.6: Store address misaligned */ |
TRAP_CODE_S_ACCESS = 0x00000007UL, /**< 0.7: Store (bus) access fault */ |
TRAP_CODE_UENV_CALL = 0x00000008UL, /**< 0.8: Environment call from user mode (ECALL instruction) */ |
TRAP_CODE_MENV_CALL = 0x0000000bUL, /**< 0.11: Environment call from machine mode (ECALL instruction) */ |
TRAP_CODE_MSI = 0x80000003UL, /**< 1.3: Machine software interrupt */ |
TRAP_CODE_MTI = 0x80000007UL, /**< 1.7: Machine timer interrupt */ |
TRAP_CODE_MEI = 0x8000000bUL, /**< 1.11: Machine external interrupt */ |
TRAP_CODE_FIRQ_0 = 0x80000010UL, /**< 1.16: Fast interrupt channel 0 */ |
TRAP_CODE_FIRQ_1 = 0x80000011UL, /**< 1.17: Fast interrupt channel 1 */ |
TRAP_CODE_FIRQ_2 = 0x80000012UL, /**< 1.18: Fast interrupt channel 2 */ |
TRAP_CODE_FIRQ_3 = 0x80000013UL, /**< 1.19: Fast interrupt channel 3 */ |
TRAP_CODE_FIRQ_4 = 0x80000014UL, /**< 1.20: Fast interrupt channel 4 */ |
TRAP_CODE_FIRQ_5 = 0x80000015UL, /**< 1.21: Fast interrupt channel 5 */ |
TRAP_CODE_FIRQ_6 = 0x80000016UL, /**< 1.22: Fast interrupt channel 6 */ |
TRAP_CODE_FIRQ_7 = 0x80000017UL, /**< 1.23: Fast interrupt channel 7 */ |
TRAP_CODE_FIRQ_8 = 0x80000018UL, /**< 1.24: Fast interrupt channel 8 */ |
TRAP_CODE_FIRQ_9 = 0x80000019UL, /**< 1.25: Fast interrupt channel 9 */ |
TRAP_CODE_FIRQ_10 = 0x8000001aUL, /**< 1.26: Fast interrupt channel 10 */ |
TRAP_CODE_FIRQ_11 = 0x8000001bUL, /**< 1.27: Fast interrupt channel 11 */ |
TRAP_CODE_FIRQ_12 = 0x8000001cUL, /**< 1.28: Fast interrupt channel 12 */ |
TRAP_CODE_FIRQ_13 = 0x8000001dUL, /**< 1.29: Fast interrupt channel 13 */ |
TRAP_CODE_FIRQ_14 = 0x8000001eUL, /**< 1.30: Fast interrupt channel 14 */ |
TRAP_CODE_FIRQ_15 = 0x8000001fUL /**< 1.31: Fast interrupt channel 15 */ |
}; |
|
|
664,7 → 664,7
|
|
// ############################################################################################################################ |
// On-Chip Debugger (should NOT be used by application software) |
// On-Chip Debugger (should NOT be used by application software at all!) |
// ############################################################################################################################ |
/**@{*/ |
/** on-chip debugger - debug module prototype */ |
678,8 → 678,11
const uint32_t reserved3[31]; /**< offset 388..508: reserved */ |
} neorv32_dm_t; |
|
/** on-chip debugger debug module base address */ |
#define NEORV32_DM_BASE (0XFFFFF800UL) |
|
/** on-chip debugger debug module hardware access (#neorv32_dm_t) */ |
#define NEORV32_DM (*((volatile neorv32_dm_t*) (0XFFFFF800UL))) |
#define NEORV32_DM (*((volatile neorv32_dm_t*) (NEORV32_DM_BASE))) |
|
/** on-chip debugger debug module control and status register bits */ |
enum NEORV32_OCD_DM_SREG_enum { |
730,8 → 733,11
uint32_t REG[32]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */ |
} neorv32_cfs_t; |
|
/** CFS base address */ |
#define NEORV32_CFS_BASE (0xFFFFFE00UL) |
|
/** CFS module hardware access (#neorv32_cfs_t) */ |
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (0xFFFFFE00UL))) |
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE))) |
/**@}*/ |
|
|
745,8 → 751,11
uint32_t DUTY[15]; /**< offset 4..60: duty cycle register 0..14 */ |
} neorv32_pwm_t; |
|
/** PWM module base address */ |
#define NEORV32_PWM_BASE (0xFFFFFE80UL) |
|
/** PWM module hardware access (#neorv32_pwm_t) */ |
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (0xFFFFFE80UL))) |
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (NEORV32_PWM_BASE))) |
|
/** PWM control register bits */ |
enum NEORV32_PWM_CTRL_enum { |
773,8 → 782,11
uint32_t DATA[8]; /**< offset 32..60: stream link data channel 0..7 */ |
} neorv32_slink_t; |
|
/** SLINK module base address */ |
#define NEORV32_SLINK_BASE (0xFFFFFEC0UL) |
|
/** SLINK module hardware access (#neorv32_slink_t) */ |
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (0xFFFFFEC0UL))) |
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (NEORV32_SLINK_BASE))) |
|
/** SLINK control register bits */ |
enum NEORV32_SLINK_CTRL_enum { |
885,8 → 897,11
uint32_t DATA_HI; /**< offset 12: SPI data register high */ |
} neorv32_xip_t; |
|
/** XIP module base address */ |
#define NEORV32_XIP_BASE (0xFFFFFF40UL) |
|
/** XIP module hardware access (#neorv32_xip_t) */ |
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (0xFFFFFF40UL))) |
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (NEORV32_XIP_BASE))) |
|
/** XIP control/data register bits */ |
enum NEORV32_XIP_CTRL_enum { |
926,8 → 941,11
const uint32_t reserved; /**< offset 12: reserved */ |
} neorv32_gptmr_t; |
|
/** GPTMR module base address */ |
#define NEORV32_GPTMR_BASE (0xFFFFFF60UL) |
|
/** GPTMR module hardware access (#neorv32_gptmr_t) */ |
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (0xFFFFFF60UL))) |
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))) |
|
/** GPTMR control/data register bits */ |
enum NEORV32_GPTMR_CTRL_enum { |
949,8 → 967,11
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */ |
} neorv32_buskeeper_t; |
|
/** BUSKEEPER module base address */ |
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF7CUL) |
|
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */ |
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL))) |
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE))) |
|
/** BUSKEEPER control/data register bits */ |
enum NEORV32_BUSKEEPER_CTRL_enum { |
972,8 → 993,11
const uint32_t reserved; /**< offset 12: reserved */ |
} neorv32_xirq_t; |
|
/** XIRQ module base address */ |
#define NEORV32_XIRQ_BASE (0xFFFFFF80UL) |
|
/** XIRQ module hardware access (#neorv32_xirq_t) */ |
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (0xFFFFFF80UL))) |
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (NEORV32_XIRQ_BASE))) |
/**@}*/ |
|
|
989,8 → 1013,11
uint32_t TIMECMP_HI; /**< offset 12: compare register high word */ |
} neorv32_mtime_t; |
|
/** MTIME module base address */ |
#define NEORV32_MTIME_BASE (0xFFFFFF90UL) |
|
/** MTIME module hardware access (#neorv32_mtime_t) */ |
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (0xFFFFFF90UL))) |
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (NEORV32_MTIME_BASE))) |
/**@}*/ |
|
|
1004,8 → 1031,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */ |
} neorv32_uart0_t; |
|
/** UART0 module base address */ |
#define NEORV32_UART0_BASE (0xFFFFFFA0UL) |
|
/** UART0 module hardware access (#neorv32_uart0_t) */ |
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (0xFFFFFFA0UL))) |
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (NEORV32_UART0_BASE))) |
|
/** UART1 module prototype */ |
typedef struct __attribute__((packed,aligned(4))) { |
1013,8 → 1043,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */ |
} neorv32_uart1_t; |
|
/** UART1 module base address */ |
#define NEORV32_UART1_BASE (0xFFFFFFD0UL) |
|
/** UART1 module hardware access (#neorv32_uart1_t) */ |
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (0xFFFFFFD0UL))) |
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (NEORV32_UART1_BASE))) |
|
/** UART0/UART1 control register bits */ |
enum NEORV32_UART_CTRL_enum { |
1090,8 → 1123,11
uint32_t DATA; /**< offset 4: data register */ |
} neorv32_spi_t; |
|
/** SPI module base address */ |
#define NEORV32_SPI_BASE (0xFFFFFFA8UL) |
|
/** SPI module hardware access (#neorv32_spi_t) */ |
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (0xFFFFFFA8UL))) |
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE))) |
|
/** SPI control register bits */ |
enum NEORV32_SPI_CTRL_enum { |
1128,8 → 1164,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */ |
} neorv32_twi_t; |
|
/** TWI module base address */ |
#define NEORV32_TWI_BASE (0xFFFFFFB0UL) |
|
/** TWI module hardware access (#neorv32_twi_t) */ |
#define NEORV32_TWI (*((volatile neorv32_twi_t*) (0xFFFFFFB0UL))) |
#define NEORV32_TWI (*((volatile neorv32_twi_t*) (NEORV32_TWI_BASE))) |
|
/** TWI control register bits */ |
enum NEORV32_TWI_CTRL_enum { |
1162,8 → 1201,11
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */ |
} neorv32_trng_t; |
|
/** TRNG module base address */ |
#define NEORV32_TRNG_BASE (0xFFFFFFB8UL) |
|
/** TRNG module hardware access (#neorv32_trng_t) */ |
#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (0xFFFFFFB8UL))) |
#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (NEORV32_TRNG_BASE))) |
|
/** TRNG control/data register bits */ |
enum NEORV32_TRNG_CTRL_enum { |
1185,8 → 1227,11
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */ |
} neorv32_wdt_t; |
|
/** WDT module base address */ |
#define NEORV32_WDT_BASE (0xFFFFFFBCUL) |
|
/** WDT module hardware access (#neorv32_wdt_t) */ |
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (0xFFFFFFBCUL))) |
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (NEORV32_WDT_BASE))) |
|
/** WTD control register bits */ |
enum NEORV32_WDT_CTRL_enum { |
1217,8 → 1262,11
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */ |
} neorv32_gpio_t; |
|
/** GPIO module base address */ |
#define NEORV32_GPIO_BASE (0xFFFFFFC0UL) |
|
/** GPIO module hardware access (#neorv32_gpio_t) */ |
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (0xFFFFFFC0UL))) |
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (NEORV32_GPIO_BASE))) |
/**@}*/ |
|
|
1232,8 → 1280,11
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */ |
} neorv32_neoled_t; |
|
/** NEOLED module base address */ |
#define NEORV32_NEOLED_BASE (0xFFFFFFD8UL) |
|
/** NEOLED module hardware access (#neorv32_neoled_t) */ |
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (0xFFFFFFD8UL))) |
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (NEORV32_NEOLED_BASE))) |
|
/** NEOLED control register bits */ |
enum NEORV32_NEOLED_CTRL_enum { |
1292,8 → 1343,11
const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */ |
} neorv32_sysinfo_t; |
|
/** SYSINFO module base address */ |
#define NEORV32_SYSINFO_BASE (0xFFFFFFE0UL) |
|
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */ |
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL))) |
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE))) |
|
/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */ |
enum NEORV32_SYSINFO_SOC_enum { |
/lib/include/neorv32_cfs.h
35,11 → 35,10
|
/**********************************************************************//** |
* @file neorv32_cfs.h |
* @author Stephan Nolting |
* @brief Custom Functions Subsystem (CFS)) HW driver header file. |
* |
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. |
* @warning Hence, the CFS designer has to provide the actual driver functions. |
* @warning The CFS designer has to provide the actual driver functions. |
* |
* @note These functions should only be used if the CFS was synthesized (IO_CFS_EN = true). |
**************************************************************************/ |
/lib/include/neorv32_cpu.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_cpu.h |
* @author Stephan Nolting |
* @brief CPU Core Functions HW driver header file. |
**************************************************************************/ |
|
43,17 → 42,17
#define neorv32_cpu_h |
|
// prototypes |
int neorv32_cpu_irq_enable(uint8_t irq_sel); |
int neorv32_cpu_irq_disable(uint8_t irq_sel); |
int neorv32_cpu_irq_enable(uint8_t irq_sel); |
int neorv32_cpu_irq_disable(uint8_t irq_sel); |
uint64_t neorv32_cpu_get_cycle(void); |
void neorv32_cpu_set_mcycle(uint64_t value); |
void neorv32_cpu_set_mcycle(uint64_t value); |
uint64_t neorv32_cpu_get_instret(void); |
void neorv32_cpu_set_minstret(uint64_t value); |
void neorv32_cpu_set_minstret(uint64_t value); |
uint64_t neorv32_cpu_get_systime(void); |
void neorv32_cpu_delay_ms(uint32_t time_ms); |
void neorv32_cpu_delay_ms(uint32_t time_ms); |
uint32_t neorv32_cpu_pmp_get_num_regions(void); |
uint32_t neorv32_cpu_pmp_get_granularity(void); |
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config); |
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config); |
uint32_t neorv32_cpu_hpm_get_counters(void); |
uint32_t neorv32_cpu_hpm_get_size(void); |
|
/lib/include/neorv32_cpu_cfu.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_cpu_cfu.h |
* @author Stephan Nolting |
* @brief CPU Core custom functions unit HW driver header file. |
**************************************************************************/ |
|
47,7 → 46,7
|
|
/**********************************************************************//** |
* @name CFU custom instructions (intrinsic) |
* @name CFU custom instructions ("intrinsics") |
**************************************************************************/ |
/**@{*/ |
/** CFU custom instruction 0 (funct3 = 000) */ |
/lib/include/neorv32_gpio.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_gpio.h |
* @author Stephan Nolting |
* @brief General purpose input/output port unit (GPIO) HW driver header file. |
* |
* @note These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true). |
/lib/include/neorv32_gptmr.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_gptmr.h |
* @author Stephan Nolting |
* @brief General purpose timer (GPTMR) HW driver header file. |
* |
* @note These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true). |
45,7 → 44,7
#define neorv32_gptmr_h |
|
// prototypes |
int neorv32_gptmr_available(void); |
int neorv32_gptmr_available(void); |
void neorv32_gptmr_setup(uint8_t prsc, uint8_t mode, uint32_t threshold); |
void neorv32_gptmr_disable(void); |
void neorv32_gptmr_enable(void); |
/lib/include/neorv32_intrinsics.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_intrinsics.h |
* @author Stephan Nolting, SaxonSoc contributors, Google-CFU |
* @brief Helper functions and macros for custom "intrinsics" / instructions. |
**************************************************************************/ |
|
/lib/include/neorv32_mtime.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_mtime.h |
* @author Stephan Nolting |
* @brief Machine System Timer (MTIME) HW driver header file. |
* |
* @note These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true). |
45,10 → 44,10
#define neorv32_mtime_h |
|
// prototypes |
int neorv32_mtime_available(void); |
void neorv32_mtime_set_time(uint64_t time); |
int neorv32_mtime_available(void); |
void neorv32_mtime_set_time(uint64_t time); |
uint64_t neorv32_mtime_get_time(void); |
void neorv32_mtime_set_timecmp(uint64_t timecmp); |
void neorv32_mtime_set_timecmp(uint64_t timecmp); |
uint64_t neorv32_mtime_get_timecmp(void); |
|
#endif // neorv32_mtime_h |
/lib/include/neorv32_neoled.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_neoled.h |
* @author Stephan Nolting |
* @brief Smart LED Interface (NEOLED) HW driver header file. |
* |
* @note These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true). |
45,15 → 44,15
#define neorv32_neoled_h |
|
// prototypes |
int neorv32_neoled_available(void); |
void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one); |
void neorv32_neoled_setup_ws2812(void); |
void neorv32_neoled_set_mode(uint32_t mode); |
void neorv32_neoled_strobe_blocking(void); |
void neorv32_neoled_strobe_nonblocking(void); |
void neorv32_neoled_enable(void); |
void neorv32_neoled_disable(void); |
void neorv32_neoled_write_blocking(uint32_t data); |
int neorv32_neoled_available(void); |
void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one); |
void neorv32_neoled_setup_ws2812(void); |
void neorv32_neoled_set_mode(uint32_t mode); |
void neorv32_neoled_strobe_blocking(void); |
void neorv32_neoled_strobe_nonblocking(void); |
void neorv32_neoled_enable(void); |
void neorv32_neoled_disable(void); |
void neorv32_neoled_write_blocking(uint32_t data); |
uint32_t neorv32_neoled_get_buffer_size(void); |
|
|
/lib/include/neorv32_pwm.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_pwm.h |
* @author Stephan Nolting |
* @brief Pulse-Width Modulation Controller (PWM) HW driver header file. |
* |
* @note These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true). |
45,12 → 44,12
#define neorv32_pwm_h |
|
// prototypes |
int neorv32_pwm_available(void); |
void neorv32_pwm_setup(uint8_t prsc); |
void neorv32_pwm_disable(void); |
void neorv32_pwm_enable(void); |
int neorv32_pmw_get_num_channels(void); |
void neorv32_pwm_set(uint8_t channel, uint8_t duty); |
int neorv32_pwm_available(void); |
void neorv32_pwm_setup(uint8_t prsc); |
void neorv32_pwm_disable(void); |
void neorv32_pwm_enable(void); |
int neorv32_pmw_get_num_channels(void); |
void neorv32_pwm_set(uint8_t channel, uint8_t duty); |
uint8_t neorv32_pwm_get(uint8_t channel); |
|
#endif // neorv32_pwm_h |
/lib/include/neorv32_rte.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_rte.h |
* @author Stephan Nolting |
* @brief NEORV32 Runtime Environment. |
**************************************************************************/ |
|
96,6 → 95,6
void neorv32_rte_print_license(void); |
|
uint32_t neorv32_rte_get_compiler_isa(void); |
int neorv32_rte_check_isa(int silent); |
int neorv32_rte_check_isa(int silent); |
|
#endif // neorv32_rte_h |
/lib/include/neorv32_slink.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_slink.h |
* @author Stephan Nolting |
* @brief Stream Link Interface HW driver header file. |
**************************************************************************/ |
|
43,35 → 42,35
#define neorv32_slink_h |
|
// prototypes |
int neorv32_slink_available(void); |
int neorv32_slink_available(void); |
void neorv32_slink_enable(void); |
void neorv32_slink_disable(void); |
void neorv32_slink_rx_irq_config(int link_id, int irq_en, int irq_type); |
void neorv32_slink_tx_irq_config(int link_id, int irq_en, int irq_type); |
int neorv32_slink_get_rx_num(void); |
int neorv32_slink_get_tx_num(void); |
int neorv32_slink_get_rx_depth(void); |
int neorv32_slink_get_tx_depth(void); |
int neorv32_slink_check_rx_half_full(int link_id); |
int neorv32_slink_check_tx_half_full(int link_id); |
int neorv32_slink_get_rx_num(void); |
int neorv32_slink_get_tx_num(void); |
int neorv32_slink_get_rx_depth(void); |
int neorv32_slink_get_tx_depth(void); |
int neorv32_slink_check_rx_half_full(int link_id); |
int neorv32_slink_check_tx_half_full(int link_id); |
// non-blocking transmit |
int neorv32_slink_tx0_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx1_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx2_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx3_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx4_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx5_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx6_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx7_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx0_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx1_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx2_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx3_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx4_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx5_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx6_nonblocking(uint32_t tx_data); |
int neorv32_slink_tx7_nonblocking(uint32_t tx_data); |
// non-blocking receive |
int neorv32_slink_rx0_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx1_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx2_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx3_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx4_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx5_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx6_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx7_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx0_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx1_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx2_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx3_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx4_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx5_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx6_nonblocking(uint32_t *rx_data); |
int neorv32_slink_rx7_nonblocking(uint32_t *rx_data); |
|
|
/**********************************************************************//** |
/lib/include/neorv32_spi.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_spi.h |
* @author Stephan Nolting |
* @brief Serial peripheral interface controller (SPI) HW driver header file. |
* |
* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true). |
45,17 → 44,17
#define neorv32_spi_h |
|
// prototypes |
int neorv32_spi_available(void); |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size); |
void neorv32_spi_disable(void); |
void neorv32_spi_enable(void); |
void neorv32_spi_highspeed_enable(void); |
void neorv32_spi_highspeed_disable(void); |
void neorv32_spi_cs_en(uint8_t cs); |
void neorv32_spi_cs_dis(uint8_t cs); |
int neorv32_spi_available(void); |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size); |
void neorv32_spi_disable(void); |
void neorv32_spi_enable(void); |
void neorv32_spi_highspeed_enable(void); |
void neorv32_spi_highspeed_disable(void); |
void neorv32_spi_cs_en(uint8_t cs); |
void neorv32_spi_cs_dis(uint8_t cs); |
uint32_t neorv32_spi_trans(uint32_t tx_data); |
void neorv32_spi_put_nonblocking(uint32_t tx_data); |
void neorv32_spi_put_nonblocking(uint32_t tx_data); |
uint32_t neorv32_spi_get_nonblocking(void); |
int neorv32_spi_busy(void); |
int neorv32_spi_busy(void); |
|
#endif // neorv32_spi_h |
/lib/include/neorv32_trng.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_trng.h |
* @author Stephan Nolting |
* @brief True Random Number Generator (TRNG) HW driver header file. |
* |
* @note These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true). |
45,9 → 44,9
#define neorv32_trng_h |
|
// prototypes |
int neorv32_trng_available(void); |
int neorv32_trng_available(void); |
void neorv32_trng_enable(void); |
void neorv32_trng_disable(void); |
int neorv32_trng_get(uint8_t *data); |
int neorv32_trng_get(uint8_t *data); |
|
#endif // neorv32_trng_h |
/lib/include/neorv32_twi.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_twi.h |
* @author Stephan Nolting |
* @brief Two-Wire Interface Controller (TWI) HW driver header file. |
* |
* @note These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true). |
45,17 → 44,17
#define neorv32_twi_h |
|
// prototypes |
int neorv32_twi_available(void); |
void neorv32_twi_setup(uint8_t prsc); |
void neorv32_twi_disable(void); |
void neorv32_twi_enable(void); |
void neorv32_twi_mack_enable(void); |
void neorv32_twi_mack_disable(void); |
int neorv32_twi_busy(void); |
int neorv32_twi_start_trans(uint8_t a); |
int neorv32_twi_trans(uint8_t d); |
int neorv32_twi_available(void); |
void neorv32_twi_setup(uint8_t prsc); |
void neorv32_twi_disable(void); |
void neorv32_twi_enable(void); |
void neorv32_twi_mack_enable(void); |
void neorv32_twi_mack_disable(void); |
int neorv32_twi_busy(void); |
int neorv32_twi_start_trans(uint8_t a); |
int neorv32_twi_trans(uint8_t d); |
uint8_t neorv32_twi_get_data(void); |
void neorv32_twi_generate_stop(void); |
void neorv32_twi_generate_start(void); |
void neorv32_twi_generate_stop(void); |
void neorv32_twi_generate_start(void); |
|
#endif // neorv32_twi_h |
/lib/include/neorv32_uart.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_uart.h |
* @author Stephan Nolting |
* @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file |
* |
* @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions. |
/lib/include/neorv32_wdt.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_wdt.h |
* @author Stephan Nolting |
* @brief Watchdog Timer (WDT) HW driver header file. |
* |
* @note These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true). |
45,11 → 44,11
#define neorv32_wdt_h |
|
// prototypes |
int neorv32_wdt_available(void); |
int neorv32_wdt_available(void); |
void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock); |
int neorv32_wdt_disable(void); |
int neorv32_wdt_disable(void); |
void neorv32_wdt_reset(void); |
int neorv32_wdt_get_cause(void); |
int neorv32_wdt_get_cause(void); |
void neorv32_wdt_force(void); |
|
#endif // neorv32_wdt_h |
/lib/include/neorv32_xip.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_xip.h |
* @author Stephan Nolting |
* @brief Execute in place module (XIP) HW driver header file. |
* |
* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true). |
45,11 → 44,11
#define neorv32_xip_h |
|
// prototypes |
int neorv32_xip_available(void); |
int neorv32_xip_init(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd); |
int neorv32_xip_start(uint8_t abytes, uint32_t page_base); |
int neorv32_xip_available(void); |
int neorv32_xip_init(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd); |
int neorv32_xip_start(uint8_t abytes, uint32_t page_base); |
void neorv32_xip_highspeed_enable(void); |
void neorv32_xip_highspeed_disable(void); |
int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data); |
int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data); |
|
#endif // neorv32_xip_h |
/lib/include/neorv32_xirq.h
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_xirq.h |
* @author Stephan Nolting |
* @brief External Interrupt controller HW driver header file. |
**************************************************************************/ |
|
43,17 → 42,16
#define neorv32_xirq_h |
|
// prototypes |
int neorv32_xirq_available(void); |
int neorv32_xirq_setup(void); |
int neorv32_xirq_available(void); |
int neorv32_xirq_setup(void); |
void neorv32_xirq_global_enable(void); |
void neorv32_xirq_global_disable(void); |
int neorv32_xirq_get_num(void); |
int neorv32_xirq_get_num(void); |
void neorv32_xirq_clear_pending(uint8_t ch); |
void neorv32_xirq_channel_enable(uint8_t ch); |
void neorv32_xirq_channel_disable(uint8_t ch); |
int neorv32_xirq_install(uint8_t ch, void (*handler)(void)); |
int neorv32_xirq_uninstall(uint8_t ch); |
|
int neorv32_xirq_install(uint8_t ch, void (*handler)(void)); |
int neorv32_xirq_uninstall(uint8_t ch); |
|
|
#endif // neorv32_xirq_h |
/lib/source/neorv32_cfs.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_cfs.c |
* @author Stephan Nolting |
* @brief Custom Functions Subsystem (CFS) HW driver source file. |
* |
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. |
/lib/source/neorv32_cpu.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_cpu.c |
* @author Stephan Nolting |
* @brief CPU Core Functions HW driver source file. |
**************************************************************************/ |
|
/lib/source/neorv32_cpu_cfu.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_cpu_cfu.c |
* @author Stephan Nolting |
* @brief CPU Core custom functions unit HW driver source file. |
**************************************************************************/ |
|
/lib/source/neorv32_gpio.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_gpio.c |
* @author Stephan Nolting |
* @brief General purpose input/output port unit (GPIO) HW driver source file. |
* |
* @note These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true). |
/lib/source/neorv32_gptmr.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_gptmr.c |
* @author Stephan Nolting |
* @brief General purpose timer (GPTMR) HW driver source file. |
* |
* @note These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true). |
/lib/source/neorv32_mtime.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_mtime.c |
* @author Stephan Nolting |
* @brief Machine System Timer (MTIME) HW driver source file. |
* |
* @note These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true). |
/lib/source/neorv32_neoled.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_neoled.c |
* @author Stephan Nolting |
* @brief Smart LED Interface (NEOLED) HW driver source file. |
* |
* @note These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true). |
/lib/source/neorv32_pwm.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_pwm.c |
* @author Stephan Nolting |
* @brief Pulse-Width Modulation Controller (PWM) HW driver source file. |
* |
* @note These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true). |
/lib/source/neorv32_rte.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_rte.c |
* @author Stephan Nolting |
* @brief NEORV32 Runtime Environment. |
**************************************************************************/ |
|
67,14 → 66,20
// configure trap handler base address |
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&__neorv32_rte_core)); |
|
// disable all IRQ channels |
neorv32_cpu_csr_write(CSR_MIE, 0); |
|
// clear all pending IRQs |
neorv32_cpu_csr_write(CSR_MIP, 0); |
|
// clear BUSKEEPER error flags |
NEORV32_BUSKEEPER.CTRL = 0; |
|
// install debug handler for all sources |
uint8_t id; |
for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) { |
neorv32_rte_exception_uninstall(id); // this will configure the debug handler |
} |
|
// clear BUSKEEPER error flags |
NEORV32_BUSKEEPER.CTRL = 0; |
} |
|
|
131,7 → 136,7
static void __attribute__((__interrupt__)) __attribute__((aligned(4))) __neorv32_rte_core(void) { |
|
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC); |
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later |
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // backup for later |
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE); |
|
// compute return address |
140,12 → 145,12
// get low half word of faulting instruction |
register uint32_t rte_trap_inst = neorv32_cpu_load_unsigned_half(rte_mepc); |
|
if ((rte_trap_inst & 3) == 3) { // faulting instruction is uncompressed instruction |
rte_mepc += 4; |
rte_mepc += 4; // default: faulting instruction is uncompressed |
if (neorv32_cpu_csr_read(CSR_MISA) & (1 << CSR_MISA_C)) { // C extension implemented? |
if ((rte_trap_inst & 3) != 3) { // faulting instruction is compressed instruction |
rte_mepc -= 2; |
} |
} |
else { // faulting instruction is compressed instruction |
rte_mepc += 2; |
} |
|
// store new return address |
neorv32_cpu_csr_write(CSR_MEPC, rte_mepc); |
746,7 → 751,6
// mask hardware features that are not used by software |
uint32_t check = misa_hw & misa_sw; |
|
// |
if (check == misa_sw) { |
return 0; |
} |
/lib/source/neorv32_slink.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_slink.c |
* @author Stephan Nolting |
* @brief Stream Link Interface HW driver source file. |
**************************************************************************/ |
|
/lib/source/neorv32_spi.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_spi.c |
* @author Stephan Nolting |
* @brief Serial peripheral interface controller (SPI) HW driver source file. |
* |
* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true). |
/lib/source/neorv32_trng.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_trng.c |
* @author Stephan Nolting |
* @brief True Random Number Generator (TRNG) HW driver source file. |
* |
* @note These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true). |
/lib/source/neorv32_twi.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_twi.c |
* @author Stephan Nolting |
* @brief Two-Wire Interface Controller (TWI) HW driver source file. |
* |
* @note These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true). |
/lib/source/neorv32_uart.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_uart.c |
* @author Stephan Nolting |
* @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver source file. |
* |
* @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions. |
/lib/source/neorv32_wdt.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_wdt.c |
* @author Stephan Nolting |
* @brief Watchdog Timer (WDT) HW driver source file. |
* |
* @note These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true). |
/lib/source/neorv32_xip.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_xip.c |
* @author Stephan Nolting |
* @brief Execute in place module (XIP) HW driver source file. |
* |
* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true). |
/lib/source/neorv32_xirq.c
35,7 → 35,6
|
/**********************************************************************//** |
* @file neorv32_xirq.c |
* @author Stephan Nolting |
* @brief External Interrupt controller HW driver source file. |
**************************************************************************/ |
|
/lib/source/syscalls.c
19,7 → 19,6
|
/**********************************************************************//** |
* @file syscalls.c |
* @author Modified for the NEORV32 RISC-V Processor by Stephan Nolting |
* @brief Newlib system calls |
* |
* @warning UART0 (if available) is used to read/write console data (STDIN, STDOUT, STDERR, ...). |
/README.md
4,24 → 4,24
This is a short description of the main folders. |
|
|
## [bootloader](bootloader) |
## [`bootloader`](bootloader) |
|
Source(s) of the default NEORV32 bootloader. |
A pre-built image is already installed into the rtl design via the `rtl/core/neorv32_bootloader_image.vhd` file. |
|
|
## [common](common) |
## [`common`](common) |
|
NEORV32-specific common files for all bootloader and application programs: |
linker script for executable generation and processor start-up code. |
|
|
## [example](example) |
## [`example`](example) |
|
Several example programs for testing and for getting started. |
|
|
## [image_gen](image_gen) |
## [`image_gen`](image_gen) |
|
This folder contains a simple program that is used to create NEORV32 executables (for upload via bootloader) and VHDL |
memory initialization files (for memory-persistent applications and for the bootloader). |
28,28 → 28,22
This program is automatically compiled using the native GCC when invoking one of the application compilation makefiles. |
|
|
## [isa-test](isa-test) |
## [`lib`](lib) |
|
NEORV32 RISC-V Architecture Test Framework. |
See [sim/README](../sim/README.md). |
|
|
## [lib](lib) |
|
Core libraries (sources and header files) and helper functions for using the processor peripherals and the CPU itself. |
|
|
## [ocd-firmware](ocd-firmware) |
## [`ocd-firmware`](ocd-firmware) |
|
Firmware (debugger "park loop") for the on-chip debugger. This folder is just for documenting the source code. |
Modifying the sources is not recommended as this could break the on-chip debugger. |
|
|
## [openocd](openocd) |
## [`openocd`](openocd) |
|
Configuration file for openOCD to connect to the NEORV32 on-chip debugger via JTAG. |
|
|
## [svd](svd) |
## [`svd`](svd) |
|
Contains a CMSIS-SVD compatible system view description file including _all_ peripherals. |