URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/docs/NEORV32.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/docs/doxygen_makefile_sw
58,7 → 58,7
# entered, it will be relative to the location where doxygen was started. If |
# left blank the current directory will be used. |
|
OUTPUT_DIRECTORY = build |
OUTPUT_DIRECTORY = doxygen_build |
|
# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- |
# directories (in 2 levels) under the output directory of each output format and |
819,11 → 819,11
# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING |
# Note: If this tag is empty the current directory is searched. |
|
INPUT = ../README.md \ |
../sw/lib/source \ |
../sw/lib/include \ |
../sw/bootloader \ |
../sw/example |
INPUT = $(PWD)/../README.md \ |
$(PWD)/../sw/lib/source \ |
$(PWD)/../sw/lib/include \ |
$(PWD)/../sw/bootloader \ |
$(PWD)/../sw/example |
|
# This tag can be used to specify the character encoding of the source files |
# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses |
/trunk/sw/lib/include/neorv32.h
384,7 → 384,7
|
|
/**********************************************************************//** |
* @name IO Device: Serial Peripheral Interface Master (SPI) |
* @name IO Device: Serial Peripheral Interface Controller (SPI) |
**************************************************************************/ |
/**@{*/ |
/** SPI control register (r/w) */ |
420,7 → 420,7
|
|
/**********************************************************************//** |
* @name IO Device: Two-Wire Interface Master (TWI) |
* @name IO Device: Two-Wire Interface Controller (TWI) |
**************************************************************************/ |
/**@{*/ |
/** TWI control register (r/w) */ |
437,7 → 437,7
TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */ |
TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */ |
TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */ |
TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate master ACK for each transmission */ |
TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */ |
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TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */ |
TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */ |
/trunk/sw/lib/include/neorv32_spi.h
1,5 → 1,5
// ################################################################################################# |
// # << NEORV32: neorv32_spi.h - Serial Peripheral Interface Master (SPI) HW Driver >> # |
// # << NEORV32: neorv32_spi.h - Serial Peripheral Interface Controller (SPI) HW Driver >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
36,7 → 36,7
/**********************************************************************//** |
* @file neorv32_spi.h |
* @author Stephan Nolting |
* @brief Serial peripheral interface master (SPI) HW driver header file. |
* @brief Serial peripheral interface controller (SPI) HW driver header file. |
* |
* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_USE = true). |
**************************************************************************/ |
/trunk/sw/lib/include/neorv32_twi.h
1,5 → 1,5
// ################################################################################################# |
// # << NEORV32: neorv32_twi.h - Two-Wire Interface Master (TWI) HW Driver >> # |
// # << NEORV32: neorv32_twi.h - Two-Wire Interface Controller (TWI) HW Driver >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
36,7 → 36,7
/**********************************************************************//** |
* @file neorv32_twi.h |
* @author Stephan Nolting |
* @brief Two-Wire Interface Master (TWI) HW driver header file. |
* @brief Two-Wire Interface Controller (TWI) HW driver header file. |
* |
* @note These functions should only be used if the TWI unit was synthesized (IO_TWI_USE = true). |
**************************************************************************/ |
/trunk/sw/lib/source/neorv32_spi.c
1,5 → 1,5
// ################################################################################################# |
// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Master (SPI) HW Driver >> # |
// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Controller (SPI) HW Driver >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
36,7 → 36,7
/**********************************************************************//** |
* @file neorv32_spi.c |
* @author Stephan Nolting |
* @brief Serial peripheral interface master (SPI) HW driver source file. |
* @brief Serial peripheral interface controller (SPI) HW driver source file. |
* |
* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_USE = true). |
**************************************************************************/ |
/trunk/sw/lib/source/neorv32_twi.c
1,5 → 1,5
// ################################################################################################# |
// # << NEORV32: neorv32_twi.c - Two-Wire Interface Master (TWI) HW Driver >> # |
// # << NEORV32: neorv32_twi.c - Two-Wire Interface Controller (TWI) HW Driver >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
36,7 → 36,7
/**********************************************************************//** |
* @file neorv32_twi.c |
* @author Stephan Nolting |
* @brief Two-Wire Interface Master (TWI) HW driver source file. |
* @brief Two-Wire Interface Controller (TWI) HW driver source file. |
* |
* @note These functions should only be used if the TWI unit was synthesized (IO_TWI_USE = true). |
**************************************************************************/ |
94,7 → 94,7
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/**********************************************************************//** |
* Activate sending ACKs by master (MACK). |
* Activate sending ACKs by controller (MACK). |
**************************************************************************/ |
void neorv32_twi_mack_enable(void) { |
|
103,7 → 103,7
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/**********************************************************************//** |
* Deacivate sending ACKs by master (MACK). |
* Deacivate sending ACKs by controller (MACK). |
**************************************************************************/ |
void neorv32_twi_mack_disable(void) { |
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/trunk/.gitignore
17,7 → 17,7
*.tmp |
|
# no stuff generated by doxygen |
docs/build |
docs/doxygen_build |
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# no compiled ghdl stuff |
*.cf |
/trunk/.travis.yml
1,3 → 1,5
sudo: false |
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dist: bionic |
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services: |
6,12 → 8,22
env: |
- PATH=$PATH:$(pwd)/riscv/bin |
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# Install dependencies |
addons: |
apt: |
packages: |
- doxygen |
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script: |
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# Generate documentary (modify doxygen script for travis ci before) |
- sed -i 's/$(PWD)\/../$(TRAVIS_BUILD_DIR)/g' docs/doxygen_makefile_sw |
- doxygen docs/doxygen_makefile_sw |
|
# Get simulator tools |
- docker pull ghdl/ghdl:buster-gcc-8.3.0 |
|
# Get toolchain & run SW check |
# Get toolchain and run SW check |
- /bin/bash -c "chmod u+x .ci/install.sh && .ci/install.sh" |
- /bin/bash -c "chmod u+x .ci/sw_check.sh && .ci/sw_check.sh" |
|
20,6 → 32,15
docker run -t -v `pwd`:/mnt/data ghdl/ghdl:buster-gcc-8.3.0 |
/bin/bash -c "chmod u+x /mnt/data/.ci/hw_check.sh && /mnt/data/.ci/hw_check.sh" |
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# Generate and deploy documentation |
deploy: |
provider: pages |
skip_cleanup: true |
local_dir: doxygen_build/html |
github_token: $GH_REPO_TOKEN |
on: |
branch: master |
|
notifications: |
email: |
on_success: never |
/trunk/README.md
31,7 → 31,8
|
This project comes with a complete software ecosystem that features core libraries for high-level usage of the |
provided functions and peripherals, application makefiles and example programs. All software source files |
provide a doxygen-based documentary. |
provide a doxygen-based documentary. The deployed doxygen-based software documentation can be found on the |
project's [Github pages](https://stnolting.github.io/neorv32/files.html). |
|
The project is intended to work "out of the box". Just synthesize the test setup from this project, upload |
it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) |
56,11 → 57,11
|
The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance). |
|
| Project | Status | |
|:--------------------------------------------------------------------------------|:-------| |
| NEORV32 processor | [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) | |
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [![Build Test](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [![Build Status](https://travis-ci.com/stnolting/neorv32_riscv_compliance.svg?branch=master)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
| Project | Status | Misc | |
|:--------------------------------------------------------------------------------|:-------|:---------| |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [![Test](https://img.shields.io/travis/stnolting/neorv32/master.svg?label=HW-test)](https://travis-ci.com/stnolting/neorv32) | [![sw doc](https://img.shields.io/badge/SW%20documentation-gh--pages-blue)](https://stnolting.github.io/neorv32/files.html) | |
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [![Test](https://img.shields.io/travis/stnolting/riscv_gcc_prebuilt/master.svg?label=compliance)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [![Test](https://img.shields.io/travis/stnolting/neorv32_riscv_compliance/master.svg?label=test)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
|
|
### Limitations to be fixed |
89,7 → 90,7
- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions |
- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available [@Github pages](https://stnolting.github.io/neorv32/files.html) |
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc. |
- Fully synchronous design, no latches, no gated clocks |
- Small hardware footprint and high operating frequency |