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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32
    from Rev 27 to Rev 28
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Rev 27 → Rev 28

/trunk/docs/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/rtl/core/neorv32_cpu_bus.vhd
319,20 → 319,19
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error
i_arbiter.rd_req <= '0';
end if;
elsif (i_bus_ack_i = '1') then -- wait for normal termination
--if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
-- if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error
-- i_arbiter.rd_req <= '0';
-- end if;
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
i_arbiter.rd_req <= '0';
end if;
end if;
 
-- cancel bus access --
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
end if;
end process ifetch_arbiter;
 
-- cancel bus access --
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
 
-- wait for bus transaction to finish --
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
374,22 → 373,21
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error
d_arbiter.wr_req <= '0';
d_arbiter.rd_req <= '0';
end if;
elsif (d_bus_ack_i = '1') then -- wait for normal termination
--if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
-- if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error
-- d_arbiter.wr_req <= '0';
-- d_arbiter.rd_req <= '0';
-- end if;
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
d_arbiter.wr_req <= '0';
d_arbiter.rd_req <= '0';
end if;
end if;
 
-- cancel bus access --
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
end if;
end process data_access_arbiter;
 
-- cancel bus access --
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
 
-- wait for bus transaction to finish --
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
/trunk/rtl/core/neorv32_cpu_control.vhd
319,6 → 319,7
fetch_engine.i_buf_state_nxt <= (others => '0');
ipb.clear <= '1'; -- clear instruction prefetch buffer
fetch_engine.state_nxt <= IFETCH_0;
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
 
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
-- ------------------------------------------------------------
331,7 → 332,6
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
fetch_engine.state_nxt <= IFETCH_2;
else
342,6 → 342,7
 
when IFETCH_2 => -- construct instruction word and issue
-- ------------------------------------------------------------
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
if (fetch_engine.pc(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
 
/trunk/rtl/core/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040309"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040400"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
 
-- Architecture Configuration -------------------------------------------------------------
/trunk/sim/neorv32_tb.vhd
285,7 → 285,7
for i in 1 to wb_mem_latency_c-1 loop
wb_mem.rdata(i) <= wb_mem.rdata(i-1);
wb_mem.rb_en(i) <= wb_mem.rb_en(i-1);
wb_mem.ack(i) <= wb_mem.ack(i-1);
wb_mem.ack(i) <= wb_mem.ack(i-1) and wb_cpu.cyc;
end loop;
end if;
end if;
/trunk/sw/example/cpu_test/main.c
40,6 → 40,7
**************************************************************************/
 
#include <neorv32.h>
#include <string.h>
 
 
/**********************************************************************//**
52,10 → 53,14
#define DETAILED_EXCEPTION_DEBUG 0
//** Set 1 to run memory tests */
#define PROBING_MEM_TEST 0
//** Set 1 to run external memory test */
#define EXT_MEM_TEST 1
//** Reachable unaligned address */
#define ADDR_UNALIGNED 0x00000002
//** Unreachable aligned address */
#define ADDR_UNREACHABLE 0xFFFFFF00
//* external memory base address */
#define EXT_MEM_BASE 0xF0000000
/**@}*/
 
 
198,7 → 203,7
// Instruction memory test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("IMEM_TEST: ");
neorv32_uart_printf("IMEM TEST: ");
#if (PROBING_MEM_TEST == 1)
cnt_test++;
 
214,9 → 219,9
dmem_probe_cnt++;
}
neorv32_uart_printf("%u bytes (should be %u bytes) ", dmem_probe_cnt, SYSINFO_ISPACE_SIZE);
neorv32_uart_printf("%u bytes (should be %u bytes) ", dmem_probe_cnt, SYSINFO_IMEM_SIZE);
neorv32_uart_printf("@ 0x%x ", SYSINFO_ISPACE_BASE);
if (dmem_probe_cnt == SYSINFO_ISPACE_SIZE) {
if (dmem_probe_cnt == SYSINFO_IMEM_SIZE) {
test_ok();
}
else {
231,7 → 236,7
// Data memory test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("DMEM_TEST: ");
neorv32_uart_printf("DMEM TEST: ");
#if (PROBING_MEM_TEST == 1)
cnt_test++;
 
247,9 → 252,9
imem_probe_cnt++;
}
neorv32_uart_printf("%u bytes (should be %u bytes) ", imem_probe_cnt, SYSINFO_DSPACE_SIZE);
neorv32_uart_printf("%u bytes (should be %u bytes) ", imem_probe_cnt, SYSINFO_DMEM_SIZE);
neorv32_uart_printf("@ 0x%x ", SYSINFO_DSPACE_BASE);
if (imem_probe_cnt == SYSINFO_DSPACE_SIZE) {
if (imem_probe_cnt == SYSINFO_DMEM_SIZE) {
test_ok();
}
else {
261,6 → 266,49
 
 
// ----------------------------------------------------------
// External memory interface test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("EXT_MEM TEST: ");
#if (EXT_MEM_TEST == 1)
cnt_test++;
 
// create test program in RAM
static const uint32_t dummy_ext_program[2] __attribute__((aligned(8))) = {
0x3407D073, // csrwi mscratch, 15
0x00008067 // ret (32-bit)
};
 
// copy to external memory
if (memcpy((void*)EXT_MEM_BASE, (void*)&dummy_ext_program, (size_t)sizeof(dummy_ext_program)) == NULL) {
test_fail();
}
else {
 
// execute program
tmp_a = (uint32_t)EXT_MEM_BASE; // call the dummy sub program
asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a));
#if (DETAILED_EXCEPTION_DEBUG==0)
if (exception_handler_answer == 0xFFFFFFFF) { // make sure there was no exception
if (neorv32_cpu_csr_read(CSR_MSCRATCH) == 15) { // make sure the program was executed in the right way
test_ok();
}
else {
test_fail();
}
}
else {
test_fail();
}
#endif
}
#else
neorv32_uart_printf("skipped (disabled)\n");
#endif
 
 
// ----------------------------------------------------------
// Test time[h] (must be == MTIME)
// ----------------------------------------------------------
neorv32_uart_printf("TIME[H]: ");
/trunk/README.md
312,7 → 312,7
**Configuration**
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
Compiler: RISCV32-GCC 10.1.0
Compiler: RISCV32-GCC 10.1.0 (rv32i)
Peripherals: UART for printing the results
~~~
 

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