OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/trunk/docs/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/rtl/core/neorv32_bootloader_image.vhd
51,11 → 51,11
00000040 => x"01612823",
00000041 => x"01712623",
00000042 => x"01812423",
00000043 => x"4fd000ef",
00000043 => x"4ed000ef",
00000044 => x"4c1000ef",
00000045 => x"429000ef",
00000046 => x"299000ef",
00000047 => x"4d9000ef",
00000047 => x"4c9000ef",
00000048 => x"281000ef",
00000049 => x"fc102473",
00000050 => x"026267b7",
84,56 → 84,56
00000073 => x"30579073",
00000074 => x"08000793",
00000075 => x"30479073",
00000076 => x"455000ef",
00000076 => x"30046073",
00000077 => x"00100513",
00000078 => x"431000ef",
00000079 => x"00000793",
00000080 => x"34079073",
00000081 => x"ffff1537",
00000082 => x"eec50513",
00000082 => x"edc50513",
00000083 => x"2ed000ef",
00000084 => x"3d0000ef",
00000085 => x"ffff1537",
00000086 => x"f2450513",
00000086 => x"f1450513",
00000087 => x"2dd000ef",
00000088 => x"fc102573",
00000089 => x"254000ef",
00000090 => x"ffff1537",
00000091 => x"f2c50513",
00000091 => x"f1c50513",
00000092 => x"2c9000ef",
00000093 => x"f1402573",
00000094 => x"240000ef",
00000095 => x"ffff1537",
00000096 => x"f3850513",
00000096 => x"f2850513",
00000097 => x"2b5000ef",
00000098 => x"30102573",
00000099 => x"22c000ef",
00000100 => x"ffff1537",
00000101 => x"f4050513",
00000101 => x"f3050513",
00000102 => x"2a1000ef",
00000103 => x"fc002573",
00000104 => x"218000ef",
00000105 => x"ffff1537",
00000106 => x"f4850513",
00000106 => x"f3850513",
00000107 => x"28d000ef",
00000108 => x"fc602573",
00000109 => x"ffff14b7",
00000110 => x"200000ef",
00000111 => x"f5048513",
00000111 => x"f4048513",
00000112 => x"279000ef",
00000113 => x"fc402573",
00000114 => x"1f0000ef",
00000115 => x"ffff1537",
00000116 => x"f5c50513",
00000116 => x"f4c50513",
00000117 => x"265000ef",
00000118 => x"fc702573",
00000119 => x"1dc000ef",
00000120 => x"f5048513",
00000120 => x"f4048513",
00000121 => x"255000ef",
00000122 => x"fc502573",
00000123 => x"1cc000ef",
00000124 => x"ffff1537",
00000125 => x"f6450513",
00000125 => x"f5450513",
00000126 => x"241000ef",
00000127 => x"00341413",
00000128 => x"00000493",
141,7 → 141,7
00000130 => x"fa402783",
00000131 => x"0607d063",
00000132 => x"ffff1537",
00000133 => x"f9450513",
00000133 => x"f8050513",
00000134 => x"221000ef",
00000135 => x"ffff1937",
00000136 => x"0f4000ef",
152,12 → 152,12
00000141 => x"07300b93",
00000142 => x"ffff14b7",
00000143 => x"ffff1c37",
00000144 => x"fa090513",
00000144 => x"f8c90513",
00000145 => x"1f5000ef",
00000146 => x"1e1000ef",
00000147 => x"00050413",
00000148 => x"1c9000ef",
00000149 => x"f9098513",
00000149 => x"f7c98513",
00000150 => x"1e1000ef",
00000151 => x"09440263",
00000152 => x"03541863",
168,7 → 168,7
00000157 => x"f8856ae3",
00000158 => x"00100513",
00000159 => x"508000ef",
00000160 => x"f9090513",
00000160 => x"f7c90513",
00000161 => x"1b5000ef",
00000162 => x"098000ef",
00000163 => x"f7dff06f",
187,9 → 187,9
00000176 => x"060000ef",
00000177 => x"f7dff06f",
00000178 => x"03f00793",
00000179 => x"fa8c0513",
00000179 => x"f94c0513",
00000180 => x"00f40463",
00000181 => x"fbc48513",
00000181 => x"fa848513",
00000182 => x"161000ef",
00000183 => x"f65ff06f",
00000184 => x"02c12083",
206,20 → 206,20
00000195 => x"03010113",
00000196 => x"00008067",
00000197 => x"ffff1537",
00000198 => x"dbc50513",
00000198 => x"dac50513",
00000199 => x"11d0006f",
00000200 => x"340027f3",
00000201 => x"00079863",
00000202 => x"ffff1537",
00000203 => x"e2050513",
00000203 => x"e1050513",
00000204 => x"1090006f",
00000205 => x"ff010113",
00000206 => x"00112623",
00000207 => x"251000ef",
00000207 => x"30047073",
00000208 => x"00000793",
00000209 => x"30479073",
00000210 => x"ffff1537",
00000211 => x"e3c50513",
00000211 => x"e2c50513",
00000212 => x"0e9000ef",
00000213 => x"fa002783",
00000214 => x"fe07cee3",
230,7 → 230,7
00000219 => x"00812423",
00000220 => x"00050413",
00000221 => x"ffff1537",
00000222 => x"e4c50513",
00000222 => x"e3c50513",
00000223 => x"00112623",
00000224 => x"0b9000ef",
00000225 => x"00500793",
238,12 → 238,12
00000227 => x"03040513",
00000228 => x"0ff57513",
00000229 => x"085000ef",
00000230 => x"1f5000ef",
00000230 => x"30047073",
00000231 => x"00100513",
00000232 => x"1c9000ef",
00000233 => x"0000006f",
00000234 => x"ffff1537",
00000235 => x"e5450513",
00000235 => x"e4450513",
00000236 => x"089000ef",
00000237 => x"fe5ff06f",
00000238 => x"fe010113",
251,7 → 251,7
00000240 => x"00050913",
00000241 => x"ffff1537",
00000242 => x"00912a23",
00000243 => x"e5c50513",
00000243 => x"e4c50513",
00000244 => x"ffff14b7",
00000245 => x"00812c23",
00000246 => x"01312623",
258,7 → 258,7
00000247 => x"00112e23",
00000248 => x"01c00413",
00000249 => x"055000ef",
00000250 => x"fc848493",
00000250 => x"fb448493",
00000251 => x"ffc00993",
00000252 => x"008957b3",
00000253 => x"00f7f793",
297,12 → 297,12
00000286 => x"00778793",
00000287 => x"02f40a63",
00000288 => x"ffff1537",
00000289 => x"e6050513",
00000289 => x"e5050513",
00000290 => x"7b0000ef",
00000291 => x"00040513",
00000292 => x"f29ff0ef",
00000293 => x"ffff1537",
00000294 => x"e7050513",
00000294 => x"e6050513",
00000295 => x"79c000ef",
00000296 => x"34102573",
00000297 => x"f15ff0ef",
507,7 → 507,7
00000496 => x"00050493",
00000497 => x"02051863",
00000498 => x"ffff1537",
00000499 => x"e7850513",
00000499 => x"e6850513",
00000500 => x"468000ef",
00000501 => x"000405b7",
00000502 => x"00048513",
518,7 → 518,7
00000507 => x"00000513",
00000508 => x"fcdff06f",
00000509 => x"ffff1537",
00000510 => x"e9850513",
00000510 => x"e8850513",
00000511 => x"43c000ef",
00000512 => x"e1dff0ef",
00000513 => x"fc0518e3",
546,7 → 546,7
00000535 => x"00200513",
00000536 => x"f4041ee3",
00000537 => x"ffff1537",
00000538 => x"ea450513",
00000538 => x"e9450513",
00000539 => x"3cc000ef",
00000540 => x"34091073",
00000541 => x"02c12083",
645,7 → 645,7
00000634 => x"34002473",
00000635 => x"02041863",
00000636 => x"ffff1537",
00000637 => x"e2050513",
00000637 => x"e1050513",
00000638 => x"01812403",
00000639 => x"01c12083",
00000640 => x"01412483",
656,17 → 656,17
00000645 => x"02010113",
00000646 => x"2200006f",
00000647 => x"ffff1537",
00000648 => x"ea850513",
00000648 => x"e9850513",
00000649 => x"214000ef",
00000650 => x"00040513",
00000651 => x"98dff0ef",
00000652 => x"ffff1537",
00000653 => x"eb450513",
00000653 => x"ea450513",
00000654 => x"200000ef",
00000655 => x"00040537",
00000656 => x"979ff0ef",
00000657 => x"ffff1537",
00000658 => x"ed050513",
00000658 => x"ec050513",
00000659 => x"1ec000ef",
00000660 => x"1d8000ef",
00000661 => x"00050493",
678,7 → 678,7
00000667 => x"00300513",
00000668 => x"8f9ff0ef",
00000669 => x"ffff1537",
00000670 => x"edc50513",
00000670 => x"ecc50513",
00000671 => x"01045493",
00000672 => x"1b8000ef",
00000673 => x"00148493",
708,7 → 708,7
00000697 => x"412005b3",
00000698 => x"e39ff0ef",
00000699 => x"ffff1537",
00000700 => x"ea450513",
00000700 => x"e9450513",
00000701 => x"f05ff06f",
00000702 => x"00090513",
00000703 => x"e7dff0ef",
873,155 → 873,150
00000862 => x"ffe7f793",
00000863 => x"00f72023",
00000864 => x"00008067",
00000865 => x"30046073",
00000866 => x"00008067",
00000867 => x"30047073",
00000868 => x"00008067",
00000869 => x"fb000713",
00000870 => x"00072783",
00000871 => x"ff77f793",
00000872 => x"00f72023",
00000873 => x"00008067",
00000874 => x"f8800713",
00000875 => x"00072783",
00000876 => x"fef7f793",
00000877 => x"00f72023",
00000878 => x"00008067",
00000879 => x"69617641",
00000880 => x"6c62616c",
00000881 => x"4d432065",
00000882 => x"0a3a7344",
00000883 => x"203a6820",
00000884 => x"706c6548",
00000885 => x"3a72200a",
00000886 => x"73655220",
00000887 => x"74726174",
00000888 => x"3a75200a",
00000889 => x"6c705520",
00000890 => x"0a64616f",
00000891 => x"203a7320",
00000892 => x"726f7453",
00000893 => x"6f742065",
00000894 => x"616c6620",
00000895 => x"200a6873",
00000896 => x"4c203a6c",
00000897 => x"2064616f",
00000898 => x"6d6f7266",
00000899 => x"616c6620",
00000900 => x"200a6873",
00000901 => x"45203a65",
00000902 => x"75636578",
00000903 => x"00006574",
00000904 => x"65206f4e",
00000905 => x"75636578",
00000906 => x"6c626174",
00000907 => x"76612065",
00000908 => x"616c6961",
00000909 => x"2e656c62",
00000865 => x"fb000713",
00000866 => x"00072783",
00000867 => x"ff77f793",
00000868 => x"00f72023",
00000869 => x"00008067",
00000870 => x"f8800713",
00000871 => x"00072783",
00000872 => x"fef7f793",
00000873 => x"00f72023",
00000874 => x"00008067",
00000875 => x"69617641",
00000876 => x"6c62616c",
00000877 => x"4d432065",
00000878 => x"0a3a7344",
00000879 => x"203a6820",
00000880 => x"706c6548",
00000881 => x"3a72200a",
00000882 => x"73655220",
00000883 => x"74726174",
00000884 => x"3a75200a",
00000885 => x"6c705520",
00000886 => x"0a64616f",
00000887 => x"203a7320",
00000888 => x"726f7453",
00000889 => x"6f742065",
00000890 => x"616c6620",
00000891 => x"200a6873",
00000892 => x"4c203a6c",
00000893 => x"2064616f",
00000894 => x"6d6f7266",
00000895 => x"616c6620",
00000896 => x"200a6873",
00000897 => x"45203a65",
00000898 => x"75636578",
00000899 => x"00006574",
00000900 => x"65206f4e",
00000901 => x"75636578",
00000902 => x"6c626174",
00000903 => x"76612065",
00000904 => x"616c6961",
00000905 => x"2e656c62",
00000906 => x"00000000",
00000907 => x"746f6f42",
00000908 => x"2e676e69",
00000909 => x"0a0a2e2e",
00000910 => x"00000000",
00000911 => x"746f6f42",
00000912 => x"2e676e69",
00000913 => x"0a0a2e2e",
00000914 => x"00000000",
00000915 => x"52450a07",
00000916 => x"00005f52",
00000917 => x"6e6b6e75",
00000918 => x"006e776f",
00000919 => x"00007830",
00000920 => x"58450a0a",
00000921 => x"54504543",
00000922 => x"3a4e4f49",
00000923 => x"00000020",
00000924 => x"30204020",
00000925 => x"00000078",
00000926 => x"69617741",
00000927 => x"676e6974",
00000928 => x"6f656e20",
00000929 => x"32337672",
00000930 => x"6578655f",
00000931 => x"6e69622e",
00000932 => x"202e2e2e",
00000933 => x"00000000",
00000934 => x"64616f4c",
00000935 => x"2e676e69",
00000936 => x"00202e2e",
00000937 => x"00004b4f",
00000938 => x"74697257",
00000939 => x"78302065",
00000940 => x"00000000",
00000941 => x"74796220",
00000942 => x"74207365",
00000943 => x"5053206f",
00000944 => x"6c662049",
00000945 => x"20687361",
00000946 => x"78302040",
00000947 => x"00000000",
00000948 => x"7928203f",
00000949 => x"20296e2f",
00000950 => x"00000000",
00000951 => x"616c460a",
00000952 => x"6e696873",
00000953 => x"2e2e2e67",
00000954 => x"00000020",
00000955 => x"0a0a0a0a",
00000956 => x"4e203c3c",
00000957 => x"56524f45",
00000958 => x"42203233",
00000959 => x"6c746f6f",
00000960 => x"6564616f",
00000961 => x"3e3e2072",
00000962 => x"4c420a0a",
00000963 => x"203a5644",
00000964 => x"206c754a",
00000965 => x"32203520",
00000966 => x"0a303230",
00000967 => x"3a565748",
00000968 => x"00002020",
00000969 => x"4b4c430a",
00000970 => x"0020203a",
00000971 => x"0a7a4820",
00000972 => x"4449484d",
00000973 => x"0000203a",
00000974 => x"53494d0a",
00000975 => x"00203a41",
00000976 => x"4e4f430a",
00000977 => x"00203a46",
00000978 => x"454d490a",
00000979 => x"00203a4d",
00000980 => x"74796220",
00000981 => x"40207365",
00000982 => x"00000020",
00000983 => x"454d440a",
00000984 => x"00203a4d",
00000985 => x"75410a0a",
00000986 => x"6f626f74",
00000987 => x"6920746f",
00000988 => x"3828206e",
00000989 => x"202e7329",
00000990 => x"73657250",
00000991 => x"656b2073",
00000992 => x"6f742079",
00000993 => x"6f626120",
00000994 => x"0a2e7472",
00000995 => x"00000000",
00000996 => x"0000000a",
00000997 => x"726f6241",
00000998 => x"2e646574",
00000999 => x"00000a0a",
00001000 => x"444d430a",
00001001 => x"00203e3a",
00001002 => x"53207962",
00001003 => x"68706574",
00001004 => x"4e206e61",
00001005 => x"69746c6f",
00001006 => x"0000676e",
00001007 => x"61766e49",
00001008 => x"2064696c",
00001009 => x"00444d43",
00001010 => x"33323130",
00001011 => x"37363534",
00001012 => x"42413938",
00001013 => x"46454443",
00000911 => x"52450a07",
00000912 => x"00005f52",
00000913 => x"6e6b6e75",
00000914 => x"006e776f",
00000915 => x"00007830",
00000916 => x"58450a0a",
00000917 => x"54504543",
00000918 => x"3a4e4f49",
00000919 => x"00000020",
00000920 => x"30204020",
00000921 => x"00000078",
00000922 => x"69617741",
00000923 => x"676e6974",
00000924 => x"6f656e20",
00000925 => x"32337672",
00000926 => x"6578655f",
00000927 => x"6e69622e",
00000928 => x"202e2e2e",
00000929 => x"00000000",
00000930 => x"64616f4c",
00000931 => x"2e676e69",
00000932 => x"00202e2e",
00000933 => x"00004b4f",
00000934 => x"74697257",
00000935 => x"78302065",
00000936 => x"00000000",
00000937 => x"74796220",
00000938 => x"74207365",
00000939 => x"5053206f",
00000940 => x"6c662049",
00000941 => x"20687361",
00000942 => x"78302040",
00000943 => x"00000000",
00000944 => x"7928203f",
00000945 => x"20296e2f",
00000946 => x"00000000",
00000947 => x"616c460a",
00000948 => x"6e696873",
00000949 => x"2e2e2e67",
00000950 => x"00000020",
00000951 => x"0a0a0a0a",
00000952 => x"4e203c3c",
00000953 => x"56524f45",
00000954 => x"42203233",
00000955 => x"6c746f6f",
00000956 => x"6564616f",
00000957 => x"3e3e2072",
00000958 => x"4c420a0a",
00000959 => x"203a5644",
00000960 => x"206c754a",
00000961 => x"32203720",
00000962 => x"0a303230",
00000963 => x"3a565748",
00000964 => x"00002020",
00000965 => x"4b4c430a",
00000966 => x"0020203a",
00000967 => x"0a7a4820",
00000968 => x"4449484d",
00000969 => x"0000203a",
00000970 => x"53494d0a",
00000971 => x"00203a41",
00000972 => x"4e4f430a",
00000973 => x"00203a46",
00000974 => x"454d490a",
00000975 => x"00203a4d",
00000976 => x"74796220",
00000977 => x"40207365",
00000978 => x"00000020",
00000979 => x"454d440a",
00000980 => x"00203a4d",
00000981 => x"75410a0a",
00000982 => x"6f626f74",
00000983 => x"6920746f",
00000984 => x"7338206e",
00000985 => x"7250202e",
00000986 => x"20737365",
00000987 => x"2079656b",
00000988 => x"61206f74",
00000989 => x"74726f62",
00000990 => x"00000a2e",
00000991 => x"0000000a",
00000992 => x"726f6241",
00000993 => x"2e646574",
00000994 => x"00000a0a",
00000995 => x"444d430a",
00000996 => x"00203e3a",
00000997 => x"53207962",
00000998 => x"68706574",
00000999 => x"4e206e61",
00001000 => x"69746c6f",
00001001 => x"0000676e",
00001002 => x"61766e49",
00001003 => x"2064696c",
00001004 => x"00444d43",
00001005 => x"33323130",
00001006 => x"37363534",
00001007 => x"42413938",
00001008 => x"46454443",
others => x"00000000"
);
 
/trunk/rtl/core/neorv32_cpu_alu.vhd
141,7 → 141,7
cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a less
cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
 
-- equal (x = y) --
170,7 → 170,7
shift_cmd_ff <= shift_cmd;
if (shift_start = '1') then -- trigger new shift
shift_sreg <= opa; -- shift operand
shift_cnt <= opb(4 downto 0); -- shift amount
shift_cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
elsif (shift_run = '1') then -- running shift
shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1);
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
187,7 → 187,7
shift_start <= '1' when (shift_cmd = '1') and (shift_cmd_ff = '0') else '0';
 
-- shift operation running? --
shift_run <= '1' when (shift_cnt /= "00000") or (shift_start = '1') else '0';
shift_run <= '1' when (or_all_f(shift_cnt) = '1') or (shift_start = '1') else '0';
 
 
-- Coprocessor Interface ------------------------------------------------------------------
200,7 → 200,7
cp_rb_ff0 <= '0';
cp_rb_ff1 <= '0';
elsif rising_edge(clk_i) then
if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then
if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then -- FIXME add second cp (floating point stuff?)
cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
cp_rb_ff0 <= '0';
cp_rb_ff1 <= cp_rb_ff0;
231,12 → 231,12
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg)
begin
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modification only)
when alu_cmd_sub_c => alu_res <= sub_res;
when alu_cmd_add_c => alu_res <= add_res;
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modifications only)
when alu_cmd_xor_c => alu_res <= opa xor opb;
when alu_cmd_or_c => alu_res <= opa or opb;
when alu_cmd_and_c => alu_res <= opa and opb;
when alu_cmd_sub_c => alu_res <= sub_res;
when alu_cmd_add_c => alu_res <= add_res;
when alu_cmd_shift_c => alu_res <= shift_sreg;
when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
when others => alu_res <= (others => '0'); -- undefined
/trunk/rtl/core/neorv32_cpu_control.vhd
892,7 → 892,7
-- RF write back --
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output register
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
execute_engine.state_nxt <= DISPATCH;
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
 
when ALU_WAIT => -- wait for multi-cycle ALU operation to finish
-- ------------------------------------------------------------
1199,6 → 1199,9
trap_ctrl.cause_nxt <= (others => '0');
trap_ctrl.irq_ack_nxt <= (others => '0');
 
-- the following traps are caused by asynchronous exceptions (-> interrupts)
-- here we do need an acknowledge mask since several sources can trigger at once
 
-- interrupt: 1.11 machine external interrupt --
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
1219,7 → 1222,8
 
 
-- the following traps are caused by synchronous exceptions
-- here we do not need an acknowledge mask since only one exception can trigger at the same time
-- here we do not need an acknowledge mask since only one exception (the one
-- with highest priority) can trigger at once
 
-- trap/fault: 0.0 instruction address misaligned --
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
1321,8 → 1325,8
csr.mstatus_mpie <= csr_wdata_i(07);
end if;
if (execute_engine.i_reg(23 downto 20) = x"1") then -- R/W: misa - machine instruction set extensions
csr.misa_c_en <= csr_wdata_i(02); -- C extension enable/disable
csr.misa_m_en <= csr_wdata_i(12); -- M extension enable/disable
csr.misa_c_en <= csr_wdata_i(02); -- C extension enable/disable during runtime
csr.misa_m_en <= csr_wdata_i(12); -- M extension enable/disable during runtime
end if;
if (execute_engine.i_reg(23 downto 20) = x"4") then -- R/W: mie - machine interrupt-enable register
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
1348,21 → 1352,20
end if;
 
else -- automatic update by hardware
 
-- machine exception PC & exception value register --
if (trap_ctrl.env_start_ack = '1') then -- trap handler started?
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only (mtval not defined for interrupts)
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
csr.mtval <= (others => '0');
else -- for EXCEPTIONs
else -- for EXCEPTIONS (according to their priority)
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
if ((trap_ctrl.exc_src(exception_iaccess_c) or trap_ctrl.exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0';
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
elsif (trap_ctrl.exc_src(exception_iillegal_c) = '1') then -- illegal instruction
csr.mtval <= execute_engine.i_reg;
else -- everything else
--elsif ((trap_ctrl.exc_src(exception_lalign_c) or trap_ctrl.exc_src(exception_salign_c) or
-- trap_ctrl.exc_src(exception_laccess_c) or trap_ctrl.exc_src(exception_saccess_c)) = '1') then -- load/store misaligned / access error
csr.mtval <= mar_i;
csr.mtval <= execute_engine.i_reg; -- the faulting instruction itself
else -- load/store msialignments/access errors
csr.mtval <= mar_i; -- faulting data access address
end if;
end if;
end if;
1370,12 → 1373,13
-- context switch in mstatus --
if (trap_ctrl.env_start_ack = '1') then -- actually entering trap
csr.mstatus_mie <= '0';
if (csr.mstatus_mpie = '0') then -- FIXME: prevent loosing the prev MIE state after several traps
if (csr.mstatus_mpie = '0') then -- prevent loosing the prev MIE state in nested traps
csr.mstatus_mpie <= csr.mstatus_mie;
end if;
elsif (trap_ctrl.env_end = '1') then -- return from exception
csr.mstatus_mie <= csr.mstatus_mpie;
end if;
 
end if;
end if;
end if;
/trunk/rtl/core/neorv32_cpu_regfile.vhd
94,7 → 94,7
-- -------------------------------------------------------------------------------------------
rf_access: process(clk_i)
begin
if rising_edge(clk_i) then
if rising_edge(clk_i) then -- sync read and write
if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
-- check if reading from r0 --
rs1_clear <= '0';
/trunk/rtl/top_templates/neorv32_test_setup.vhd
70,7 → 70,7
generic map (
-- General --
CLOCK_FREQUENCY => 100000000, -- clock frequency of clk_i in Hz
HART_ID => x"00000000", -- custom hardware thread ID
HART_ID => x"00000000", -- hardware thread ID
BOOTLOADER_USE => true, -- implement processor-internal bootloader?
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
-- RISC-V CPU Extensions --
/trunk/sw/bootloader/bootloader.c
63,7 → 63,7
/** UART BAUD rate */
#define BAUD_RATE (19200)
/** Time until the auto-boot sequence starts (in seconds) */
#define AUTOBOOT_TIMEOUT (8)
#define AUTOBOOT_TIMEOUT 8
/** Bootloader status LED at GPIO output port (0..15) */
#define STATUS_LED (0)
/** SPI flash boot image base address */
/trunk/sw/lib/include/neorv32_cpu.h
43,14 → 43,9
#define neorv32_cpu_h
 
// prototypes
void neorv32_cpu_sleep(void);
void neorv32_cpu_eint(void);
void neorv32_cpu_dint(void);
int neorv32_cpu_switch_extension(int sel, int state);
int neorv32_cpu_irq_enable(uint8_t irq_sel);
int neorv32_cpu_irq_disable(uint8_t irq_sel);
void neorv32_cpu_sw_irq(void);
void neorv32_cpu_breakpoint(void);
void neorv32_cpu_env_call(void);
void neorv32_cpu_delay_ms(uint32_t time_ms);
 
 
83,4 → 78,74
asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
}
 
 
/**********************************************************************//**
* Put CPU into "sleep" mode.
*
* @note This function executes the WFI insstruction.
* The WFI (wait for interrupt) instruction will make the CPU stall until
* an interupt request is detected. Interrupts have to be globally enabled
* and at least one external source must be enabled (e.g., the CLIC or the machine
* timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
* this will permanently stall the CPU.
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
 
asm volatile ("wfi");
}
 
 
/**********************************************************************//**
* Enable global CPU interrupts (via MIE flag in mstatus CSR).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
 
asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
}
 
 
/**********************************************************************//**
* Disable global CPU interrupts (via MIE flag in mstatus CSR).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
 
asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
}
 
 
/**********************************************************************//**
* Trigger machine software interrupt.
*
* @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and
* global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.
* The MSI becomes active after 3 clock cycles.
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_sw_irq(void) {
 
asm volatile ("csrrsi zero, mip, %0" : : "i" (1 << CPU_MIP_MSIP));
 
// the MSI becomes active 3 clock cycles afters issueing
asm volatile ("nop"); // these nops are not required, they just make sure the MSI becomes active
asm volatile ("nop"); // before the "real" next operation is executed
}
 
 
/**********************************************************************//**
* Trigger breakpoint exception (via EBREAK instruction).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) {
 
asm volatile ("ebreak");
}
 
 
/**********************************************************************//**
* Trigger "environment call" exception (via ECALL instruction).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_env_call(void) {
 
asm volatile ("ecall");
}
 
 
#endif // neorv32_cpu_h
/trunk/sw/lib/source/neorv32_cpu.c
44,38 → 44,50
 
 
/**********************************************************************//**
* Put CPU into "sleep" mode.
* Enable/disable CPU extension during runtime via the 'misa' CSR.
*
* @note This function executes the WFI insstruction.
* The WFI (wait for interrupt) instruction will make the CPU stall until
* an interupt request is detected. Interrupts have to be globally enabled
* and at least one external source must be enabled (e.g., the CLIC or the machine
* timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
* this will permanently stall the CPU.
* @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions.
*
* @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum.
* @param[in] state Set 1 to enable the selected extension, set 0 to disable it;
* return 0 if success, 1 if error (invalid sel or extension cannot be enabled).
**************************************************************************/
void neorv32_cpu_sleep(void) {
int neorv32_cpu_switch_extension(int sel, int state) {
 
asm volatile ("wfi");
}
// get current misa setting
uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA);
uint32_t misa_prev = misa_curr;
 
// abort if misa.z is cleared
if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) {
return 1;
}
 
/**********************************************************************//**
* Enable global CPU interrupts (via MIE flag in mstatus CSR).
**************************************************************************/
void neorv32_cpu_eint(void) {
// out of range?
if (sel > 25) {
return 1;
}
 
const int mask = 1 << CPU_MSTATUS_MIE;
asm volatile ("csrrsi zero, mstatus, %0" : : "i" (mask));
}
// enable/disable selected extension
if (state & 1) {
misa_curr |= (1 << sel);
}
else {
misa_curr &= ~(1 << sel);
}
 
// try updating misa
neorv32_cpu_csr_write(CSR_MISA, misa_curr);
asm volatile("fence.i"); // required to flush prefetch buffers
asm volatile("nop");
 
/**********************************************************************//**
* Disable global CPU interrupts (via MIE flag in mstatus CSR).
**************************************************************************/
void neorv32_cpu_dint(void) {
 
const int mask = 1 << CPU_MSTATUS_MIE;
asm volatile ("csrrci zero, mstatus, %0" : : "i" (mask));
// dit it work?
if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) {
return 1; // nope
}
else {
return 0; // fine
}
}
 
 
118,37 → 130,6
 
 
/**********************************************************************//**
* Trigger machine software interrupt.
*
* @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and
* global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.
**************************************************************************/
void neorv32_cpu_sw_irq(void) {
 
register uint32_t mask = (uint32_t)(1 << CPU_MIP_MSIP);
asm volatile ("csrrs zero, mip, %0" : : "r" (mask));
}
 
 
/**********************************************************************//**
* Trigger breakpoint exception (via EBREAK instruction).
**************************************************************************/
void neorv32_cpu_breakpoint(void) {
 
asm volatile ("ebreak");
}
 
 
/**********************************************************************//**
* Trigger "environment call" exception (via ECALL instruction).
**************************************************************************/
void neorv32_cpu_env_call(void) {
 
asm volatile ("ecall");
}
 
 
/**********************************************************************//**
* Simple delay function (not very precise) using busy wait.
*
* @param[in] time_ms Time in ms to wait.
/trunk/README.md
4,12 → 4,7
[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
 
[![issues](https://img.shields.io/github/issues/stnolting/neorv32)](https://github.com/stnolting/neorv32/issues)
[![pull requests](https://img.shields.io/github/issues-pr/stnolting/neorv32)](https://github.com/stnolting/neorv32/pulls)
[![last commit](https://img.shields.io/github/last-commit/stnolting/neorv32)](https://github.com/stnolting/neorv32/commits/master)
 
 
 
## Table of Content
 
* [Introduction](#Introduction)
18,7 → 13,7
* [Performance](#Performance)
* [Top Entity](#Top-Entity)
* [**Getting Started**](#Getting-Started)
* [Contact](#Contact)
* [Contribute](#Contribute)
* [Legal](#Legal)
 
 
32,7 → 27,7
 
The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled and configured via VHDL generics.
 
This project comes with a complete software ecosystem that features core libraries for high-level usage of the
provided functions and peripherals, application makefiles and example programs. All software source files
61,22 → 56,23
 
The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
 
| | |
| Project | Status |
|:--------------------------------------------------------------------------------|:-------|
| NEORV32 processor | [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) |
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [![Build Test](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [![Build Status](https://travis-ci.com/stnolting/neorv32_riscv_compliance.svg?branch=master)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
 
 
#### Limitations to be fixed
### Limitations to be fixed
 
* No exception is triggered in `E`-mode when using registers above `x15` yet
 
 
#### To-Do / Wish List
### To-Do / Wish List
 
- Synthesis results for more platforms
- Port Dhrystone benchmark
- Implement atomic operations (`A` extension)
- Implement `Zifence` extension
- Implement co-processor for single-precision floating-point operations (`F` extension)
- Implement user mode (`U` extension)
- Make a 64-bit branch
155,9 → 151,9
* Store address misaligned
* Store access fault
* Environment call from M-mode (via `ecall` instruction)
* Machine software instrrupt
* Machine timer interrupt (via `MTIME` unit)
* Machine external interrupt (via `CLIC` unit)
* Machine software instrrupt `msi`
* Machine timer interrupt `mti` (via MTIME unit)
* Machine external interrupt `mei` (via CLIC unit)
 
**Privileged architecture / FENCE.I** (`Zifencei` extension):
* System instructions: `FENCE.I`
263,9 → 259,9
 
### Instruction Cycles
 
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
consecutive micro operations. Hence, each instruction requires several clock cycles to execute. The average CPI
(cycles per instruction) depends on the instruction mix of a specific applications and also on the available
The NEORV32 CPU is based on two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
CPU extensions.
 
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
272,7 → 268,8
`M` extension use a bit-serial approach and require several cycles for completion.
 
The following table shows the performance results for successfully running 2000 CoreMark
iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
dividing the total number of required clock cycles (all of CoreMark
– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
were generated using optimization `-O2`.
 
413,7 → 410,7
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
 
 
### Dowload the Project and Create a Hardware Project
### Dowload the NEORV32 Project and Create a Hardware Project
 
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
`git` from the command line (suggested for easy project updates via `git pull`):
429,18 → 426,18
propagated:
 
```vhdl
entity neorv32_test_setup is
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0' -- UART receive data
);
end neorv32_test_setup;
entity neorv32_test_setup is
port (
-- Global control --
clk_i : in std_ulogic := '0'; -- global clock, rising edge
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic := '0' -- UART receive data
);
end neorv32_test_setup;
```
 
This test setup is intended as quick and easy "hello world" test setup to get into the NEORV32.
453,11 → 450,10
 
neorv32/sw/example/blink_led$ make check
 
The NEORV32 project includes some example programs from which you can start your own application:
[SW example projects](https://github.com/stnolting/neorv32/tree/master/sw/example)
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
executable `neorv32_exe.bin` in the same folder.
 
Simply compile one of these projects. This will create a NEORV32 executable `neorv32_exe.bin` in the same folder.
 
neorv32/sw/example/blink_led$ make clean_all compile
 
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
470,21 → 466,52
- No transmission / flow control protocol (raw bytes only)
- Newline on `\r\n` (carriage return & newline)
 
Use the bootloader console to upload and execute your application image.
Use the bootloader console to upload the `neorv32_exe.bin` file and run your application image.
 
Going further: Take a look at the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
```
<< NEORV32 Bootloader >>
BLDV: Jul 6 2020
HWV: 1.0.1.0
CLK: 0x0134FD90 Hz
MHID: 0x0001CE40
MISA: 0x42801104
CONF: 0x03FF0035
IMEM: 0x00010000 bytes @ 0x00000000
DMEM: 0x00010000 bytes @ 0x80000000
Autoboot in 8s. Press key to abort.
Aborted.
Available CMDs:
h: Help
r: Restart
u: Upload
s: Store to flash
l: Load from flash
e: Execute
CMD:> u
Awaiting neorv32_exe.bin... OK
CMD:> e
Booting...
Blinking LED demo program
```
 
Going further: Take a look at the _Let's Get It Started!_ chapter of the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
 
 
## Contact
 
If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a
[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
## Contribute
 
stnolting@gmail.com
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
to open a [new issue](https://github.com/stnolting/neorv32/issues).
 
If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
 
 
 
## Citation
 
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
498,7 → 525,7
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
Other implied/used projects might have different licensing - see their documentation to get more information.
 
**BSD 3-Clause License**
#### BSD 3-Clause License
 
Copyright (c) 2020, Stephan Nolting. All rights reserved.
 
525,6 → 552,19
OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
#### Limitation of Liability for External Links
 
Our website contains links to the websites of third parties („external links“). As the
content of these websites is not under our control, we cannot assume any liability for
such external content. In all cases, the provider of information of the linked websites
is liable for the content and accuracy of the information provided. At the point in time
when the links were placed, no infringements of the law were recognisable to us. As soon
as an infringement of the law becomes known to us, we will immediately remove the
link in question.
 
 
#### Propretary Notice
 
"Windows" is a trademark of Microsoft Corporation.
 
"Artix" and "Vivado" are trademarks of Xilinx Inc.
536,6 → 576,8
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
 
 
#### Misc
 
[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)
 
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).

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