OpenCores
URL https://opencores.org/ocsvn/neural_net_perceptron/neural_net_perceptron/trunk

Subversion Repositories neural_net_perceptron

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neural_net_perceptron
    from Rev 4 to Rev 5
    ↔ Reverse comparison
  •

Rev 4 → Rev 5

/trunk/rtl/vhdl/memory_vhd_v03_pkg.vhd
0,0 → 1,190
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Created: 24-02-2022 13:24:00
--
-----------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY work;
 
PACKAGE memory_vhd_v03_pkg IS
-- /////////////////\\\\\\\\\\\\\\\\\\\
-- ************************************
-- *** User Settings ***
-- ************************************
 
-- Wishbone Bus
CONSTANT WB_DATA_WIDTH : integer := 32; -- Wishbone Data Bus width
CONSTANT WB_ADDR_WIDTH : integer := 5; -- Wishbone Address Bus width
 
CONSTANT VENDOR : string := "generic"; -- (generic, altera, xilinx)
-- NOT IMPLEMENTED YET
 
-- Bus width (DATA_T) of all memories (all are equal)
-- Chose a value high enough to hold all possible values cumulated in
-- y_inj_reg,
-- Memory t,
-- Memory bias,
-- Memory w
CONSTANT DATA_WIDTH : integer := 8;
 
-- Address width of s input vector memory (maximum number of components/inputs = 2**MEM_S_ADDR_WIDTH)
CONSTANT MEM_S_ADDR_WIDTH : integer := 3; -- = 8
 
-- Address width of t output vector memory (maximum number of neurons/outputs = 2**MEM_T_ADDR_WIDTH)
CONSTANT MEM_T_ADDR_WIDTH : integer := 2; -- = 4
-- /////////////////\\\\\\\\\\\\\\\\\\\
-- /////////////////\\\\\\\\\\\\\\\\\\\
 
 
-- ************************************
-- *** System Constants ***
-- *** DO NOT CHANGE ***
-- ************************************
-- Number of maximum usable components/inputs - 1
CONSTANT I_MAX : integer := ( 2 ** MEM_S_ADDR_WIDTH ) - 1;
-- Number of maximum usable neurons/outputs - 1
CONSTANT J_MAX : integer := ( 2 ** MEM_T_ADDR_WIDTH ) - 1;
-- Width of Memory Latency counter (mem_rd_lat_reg)
CONSTANT MEM_LAT_CNT_WIDTH : integer := 7; -- At least 3 bits width -> latency 0...2
-- Value to reach for leaving counting loops
CONSTANT MEM_LAT_CNT_TRANSITION : integer := ( 2 ** MEM_LAT_CNT_WIDTH ) - 1;
-- Number of memory write lines (to build up the RD/WR vector
CONSTANT MEM_WR_LINES : integer := 5;
CONSTANT MEM_S_BITPOS : integer := MEM_WR_LINES - 5;
CONSTANT MEM_T_BITPOS : integer := MEM_WR_LINES - 4;
CONSTANT MEM_W_BITPOS : integer := MEM_WR_LINES - 3;
CONSTANT MEM_Y_BITPOS : integer := MEM_WR_LINES - 2;
CONSTANT MEM_BIAS_BITPOS : integer := MEM_WR_LINES - 1;
-- Status READY FOR COMMANDS bit position
CONSTANT STAT_RDY : integer := 0;
-- Status Latency Messurement in progress
CONSTANT STAT_LAT_RUN : integer := 1;
-- Status Controller is NOT ready -> RESET (while start of function TRAIN)
CONSTANT STAT_NOT_RDY : integer := 2;
-- Status Interrupt Enable
CONSTANT STAT_INT_EN : integer := 3;
-- Status Memory Error
CONSTANT STAT_MEMERR : integer := 4;
-- Status DATA OUTPUT READY bit position
CONSTANT STAT_RD_WR_COMPLETE : integer := 5;
-- Status Interrupt TEST pending
CONSTANT STAT_INT_TEST : integer := 6;
-- Status Interrupt TRAIN pending
CONSTANT STAT_INT_TRAIN : integer := 7;
 
 
-- Calculate all memory address widths and other dependencies
-- s input memory depth
CONSTANT MEM_S_DEPTH : integer := ( 2**MEM_S_ADDR_WIDTH ) - 1;
-- t output memory depth
CONSTANT MEM_T_DEPTH : integer := ( 2**MEM_T_ADDR_WIDTH ) - 1;
-- w (weights) memory address width calculation
CONSTANT MEM_W_ADDR_WIDTH : integer := MEM_S_ADDR_WIDTH + MEM_T_ADDR_WIDTH;
-- w (weights) memory depths calculation
CONSTANT MEM_W_DEPTH : integer := ( 2**MEM_W_ADDR_WIDTH ) - 1;
 
-- ************************************
-- Wishbone Address Map
CONSTANT WB_STAT_A : integer := 0; --
CONSTANT WB_THRES : integer := 1; --
CONSTANT WB_BIAS : integer := 2; --
CONSTANT WB_OFFSET : integer := 3; --
CONSTANT WB_MAXEPOCH : integer := 4; --
CONSTANT WB_UNUSED_X05 : integer := 5; -- DO NOT USE, for feature use
CONSTANT WB_UNUSED_X06 : integer := 6; -- DO NOT USE, for feature use
CONSTANT WB_STARTI : integer := 7; --
CONSTANT WB_STOPI : integer := 8; --
CONSTANT WB_STARTJ : integer := 9; --
 
CONSTANT WB_STOPJ : integer := 10; --
CONSTANT WB_EPOCH : integer := 11; --
CONSTANT WB_WRLAT : integer := 12; --
CONSTANT WB_RDLAT : integer := 13; --
CONSTANT WB_ALLLAT : integer := 14; --
CONSTANT WB_START3 : integer := 15; --
CONSTANT WB_START4 : integer := 16; --
CONSTANT WB_START5_S : integer := 17; --
CONSTANT WB_START5_T : integer := 18; --
CONSTANT WB_START5_W : integer := 19; --
 
CONSTANT WB_START5_Y : integer := 20; --
CONSTANT WB_START5_BIAS : integer := 21; --
CONSTANT WB_START6 : integer := 22; --
CONSTANT WB_IMAX : integer := 23; --
CONSTANT WB_JMAX : integer := 24; --
CONSTANT WB_MEMDATA_WIDTH : integer := 25; --
-- ************************************
-- ************************************
-- *** Type Definitions ***
-- ************************************
-- Wishbone data and address types
SUBTYPE WB_DATA_WIDTH_T IS std_logic_vector ( WB_DATA_WIDTH-1 downto 0 );
SUBTYPE WB_ADDR_WIDTH_T IS std_logic_vector ( WB_ADDR_WIDTH-1 downto 0 );
 
-- Data bus type for all memories
SUBTYPE DATA_T IS std_logic_vector ( DATA_WIDTH-1 downto 0 );
SUBTYPE DATA_N IS integer range DATA_WIDTH-1 downto 0;
-- Memory Latency counter type
SUBTYPE MEM_LAT_CNT_WIDTH_T IS std_logic_vector ( MEM_LAT_CNT_WIDTH-1 downto 0 );
-- Vector bus to select memory RD or WR
SUBTYPE MEM_WR_LINES_T IS std_logic_vector ( MEM_WR_LINES-1 downto 0 );
-- Declare the types for all memory address busses
-- s input memory
SUBTYPE ADDRESS_S_T IS std_logic_vector ( MEM_S_ADDR_WIDTH-1 downto 0 );
SUBTYPE ADDRESS_S_N IS integer range MEM_S_ADDR_WIDTH-1 downto 0;
SUBTYPE ADDRESS_S_ZERO_T IS std_logic_vector ( MEM_S_ADDR_WIDTH-1 downto 1 );
-- t input/output memory
SUBTYPE ADDRESS_T_T IS std_logic_vector ( MEM_T_ADDR_WIDTH-1 downto 0 );
SUBTYPE ADDRESS_T_N IS integer range MEM_T_ADDR_WIDTH-1 downto 0;
SUBTYPE ADDRESS_T_ZERO_T IS std_logic_vector ( MEM_T_ADDR_WIDTH-1 downto 1 );
-- w (weigths) memory
SUBTYPE ADDRESS_W_T IS std_logic_vector ( MEM_W_ADDR_WIDTH-1 downto 0 );
-- Declare the types for all memory arrays
-- s input memory
TYPE S_RAM_T IS ARRAY ( MEM_S_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 );
-- t output memory
TYPE T_RAM_T IS ARRAY ( MEM_T_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 );
-- w (weights) memory
TYPE W_RAM_T IS ARRAY ( MEM_W_DEPTH DOWNTO 0 ) OF std_logic_vector( DATA_WIDTH-1 DOWNTO 0 );
-- ************************************
SUBTYPE SIM_STATE_T IS integer;
 
CONSTANT ST0 : SIM_STATE_T := 0;
CONSTANT INIT : SIM_STATE_T := 1;
CONSTANT WR1 : SIM_STATE_T := 2;
CONSTANT WR_13_BURST : SIM_STATE_T := 3;
CONSTANT WR_13_END : SIM_STATE_T := 4;
CONSTANT WR_7_SINGLE : SIM_STATE_T := 5;
CONSTANT WR_7_END : SIM_STATE_T := 6;
CONSTANT ST7 : SIM_STATE_T := 7;
END memory_vhd_v03_pkg;
 
 
/trunk/rtl/vhdl/p0300_m00000_s_v03_top_level_blk.vhd
0,0 → 1,270
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00000_s_v03_top_level_blk IS
PORT(
wb_adr_i : IN WB_ADDR_WIDTH_T;
wb_clk_i : IN std_logic;
wb_cyc_i : IN std_logic;
wb_dat_i : IN WB_DATA_WIDTH_T;
wb_rst_i : IN std_logic;
wb_stb_i : IN std_logic;
wb_we_i : IN std_logic;
ctrl_int_o : OUT std_logic;
wb_ack_o : OUT std_logic;
wb_dat_o : OUT WB_DATA_WIDTH_T
);
 
-- Declarations
 
END p0300_m00000_s_v03_top_level_blk ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
--
-- Revision 3.0 2022/07/04
-- - Update wiring and connections
-- - Insert new versioned symbol of U_0
-- Revision 2.0 2022/06/13
-- - Insert new versioned symbol of U_0
-- Revision 1.0 2022/06/12
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
 
ARCHITECTURE struct OF p0300_m00000_s_v03_top_level_blk IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL addr_i_oi : ADDRESS_S_T;
SIGNAL addr_j_oi : ADDRESS_T_T;
SIGNAL dbias_oi : DATA_T;
SIGNAL dout1_oi : DATA_T;
SIGNAL dout2_oi : DATA_T;
SIGNAL dout3_oi : DATA_T;
SIGNAL dout4_oi : DATA_T;
SIGNAL dout5_oi : DATA_T;
SIGNAL dout7_oi : DATA_T;
SIGNAL ds_oi : DATA_T;
SIGNAL dt_oi : DATA_T;
SIGNAL dw_oi : DATA_T;
SIGNAL dy_oi : DATA_T;
SIGNAL we_bias2_oi : std_logic;
SIGNAL we_bias3_oi : std_logic;
SIGNAL we_bias5_oi : std_logic;
SIGNAL we_s3_oi : std_logic;
SIGNAL we_s4_oi : std_logic;
SIGNAL we_s5_oi : std_logic;
SIGNAL we_t3_oi : std_logic;
SIGNAL we_t4_oi : std_logic;
SIGNAL we_t5_oi : std_logic;
SIGNAL we_w2_oi : std_logic;
SIGNAL we_w3_oi : std_logic;
SIGNAL we_w4_oi : std_logic;
SIGNAL we_w5_oi : std_logic;
SIGNAL we_w7_oi : std_logic;
SIGNAL we_y1_oi : std_logic;
SIGNAL we_y3_oi : std_logic;
SIGNAL we_y5_oi : std_logic;
 
 
-- Component Declarations
COMPONENT p0300_m00020_s_v03_perceptron_blk
PORT (
clk_i : IN std_logic ;
dbias_i : IN DATA_T ;
ds_i : IN DATA_T ;
dt_i : IN DATA_T ;
dw_i : IN DATA_T ;
dy_i : IN DATA_T ;
rst_i : IN std_logic ;
wb_adr_i : IN WB_ADDR_WIDTH_T ;
wb_cyc_i : IN std_logic ;
wb_dat_i : IN WB_DATA_WIDTH_T ;
wb_stb_i : IN std_logic ;
wb_we_i : IN std_logic ;
addr_i_o : OUT ADDRESS_S_T ;
addr_j_o : OUT ADDRESS_T_T ;
ctrl_int_o : OUT std_logic ;
dout1_o : OUT DATA_T ;
dout2_o : OUT DATA_T ;
dout3_o : OUT DATA_T ;
dout4_o : OUT DATA_T ;
dout5_o : OUT DATA_T ;
dout7_o : OUT DATA_T ;
wb_ack_o : OUT std_logic ;
wb_dat_o : OUT WB_DATA_WIDTH_T ;
we_bias2_o : OUT std_logic ;
we_bias3_o : OUT std_logic ;
we_bias5_o : OUT std_logic ;
we_s3_o : OUT std_logic ;
we_s4_o : OUT std_logic ;
we_s5_o : OUT std_logic ;
we_t3_o : OUT std_logic ;
we_t4_o : OUT std_logic ;
we_t5_o : OUT std_logic ;
we_w2_o : OUT std_logic ;
we_w3_o : OUT std_logic ;
we_w4_o : OUT std_logic ;
we_w5_o : OUT std_logic ;
we_w7_o : OUT std_logic ;
we_y1_o : OUT std_logic ;
we_y3_o : OUT std_logic ;
we_y5_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00100_s_v01_mem_gen_blk
PORT (
addr_i_i : IN ADDRESS_S_T ;
addr_j_i : IN ADDRESS_T_T ;
clk_i : IN std_logic ;
din1_i : IN DATA_T ;
din2_i : IN DATA_T ;
din3_i : IN DATA_T ;
din4_i : IN DATA_T ;
din5_i : IN DATA_T ;
din7_i : IN DATA_T ;
we_bias2_i : IN std_logic ;
we_bias3_i : IN std_logic ;
we_bias5_i : IN std_logic ;
we_s3_i : IN std_logic ;
we_s4_i : IN std_logic ;
we_s5_i : IN std_logic ;
we_t3_i : IN std_logic ;
we_t4_i : IN std_logic ;
we_t5_i : IN std_logic ;
we_w2_i : IN std_logic ;
we_w3_i : IN std_logic ;
we_w4_i : IN std_logic ;
we_w5_i : IN std_logic ;
we_w7_i : IN std_logic ;
we_y1_i : IN std_logic ;
we_y3_i : IN std_logic ;
we_y5_i : IN std_logic ;
dbias_o : OUT DATA_T ;
ds_o : OUT DATA_T ;
dt_o : OUT DATA_T ;
dw_o : OUT DATA_T ;
dy_o : OUT DATA_T
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : p0300_m00020_s_v03_perceptron_blk USE ENTITY work.p0300_m00020_s_v03_perceptron_blk;
FOR ALL : p0300_m00100_s_v01_mem_gen_blk USE ENTITY work.p0300_m00100_s_v01_mem_gen_blk;
-- pragma synthesis_on
 
 
BEGIN
 
-- Instance port mappings.
U_0 : p0300_m00020_s_v03_perceptron_blk
PORT MAP (
clk_i => wb_clk_i,
dbias_i => dbias_oi,
ds_i => ds_oi,
dt_i => dt_oi,
dw_i => dw_oi,
dy_i => dy_oi,
rst_i => wb_rst_i,
wb_adr_i => wb_adr_i,
wb_cyc_i => wb_cyc_i,
wb_dat_i => wb_dat_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
addr_i_o => addr_i_oi,
addr_j_o => addr_j_oi,
ctrl_int_o => ctrl_int_o,
dout1_o => dout1_oi,
dout2_o => dout2_oi,
dout3_o => dout3_oi,
dout4_o => dout4_oi,
dout5_o => dout5_oi,
dout7_o => dout7_oi,
wb_ack_o => wb_ack_o,
wb_dat_o => wb_dat_o,
we_bias2_o => we_bias2_oi,
we_bias3_o => we_bias3_oi,
we_bias5_o => we_bias5_oi,
we_s3_o => we_s3_oi,
we_s4_o => we_s4_oi,
we_s5_o => we_s5_oi,
we_t3_o => we_t3_oi,
we_t4_o => we_t4_oi,
we_t5_o => we_t5_oi,
we_w2_o => we_w2_oi,
we_w3_o => we_w3_oi,
we_w4_o => we_w4_oi,
we_w5_o => we_w5_oi,
we_w7_o => we_w7_oi,
we_y1_o => we_y1_oi,
we_y3_o => we_y3_oi,
we_y5_o => we_y5_oi
);
U_1 : p0300_m00100_s_v01_mem_gen_blk
PORT MAP (
addr_i_i => addr_i_oi,
addr_j_i => addr_j_oi,
clk_i => wb_clk_i,
din1_i => dout1_oi,
din2_i => dout2_oi,
din3_i => dout3_oi,
din4_i => dout4_oi,
din5_i => dout5_oi,
din7_i => dout7_oi,
we_bias2_i => we_bias2_oi,
we_bias3_i => we_bias3_oi,
we_bias5_i => we_bias5_oi,
we_s3_i => we_s3_oi,
we_s4_i => we_s4_oi,
we_s5_i => we_s5_oi,
we_t3_i => we_t3_oi,
we_t4_i => we_t4_oi,
we_t5_i => we_t5_oi,
we_w2_i => we_w2_oi,
we_w3_i => we_w3_oi,
we_w4_i => we_w4_oi,
we_w5_i => we_w5_oi,
we_w7_i => we_w7_oi,
we_y1_i => we_y1_oi,
we_y3_i => we_y3_oi,
we_y5_i => we_y5_oi,
dbias_o => dbias_oi,
ds_o => ds_oi,
dt_o => dt_oi,
dw_o => dw_oi,
dy_o => dy_oi
);
 
END struct;
/trunk/rtl/vhdl/p0300_m00020_s_v03_perceptron_blk.vhd
0,0 → 1,668
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00020_s_v03_perceptron_blk IS
PORT(
clk_i : IN std_logic;
dbias_i : IN DATA_T;
ds_i : IN DATA_T;
dt_i : IN DATA_T;
dw_i : IN DATA_T;
dy_i : IN DATA_T;
rst_i : IN std_logic;
wb_adr_i : IN WB_ADDR_WIDTH_T;
wb_cyc_i : IN std_logic;
wb_dat_i : IN WB_DATA_WIDTH_T;
wb_stb_i : IN std_logic;
wb_we_i : IN std_logic;
addr_i_o : OUT ADDRESS_S_T;
addr_j_o : OUT ADDRESS_T_T;
ctrl_int_o : OUT std_logic;
dout1_o : OUT DATA_T;
dout2_o : OUT DATA_T;
dout3_o : OUT DATA_T;
dout4_o : OUT DATA_T;
dout5_o : OUT DATA_T;
dout7_o : OUT DATA_T;
wb_ack_o : OUT std_logic;
wb_dat_o : OUT WB_DATA_WIDTH_T;
we_bias2_o : OUT std_logic;
we_bias3_o : OUT std_logic;
we_bias5_o : OUT std_logic;
we_s3_o : OUT std_logic;
we_s4_o : OUT std_logic;
we_s5_o : OUT std_logic;
we_t3_o : OUT std_logic;
we_t4_o : OUT std_logic;
we_t5_o : OUT std_logic;
we_w2_o : OUT std_logic;
we_w3_o : OUT std_logic;
we_w4_o : OUT std_logic;
we_w5_o : OUT std_logic;
we_w7_o : OUT std_logic;
we_y1_o : OUT std_logic;
we_y3_o : OUT std_logic;
we_y5_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00020_s_v03_perceptron_blk ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 3.0 2022/07/04
-- - Update wiring and connections
-- - Insert all new versioned symbols
-- Revision 2.0 2022/06/18
-- - Update wiring and connections
-- - Insert all new versioned symbols
-- Revision 1.0 2022/06/12
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
 
ARCHITECTURE struct OF p0300_m00020_s_v03_perceptron_blk IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL cnt_alllat_oi : MEM_LAT_CNT_WIDTH_T;
SIGNAL cnteni1_oi : std_logic;
SIGNAL cnteni2_oi : std_logic;
SIGNAL cnteni3_oi : std_logic;
SIGNAL cnteni4_oi : std_logic;
SIGNAL cnteni5_oi : std_logic;
SIGNAL cnteni7_oi : std_logic;
SIGNAL cntenj1_oi : std_logic;
SIGNAL cntenj2_oi : std_logic;
SIGNAL cntenj3_oi : std_logic;
SIGNAL cntenj4_oi : std_logic;
SIGNAL cntenj5_oi : std_logic;
SIGNAL cntenj7_oi : std_logic;
SIGNAL cnti_end_oi : std_logic;
SIGNAL cnti_rdy_oi : std_logic;
SIGNAL cntj_end_oi : std_logic;
SIGNAL cntj_rdy_oi : std_logic;
SIGNAL ctrl_bias_oi : DATA_T;
SIGNAL ctrl_clear_epoch_oi : std_logic;
SIGNAL ctrl_complete_oi : std_logic;
SIGNAL ctrl_din_oi : DATA_T;
SIGNAL ctrl_dout_oi : DATA_T;
SIGNAL ctrl_dout_valid_oi : std_logic;
SIGNAL ctrl_epoch_oi : WB_DATA_WIDTH_T;
SIGNAL ctrl_int4_o : std_logic;
SIGNAL ctrl_int6_o : std_logic;
SIGNAL ctrl_maxepoch_oi : WB_DATA_WIDTH_T;
SIGNAL ctrl_memerr_oi : std_logic;
SIGNAL ctrl_not_rdy6_oi : std_logic;
SIGNAL ctrl_offset_oi : DATA_T;
SIGNAL ctrl_rd_vec_oi : MEM_WR_LINES_T;
SIGNAL ctrl_rdlat_oi : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_rdy1_oi : std_logic;
SIGNAL ctrl_rdy2_oi : std_logic;
SIGNAL ctrl_rdy3_oi : std_logic;
SIGNAL ctrl_rdy4_oi : std_logic;
SIGNAL ctrl_rdy5_oi : std_logic;
SIGNAL ctrl_rdy6_oi : std_logic;
SIGNAL ctrl_rdy7_oi : std_logic;
SIGNAL ctrl_run7_oi : std_logic;
SIGNAL ctrl_start1_oi : std_logic;
SIGNAL ctrl_start2_oi : std_logic;
SIGNAL ctrl_start3_oi : std_logic;
SIGNAL ctrl_start4_oi : std_logic;
SIGNAL ctrl_start5_oi : std_logic;
SIGNAL ctrl_start6_oi : std_logic;
SIGNAL ctrl_thres_oi : DATA_T;
SIGNAL ctrl_wchgd_oi : std_logic;
SIGNAL ctrl_wr_vec_oi : MEM_WR_LINES_T;
SIGNAL ctrl_wrlat_oi : MEM_LAT_CNT_WIDTH_T;
SIGNAL rst_n_oi : std_logic;
SIGNAL set_initi_oi : std_logic;
SIGNAL set_initj_oi : std_logic;
SIGNAL starti_val_oi : ADDRESS_S_T;
SIGNAL startj_val_oi : ADDRESS_T_T;
SIGNAL stopi_val_oi : ADDRESS_S_T;
SIGNAL stopj_val_oi : ADDRESS_T_T;
 
 
-- Component Declarations
COMPONENT p0300_m00021_s_v03_wishbone_fsm
PORT (
clk_i : IN std_logic ;
ctrl_alllat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_complete_i : IN std_logic ;
ctrl_dout_i : IN DATA_T ;
ctrl_dout_valid_i : IN std_logic ;
ctrl_epoch_i : IN WB_DATA_WIDTH_T ;
ctrl_int_test_i : IN std_logic ;
ctrl_int_train_i : IN std_logic ;
ctrl_memerr_i : IN std_logic ;
ctrl_not_rdy6_i : IN std_logic ;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy1_i : IN std_logic ;
ctrl_rdy2_i : IN std_logic ;
ctrl_rdy3_i : IN std_logic ;
ctrl_rdy4_i : IN std_logic ;
ctrl_rdy5_i : IN std_logic ;
ctrl_rdy6_i : IN std_logic ;
ctrl_run7_i : IN std_logic ;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ;
rst_n_i : IN std_logic ;
wb_adr_i : IN WB_ADDR_WIDTH_T ;
wb_cyc_i : IN std_logic ;
wb_dat_i : IN WB_DATA_WIDTH_T ;
wb_stb_i : IN std_logic ;
wb_we_i : IN std_logic ;
ctrl_bias_o : OUT DATA_T ;
ctrl_clear_epoch_o : OUT std_logic ;
ctrl_din_o : OUT DATA_T ;
ctrl_int_o : OUT std_logic ;
ctrl_maxepoch_o : OUT WB_DATA_WIDTH_T ;
ctrl_offset_o : OUT DATA_T ;
ctrl_rd_vec_o : OUT MEM_WR_LINES_T ;
ctrl_set_starti_o : OUT std_logic ;
ctrl_set_startj_o : OUT std_logic ;
ctrl_start3_o : OUT std_logic ;
ctrl_start4_o : OUT std_logic ;
ctrl_start5_o : OUT std_logic ;
ctrl_start6_o : OUT std_logic ;
ctrl_starti_val_o : OUT ADDRESS_S_T ;
ctrl_startj_val_o : OUT ADDRESS_T_T ;
ctrl_stopi_val_o : OUT ADDRESS_S_T ;
ctrl_stopj_val_o : OUT ADDRESS_T_T ;
ctrl_thres_o : OUT DATA_T ;
ctrl_wr_vec_o : OUT MEM_WR_LINES_T ;
wb_ack_o : OUT std_logic ;
wb_dat_o : OUT WB_DATA_WIDTH_T
);
END COMPONENT;
COMPONENT p0300_m00022_s_v02_cal_y_fsm
PORT (
clk_i : IN std_logic ;
cnti_end_i : IN std_logic ;
cntj_end_i : IN std_logic ;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy7_i : IN std_logic ;
ctrl_start_i : IN std_logic ;
ctrl_thres_i : IN DATA_T ;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ;
dbias_i : IN DATA_T ;
ds_i : IN DATA_T ;
dw_i : IN DATA_T ;
rst_n_i : IN std_logic ;
cnteni_o : OUT std_logic ;
cntenj_o : OUT std_logic ;
ctrl_rdy_o : OUT std_logic ;
dout_o : OUT DATA_T ;
we_y_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00023_s_v02_cal_w_fsm
PORT (
clk_i : IN std_logic ;
cnti_end_i : IN std_logic ;
cntj_end_i : IN std_logic ;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy7_i : IN std_logic ;
ctrl_start_i : IN std_logic ;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ;
dbias_i : IN DATA_T ;
ds_i : IN DATA_T ;
dt_i : IN DATA_T ;
dw_i : IN DATA_T ;
dy_i : IN DATA_T ;
rst_n_i : IN std_logic ;
cnteni_o : OUT std_logic ;
cntenj_o : OUT std_logic ;
ctrl_rdy_o : OUT std_logic ;
ctrl_wchgd_o : OUT std_logic ;
dout_o : OUT DATA_T ;
we_bias_o : OUT std_logic ;
we_w_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00024_s_v02_test_fsm
PORT (
clk_i : IN std_logic ;
cnti_end_i : IN std_logic ;
cntj_end_i : IN std_logic ;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy7_i : IN std_logic ;
ctrl_start_i : IN std_logic ;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ds_i : IN DATA_T ;
dt_i : IN DATA_T ;
dw_i : IN DATA_T ;
offset_i : IN DATA_T ;
rst_n_i : IN std_logic ;
cnteni_o : OUT std_logic ;
cntenj_o : OUT std_logic ;
ctrl_int_o : OUT std_logic ;
ctrl_rdy_o : OUT std_logic ;
dout_o : OUT DATA_T ;
we_s_o : OUT std_logic ;
we_t_o : OUT std_logic ;
we_w_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00025_s_v02_init_fsm
PORT (
clk_i : IN std_logic ;
cnti_end_i : IN std_logic ;
cntj_end_i : IN std_logic ;
ctrl_bias_i : IN DATA_T ;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy7_i : IN std_logic ;
ctrl_start_i : IN std_logic ;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ;
rst_n_i : IN std_logic ;
cnteni_o : OUT std_logic ;
cntenj_o : OUT std_logic ;
ctrl_rdy_o : OUT std_logic ;
dout_o : OUT DATA_T ;
we_bias_o : OUT std_logic ;
we_s_o : OUT std_logic ;
we_t_o : OUT std_logic ;
we_w_o : OUT std_logic ;
we_y_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00026_s_v02_rd_wr_fsm
PORT (
clk_i : IN std_logic ;
cnti_end_i : IN std_logic ;
cntj_end_i : IN std_logic ;
ctrl_din_i : IN DATA_T ;
ctrl_rd_vec_i : IN MEM_WR_LINES_T ;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy7_i : IN std_logic ;
ctrl_start_i : IN std_logic ;
ctrl_wr_vec_i : IN MEM_WR_LINES_T ;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T ;
dbias_i : IN DATA_T ;
ds_i : IN DATA_T ;
dt_i : IN DATA_T ;
dw_i : IN DATA_T ;
dy_i : IN DATA_T ;
rst_n_i : IN std_logic ;
cnteni_o : OUT std_logic ;
cntenj_o : OUT std_logic ;
ctrl_complete_o : OUT std_logic ;
ctrl_dout_o : OUT DATA_T ;
ctrl_dout_valid_o : OUT std_logic ;
ctrl_rdy_o : OUT std_logic ;
dout_o : OUT DATA_T ;
we_bias_o : OUT std_logic ;
we_s_o : OUT std_logic ;
we_t_o : OUT std_logic ;
we_w_o : OUT std_logic ;
we_y_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00027_s_v01_train_fsm
PORT (
clk_i : IN std_logic ;
cnti_rdy_i : IN std_logic ;
cntj_rdy_i : IN std_logic ;
ctrl_clear_epoch_i : IN std_logic ;
ctrl_maxepoch_i : IN WB_DATA_WIDTH_T ;
ctrl_rdy1_i : IN std_logic ;
ctrl_rdy2_i : IN std_logic ;
ctrl_rdy7_i : IN std_logic ;
ctrl_start_i : IN std_logic ;
ctrl_wchgd_i : IN std_logic ;
rst_n_i : IN std_logic ;
ctrl_epoch_o : OUT WB_DATA_WIDTH_T ;
ctrl_int_o : OUT std_logic ;
ctrl_not_rdy_o : OUT std_logic ;
ctrl_rdy_o : OUT std_logic ;
ctrl_start1_o : OUT std_logic ;
ctrl_start2_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00028_s_v02_latency_fsm
PORT (
clk_i : IN std_logic ;
dw_i : IN DATA_T ;
rst_n_i : IN std_logic ;
cnt_alllat_o : OUT MEM_LAT_CNT_WIDTH_T ;
cnteni_o : OUT std_logic ;
cntenj_o : OUT std_logic ;
ctrl_memerr_o : OUT std_logic ;
ctrl_rdlat_o : OUT MEM_LAT_CNT_WIDTH_T ;
ctrl_rdy_o : OUT std_logic ;
ctrl_run_o : OUT std_logic ;
ctrl_wrlat_o : OUT MEM_LAT_CNT_WIDTH_T ;
dout_o : OUT DATA_T ;
we_w_o : OUT std_logic
);
END COMPONENT;
COMPONENT p0300_m00033_s_v01_for_loop_memwi_fsm
PORT (
clk_i : IN std_logic ;
cnten1_i : IN std_logic ;
cnten2_i : IN std_logic ;
cnten3_i : IN std_logic ;
cnten4_i : IN std_logic ;
cnten5_i : IN std_logic ;
cnten7_i : IN std_logic ;
rst_n_i : IN std_logic ;
set_init_i : IN std_logic ;
start_vali_i : IN ADDRESS_S_T ;
stop_vali_i : IN ADDRESS_S_T ;
cnt_end_o : OUT std_logic ;
cnt_rdy_o : OUT std_logic ;
cnt_val_o : OUT ADDRESS_S_T
);
END COMPONENT;
COMPONENT p0300_m00034_s_v01_for_loop_memwj_fsm
PORT (
clk_i : IN std_logic ;
cnten1_i : IN std_logic ;
cnten2_i : IN std_logic ;
cnten3_i : IN std_logic ;
cnten4_i : IN std_logic ;
cnten5_i : IN std_logic ;
cnten7_i : IN std_logic ;
rst_n_i : IN std_logic ;
set_init_i : IN std_logic ;
start_valj_i : IN ADDRESS_T_T ;
stop_valj_i : IN ADDRESS_T_T ;
cnt_end_o : OUT std_logic ;
cnt_rdy_o : OUT std_logic ;
cnt_val_o : OUT ADDRESS_T_T
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : p0300_m00021_s_v03_wishbone_fsm USE ENTITY work.p0300_m00021_s_v03_wishbone_fsm;
FOR ALL : p0300_m00022_s_v02_cal_y_fsm USE ENTITY work.p0300_m00022_s_v02_cal_y_fsm;
FOR ALL : p0300_m00023_s_v02_cal_w_fsm USE ENTITY work.p0300_m00023_s_v02_cal_w_fsm;
FOR ALL : p0300_m00024_s_v02_test_fsm USE ENTITY work.p0300_m00024_s_v02_test_fsm;
FOR ALL : p0300_m00025_s_v02_init_fsm USE ENTITY work.p0300_m00025_s_v02_init_fsm;
FOR ALL : p0300_m00026_s_v02_rd_wr_fsm USE ENTITY work.p0300_m00026_s_v02_rd_wr_fsm;
FOR ALL : p0300_m00027_s_v01_train_fsm USE ENTITY work.p0300_m00027_s_v01_train_fsm;
FOR ALL : p0300_m00028_s_v02_latency_fsm USE ENTITY work.p0300_m00028_s_v02_latency_fsm;
FOR ALL : p0300_m00033_s_v01_for_loop_memwi_fsm USE ENTITY work.p0300_m00033_s_v01_for_loop_memwi_fsm;
FOR ALL : p0300_m00034_s_v01_for_loop_memwj_fsm USE ENTITY work.p0300_m00034_s_v01_for_loop_memwj_fsm;
-- pragma synthesis_on
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
rst_n_oi <= NOT ( rst_i );
 
 
-- Instance port mappings.
U_14 : p0300_m00021_s_v03_wishbone_fsm
PORT MAP (
clk_i => clk_i,
ctrl_alllat_i => cnt_alllat_oi,
ctrl_complete_i => ctrl_complete_oi,
ctrl_dout_i => ctrl_dout_oi,
ctrl_dout_valid_i => ctrl_dout_valid_oi,
ctrl_epoch_i => ctrl_epoch_oi,
ctrl_int_test_i => ctrl_int4_o,
ctrl_int_train_i => ctrl_int6_o,
ctrl_memerr_i => ctrl_memerr_oi,
ctrl_not_rdy6_i => ctrl_not_rdy6_oi,
ctrl_rdlat_i => ctrl_rdlat_oi,
ctrl_rdy1_i => ctrl_rdy1_oi,
ctrl_rdy2_i => ctrl_rdy2_oi,
ctrl_rdy3_i => ctrl_rdy3_oi,
ctrl_rdy4_i => ctrl_rdy4_oi,
ctrl_rdy5_i => ctrl_rdy5_oi,
ctrl_rdy6_i => ctrl_rdy6_oi,
ctrl_run7_i => ctrl_run7_oi,
ctrl_wrlat_i => ctrl_wrlat_oi,
rst_n_i => rst_n_oi,
wb_adr_i => wb_adr_i,
wb_cyc_i => wb_cyc_i,
wb_dat_i => wb_dat_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
ctrl_bias_o => ctrl_bias_oi,
ctrl_clear_epoch_o => ctrl_clear_epoch_oi,
ctrl_din_o => ctrl_din_oi,
ctrl_int_o => ctrl_int_o,
ctrl_maxepoch_o => ctrl_maxepoch_oi,
ctrl_offset_o => ctrl_offset_oi,
ctrl_rd_vec_o => ctrl_rd_vec_oi,
ctrl_set_starti_o => set_initi_oi,
ctrl_set_startj_o => set_initj_oi,
ctrl_start3_o => ctrl_start3_oi,
ctrl_start4_o => ctrl_start4_oi,
ctrl_start5_o => ctrl_start5_oi,
ctrl_start6_o => ctrl_start6_oi,
ctrl_starti_val_o => starti_val_oi,
ctrl_startj_val_o => startj_val_oi,
ctrl_stopi_val_o => stopi_val_oi,
ctrl_stopj_val_o => stopj_val_oi,
ctrl_thres_o => ctrl_thres_oi,
ctrl_wr_vec_o => ctrl_wr_vec_oi,
wb_ack_o => wb_ack_o,
wb_dat_o => wb_dat_o
);
U_0 : p0300_m00022_s_v02_cal_y_fsm
PORT MAP (
clk_i => clk_i,
cnti_end_i => cnti_end_oi,
cntj_end_i => cntj_end_oi,
ctrl_rdlat_i => ctrl_rdlat_oi,
ctrl_rdy7_i => ctrl_rdy7_oi,
ctrl_start_i => ctrl_start1_oi,
ctrl_thres_i => ctrl_thres_oi,
ctrl_wrlat_i => ctrl_wrlat_oi,
dbias_i => dbias_i,
ds_i => ds_i,
dw_i => dw_i,
rst_n_i => rst_n_oi,
cnteni_o => cnteni1_oi,
cntenj_o => cntenj1_oi,
ctrl_rdy_o => ctrl_rdy1_oi,
dout_o => dout1_o,
we_y_o => we_y1_o
);
U_8 : p0300_m00023_s_v02_cal_w_fsm
PORT MAP (
clk_i => clk_i,
cnti_end_i => cnti_end_oi,
cntj_end_i => cntj_end_oi,
ctrl_rdlat_i => ctrl_rdlat_oi,
ctrl_rdy7_i => ctrl_rdy7_oi,
ctrl_start_i => ctrl_start2_oi,
ctrl_wrlat_i => ctrl_wrlat_oi,
dbias_i => dbias_i,
ds_i => ds_i,
dt_i => dt_i,
dw_i => dw_i,
dy_i => dy_i,
rst_n_i => rst_n_oi,
cnteni_o => cnteni2_oi,
cntenj_o => cntenj2_oi,
ctrl_rdy_o => ctrl_rdy2_oi,
ctrl_wchgd_o => ctrl_wchgd_oi,
dout_o => dout2_o,
we_bias_o => we_bias2_o,
we_w_o => we_w2_o
);
U_10 : p0300_m00024_s_v02_test_fsm
PORT MAP (
clk_i => clk_i,
cnti_end_i => cnti_end_oi,
cntj_end_i => cntj_end_oi,
ctrl_rdlat_i => ctrl_rdlat_oi,
ctrl_rdy7_i => ctrl_rdy7_oi,
ctrl_start_i => ctrl_start4_oi,
ctrl_wrlat_i => ctrl_wrlat_oi,
ds_i => ds_i,
dt_i => dt_i,
dw_i => dw_i,
offset_i => ctrl_offset_oi,
rst_n_i => rst_n_oi,
cnteni_o => cnteni4_oi,
cntenj_o => cntenj4_oi,
ctrl_int_o => ctrl_int4_o,
ctrl_rdy_o => ctrl_rdy4_oi,
dout_o => dout4_o,
we_s_o => we_s4_o,
we_t_o => we_t4_o,
we_w_o => we_w4_o
);
U_9 : p0300_m00025_s_v02_init_fsm
PORT MAP (
clk_i => clk_i,
cnti_end_i => cnti_end_oi,
cntj_end_i => cntj_end_oi,
ctrl_bias_i => ctrl_bias_oi,
ctrl_rdlat_i => ctrl_rdlat_oi,
ctrl_rdy7_i => ctrl_rdy7_oi,
ctrl_start_i => ctrl_start3_oi,
ctrl_wrlat_i => ctrl_wrlat_oi,
rst_n_i => rst_n_oi,
cnteni_o => cnteni3_oi,
cntenj_o => cntenj3_oi,
ctrl_rdy_o => ctrl_rdy3_oi,
dout_o => dout3_o,
we_bias_o => we_bias3_o,
we_s_o => we_s3_o,
we_t_o => we_t3_o,
we_w_o => we_w3_o,
we_y_o => we_y3_o
);
U_11 : p0300_m00026_s_v02_rd_wr_fsm
PORT MAP (
clk_i => clk_i,
cnti_end_i => cnti_end_oi,
cntj_end_i => cntj_end_oi,
ctrl_din_i => ctrl_din_oi,
ctrl_rd_vec_i => ctrl_rd_vec_oi,
ctrl_rdlat_i => ctrl_rdlat_oi,
ctrl_rdy7_i => ctrl_rdy7_oi,
ctrl_start_i => ctrl_start5_oi,
ctrl_wr_vec_i => ctrl_wr_vec_oi,
ctrl_wrlat_i => ctrl_wrlat_oi,
dbias_i => dbias_i,
ds_i => ds_i,
dt_i => dt_i,
dw_i => dw_i,
dy_i => dy_i,
rst_n_i => rst_n_oi,
cnteni_o => cnteni5_oi,
cntenj_o => cntenj5_oi,
ctrl_complete_o => ctrl_complete_oi,
ctrl_dout_o => ctrl_dout_oi,
ctrl_dout_valid_o => ctrl_dout_valid_oi,
ctrl_rdy_o => ctrl_rdy5_oi,
dout_o => dout5_o,
we_bias_o => we_bias5_o,
we_s_o => we_s5_o,
we_t_o => we_t5_o,
we_w_o => we_w5_o,
we_y_o => we_y5_o
);
U_12 : p0300_m00027_s_v01_train_fsm
PORT MAP (
clk_i => clk_i,
cnti_rdy_i => cnti_rdy_oi,
cntj_rdy_i => cntj_rdy_oi,
ctrl_clear_epoch_i => ctrl_clear_epoch_oi,
ctrl_maxepoch_i => ctrl_maxepoch_oi,
ctrl_rdy1_i => ctrl_rdy1_oi,
ctrl_rdy2_i => ctrl_rdy2_oi,
ctrl_rdy7_i => ctrl_rdy7_oi,
ctrl_start_i => ctrl_start6_oi,
ctrl_wchgd_i => ctrl_wchgd_oi,
rst_n_i => rst_n_oi,
ctrl_epoch_o => ctrl_epoch_oi,
ctrl_int_o => ctrl_int6_o,
ctrl_not_rdy_o => ctrl_not_rdy6_oi,
ctrl_rdy_o => ctrl_rdy6_oi,
ctrl_start1_o => ctrl_start1_oi,
ctrl_start2_o => ctrl_start2_oi
);
U_13 : p0300_m00028_s_v02_latency_fsm
PORT MAP (
clk_i => clk_i,
dw_i => dw_i,
rst_n_i => rst_n_oi,
cnt_alllat_o => cnt_alllat_oi,
cnteni_o => cnteni7_oi,
cntenj_o => cntenj7_oi,
ctrl_memerr_o => ctrl_memerr_oi,
ctrl_rdlat_o => ctrl_rdlat_oi,
ctrl_rdy_o => ctrl_rdy7_oi,
ctrl_run_o => ctrl_run7_oi,
ctrl_wrlat_o => ctrl_wrlat_oi,
dout_o => dout7_o,
we_w_o => we_w7_o
);
U_2 : p0300_m00033_s_v01_for_loop_memwi_fsm
PORT MAP (
clk_i => clk_i,
cnten1_i => cnteni1_oi,
cnten2_i => cnteni2_oi,
cnten3_i => cnteni3_oi,
cnten4_i => cnteni4_oi,
cnten5_i => cnteni5_oi,
cnten7_i => cnteni7_oi,
rst_n_i => rst_n_oi,
set_init_i => set_initi_oi,
start_vali_i => starti_val_oi,
stop_vali_i => stopi_val_oi,
cnt_end_o => cnti_end_oi,
cnt_rdy_o => cnti_rdy_oi,
cnt_val_o => addr_i_o
);
U_1 : p0300_m00034_s_v01_for_loop_memwj_fsm
PORT MAP (
clk_i => clk_i,
cnten1_i => cntenj1_oi,
cnten2_i => cntenj2_oi,
cnten3_i => cntenj3_oi,
cnten4_i => cntenj4_oi,
cnten5_i => cntenj5_oi,
cnten7_i => cntenj7_oi,
rst_n_i => rst_n_oi,
set_init_i => set_initj_oi,
start_valj_i => startj_val_oi,
stop_valj_i => stopj_val_oi,
cnt_end_o => cntj_end_oi,
cnt_rdy_o => cntj_rdy_oi,
cnt_val_o => addr_j_o
);
 
END struct;
/trunk/rtl/vhdl/p0300_m00021_s_v03_wishbone_fsm.vhd
0,0 → 1,867
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00021_s_v03_wishbone_fsm IS
PORT(
clk_i : IN std_logic;
ctrl_alllat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_complete_i : IN std_logic;
ctrl_dout_i : IN DATA_T;
ctrl_dout_valid_i : IN std_logic;
ctrl_epoch_i : IN WB_DATA_WIDTH_T;
ctrl_int_test_i : IN std_logic;
ctrl_int_train_i : IN std_logic;
ctrl_memerr_i : IN std_logic;
ctrl_not_rdy6_i : IN std_logic;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_rdy1_i : IN std_logic;
ctrl_rdy2_i : IN std_logic;
ctrl_rdy3_i : IN std_logic;
ctrl_rdy4_i : IN std_logic;
ctrl_rdy5_i : IN std_logic;
ctrl_rdy6_i : IN std_logic;
ctrl_run7_i : IN std_logic;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
rst_n_i : IN std_logic;
wb_adr_i : IN WB_ADDR_WIDTH_T;
wb_cyc_i : IN std_logic;
wb_dat_i : IN WB_DATA_WIDTH_T;
wb_stb_i : IN std_logic;
wb_we_i : IN std_logic;
ctrl_bias_o : OUT DATA_T;
ctrl_clear_epoch_o : OUT std_logic;
ctrl_din_o : OUT DATA_T;
ctrl_int_o : OUT std_logic;
ctrl_maxepoch_o : OUT WB_DATA_WIDTH_T;
ctrl_offset_o : OUT DATA_T;
ctrl_rd_vec_o : OUT MEM_WR_LINES_T;
ctrl_set_starti_o : OUT std_logic;
ctrl_set_startj_o : OUT std_logic;
ctrl_start3_o : OUT std_logic;
ctrl_start4_o : OUT std_logic;
ctrl_start5_o : OUT std_logic;
ctrl_start6_o : OUT std_logic;
ctrl_starti_val_o : OUT ADDRESS_S_T;
ctrl_startj_val_o : OUT ADDRESS_T_T;
ctrl_stopi_val_o : OUT ADDRESS_S_T;
ctrl_stopj_val_o : OUT ADDRESS_T_T;
ctrl_thres_o : OUT DATA_T;
ctrl_wr_vec_o : OUT MEM_WR_LINES_T;
wb_ack_o : OUT std_logic;
wb_dat_o : OUT WB_DATA_WIDTH_T
);
 
-- Declarations
 
END p0300_m00021_s_v03_wishbone_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 3.0 2022/07/21
-- - Delete alpha register and output
-- - Consolidate # cycles
-- Revision 2.0 2022/06/18
-- - Introduce self-resets for status signals
-- - Remove states introduced for debugging
-- Revision 1.0 2022/06/11
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00021_s_v03_wishbone_fsm IS
 
-- Architecture Declarations
SIGNAL ctrl_bias_reg : DATA_T;
SIGNAL ctrl_complete_reg : std_logic;
SIGNAL ctrl_din_reg : DATA_T;
SIGNAL ctrl_int_en_reg : std_logic;
SIGNAL ctrl_int_test_reg : std_logic;
SIGNAL ctrl_int_train_reg : std_logic;
SIGNAL ctrl_maxepoch_reg : WB_DATA_WIDTH_T;
SIGNAL ctrl_offset_reg : DATA_T;
SIGNAL ctrl_rd_vec_reg : MEM_WR_LINES_T;
SIGNAL ctrl_rdy_reg : std_logic;
SIGNAL ctrl_starti_val_reg : ADDRESS_S_T;
SIGNAL ctrl_startj_val_reg : ADDRESS_T_T;
SIGNAL ctrl_stat_a_reg : DATA_T;
SIGNAL ctrl_stopi_val_reg : ADDRESS_S_T;
SIGNAL ctrl_stopj_val_reg : ADDRESS_T_T;
SIGNAL ctrl_thres_reg : DATA_T;
SIGNAL ctrl_wr_vec_reg : MEM_WR_LINES_T;
SIGNAL wb_adr_reg : WB_ADDR_WIDTH_T;
SIGNAL wb_cyc_reg : std_logic;
SIGNAL wb_dat_reg : WB_DATA_WIDTH_T;
SIGNAL wb_stb_reg : std_logic;
SIGNAL wb_we_reg : std_logic;
SIGNAL zero_net_addrs : ADDRESS_S_ZERO_T;
SIGNAL zero_net_addrt : ADDRESS_T_ZERO_T;
 
TYPE STATE_TYPE IS (
S03,
S01,
S04,
S06,
S07,
S08,
S09,
S10,
S11,
S12,
S13,
S17,
S18,
S19,
S20,
S21,
S22,
S23,
S24,
S25,
S26,
S27,
S28,
S29,
S30,
S31,
S32,
S33,
S34,
S35,
S36,
S37,
S38,
S39,
S40,
S41,
S00,
S46,
S47,
S02,
S48,
S14,
S15,
S01a
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
ctrl_bias_reg <= (others => '0');
ctrl_complete_reg <= '0';
ctrl_din_reg <= (others => '0');
ctrl_int_en_reg <= '0';
ctrl_int_test_reg <= '0';
ctrl_int_train_reg <= '0';
ctrl_maxepoch_reg <= (others => '0');
ctrl_offset_reg <= (others => '0');
ctrl_rd_vec_reg <= (others => '0');
ctrl_rdy_reg <= '0';
ctrl_starti_val_reg <= (others => '0');
ctrl_startj_val_reg <= (others => '0');
ctrl_stat_a_reg <= (others => '0');
ctrl_stopi_val_reg <= zero_net_addrs & '1';
ctrl_stopj_val_reg <= zero_net_addrt & '1';
ctrl_thres_reg <= (others => '0');
ctrl_wr_vec_reg <= (others => '0');
wb_adr_reg <= (others => '0');
wb_cyc_reg <= '0';
wb_dat_reg <= (others => '0');
wb_stb_reg <= '0';
wb_we_reg <= '0';
ELSE
current_state <= next_state;
-- Default Assignment To Internals
ctrl_bias_reg <= ctrl_bias_reg;
ctrl_complete_reg <= ctrl_complete_reg OR ctrl_complete_i;
ctrl_din_reg <= ctrl_din_reg;
ctrl_int_en_reg <= ctrl_int_en_reg;
ctrl_int_test_reg <= ctrl_int_test_reg OR ctrl_int_test_i;
ctrl_int_train_reg <= ctrl_int_train_reg OR ctrl_int_train_i;
ctrl_maxepoch_reg <= ctrl_maxepoch_reg;
ctrl_offset_reg <= ctrl_offset_reg;
ctrl_rd_vec_reg <= ctrl_rd_vec_reg;
ctrl_rdy_reg <= ctrl_rdy1_i AND ctrl_rdy2_i AND ctrl_rdy3_i AND ctrl_rdy4_i AND ctrl_rdy5_i AND ctrl_rdy6_i;
ctrl_starti_val_reg <= ctrl_starti_val_reg;
ctrl_startj_val_reg <= ctrl_startj_val_reg;
ctrl_stat_a_reg <= ctrl_stat_a_reg;
ctrl_stopi_val_reg <= ctrl_stopi_val_reg;
ctrl_stopj_val_reg <= ctrl_stopj_val_reg;
ctrl_thres_reg <= ctrl_thres_reg;
ctrl_wr_vec_reg <= ctrl_wr_vec_reg;
wb_adr_reg <= wb_adr_i;
wb_cyc_reg <= wb_cyc_i;
wb_dat_reg <= wb_dat_i;
wb_stb_reg <= wb_stb_i;
wb_we_reg <= wb_we_i;
 
-- Combined Actions
CASE current_state IS
-- READ Status A
WHEN S03 =>
ctrl_complete_reg <= ctrl_complete_i OR ( ctrl_complete_reg AND ( NOT ( ctrl_stat_a_reg (STAT_RD_WR_COMPLETE) ) ) );
ctrl_int_test_reg <= ctrl_int_test_i OR ( ctrl_int_test_reg AND ( NOT ( ctrl_stat_a_reg (STAT_INT_TEST) ) ) );
ctrl_int_train_reg <= ctrl_int_train_i OR ( ctrl_int_train_reg AND ( NOT ( ctrl_stat_a_reg (STAT_INT_TRAIN) ) ) );
-- Wait for
-- transfer/phase
WHEN S01 =>
ctrl_stat_a_reg (STAT_RDY) <= ctrl_rdy_reg;
ctrl_stat_a_reg (STAT_LAT_RUN) <= ctrl_run7_i;
ctrl_stat_a_reg (STAT_NOT_RDY) <= ctrl_not_rdy6_i;
ctrl_stat_a_reg (STAT_INT_EN) <= ctrl_int_en_reg;
ctrl_stat_a_reg (STAT_MEMERR) <= ctrl_memerr_i;
ctrl_stat_a_reg (STAT_RD_WR_COMPLETE) <= ctrl_complete_reg AND ctrl_rdy_reg;
ctrl_stat_a_reg (STAT_INT_TEST) <= ctrl_int_test_reg AND ctrl_rdy_reg;
ctrl_stat_a_reg (STAT_INT_TRAIN) <= ctrl_int_train_reg AND ctrl_rdy_reg;
-- WRITE Threshold
-- register
WHEN S04 =>
ctrl_thres_reg <= wb_dat_reg (DATA_N);
-- WRITE Bias
-- register
WHEN S08 =>
ctrl_bias_reg <= wb_dat_reg (DATA_N);
-- WRITE Offset
-- register
WHEN S10 =>
ctrl_offset_reg <= wb_dat_reg (DATA_N);
-- WRITE Maxepochs
-- register
WHEN S12 =>
ctrl_maxepoch_reg <= wb_dat_reg;
-- WRITE Start i
-- register
WHEN S18 =>
ctrl_starti_val_reg <= wb_dat_reg (ADDRESS_S_N);
-- WRITE Start j
-- register
WHEN S20 =>
ctrl_startj_val_reg <= wb_dat_reg (ADDRESS_T_N);
-- WRITE Stop i
-- register
WHEN S22 =>
ctrl_stopi_val_reg <= wb_dat_reg (ADDRESS_S_N);
-- WRITE Stop j
-- register
WHEN S24 =>
ctrl_stopj_val_reg <= wb_dat_reg (ADDRESS_T_N);
-- WRITE SMEM
WHEN S32 =>
ctrl_rd_vec_reg <= "00001";
ctrl_wr_vec_reg <= "00001";
ctrl_din_reg <= wb_dat_reg (DATA_N);
-- WRITE TMEM
WHEN S33 =>
ctrl_rd_vec_reg <= "00010";
ctrl_wr_vec_reg <= "00010";
ctrl_din_reg <= wb_dat_reg (DATA_N);
-- WRITE WMEM
WHEN S34 =>
ctrl_rd_vec_reg <= "00100";
ctrl_wr_vec_reg <= "00100";
ctrl_din_reg <= wb_dat_reg (DATA_N);
-- WRITE YMEM
WHEN S35 =>
ctrl_rd_vec_reg <= "01000";
ctrl_wr_vec_reg <= "01000";
ctrl_din_reg <= wb_dat_reg (DATA_N);
-- WRITE BIASMEM
WHEN S36 =>
ctrl_rd_vec_reg <= "10000";
ctrl_wr_vec_reg <= "10000";
ctrl_din_reg <= wb_dat_reg (DATA_N);
-- READ SMEM
WHEN S37 =>
ctrl_rd_vec_reg <= "00001";
-- READ TMEM
WHEN S38 =>
ctrl_rd_vec_reg <= "00010";
-- READ WMEM
WHEN S39 =>
ctrl_rd_vec_reg <= "00100";
-- READ YMEM
WHEN S40 =>
ctrl_rd_vec_reg <= "01000";
-- READ BIASMEM
WHEN S41 =>
ctrl_rd_vec_reg <= "10000";
-- WRITE Status A
WHEN S02 =>
ctrl_int_en_reg <= wb_dat_reg (STAT_INT_EN);
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
ctrl_rdy3_i,
ctrl_rdy4_i,
ctrl_rdy5_i,
current_state,
wb_adr_reg,
wb_cyc_reg,
wb_stb_reg,
wb_we_reg
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- READ Status A
WHEN S03 =>
next_state <= S01a;
-- Wait for
-- transfer/phase
WHEN S01 =>
IF (unsigned (wb_adr_reg) = WB_STAT_A AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S03;
ELSIF (unsigned (wb_adr_reg) = WB_THRES AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S06;
ELSIF (unsigned (wb_adr_reg) = WB_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S07;
ELSIF (unsigned (wb_adr_reg) = WB_OFFSET AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S09;
ELSIF (unsigned (wb_adr_reg) = WB_MAXEPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S11;
ELSIF (unsigned (wb_adr_reg) = WB_IMAX AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S13;
ELSIF (unsigned (wb_adr_reg) = WB_STARTI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S17;
ELSIF (unsigned (wb_adr_reg) = WB_STOPI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S21;
ELSIF (unsigned (wb_adr_reg) = WB_STARTJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S19;
ELSIF (unsigned (wb_adr_reg) = WB_STOPJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S23;
ELSIF (unsigned (wb_adr_reg) = WB_EPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S25;
ELSIF (unsigned (wb_adr_reg) = WB_WRLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S26;
ELSIF (unsigned (wb_adr_reg) = WB_RDLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S27;
ELSIF (unsigned (wb_adr_reg) = WB_ALLLAT AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S28;
ELSIF (unsigned (wb_adr_reg) = WB_START5_S AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S37;
ELSIF (unsigned (wb_adr_reg) = WB_START5_T AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S38;
ELSIF (unsigned (wb_adr_reg) = WB_START5_W AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S39;
ELSIF (unsigned (wb_adr_reg) = WB_START5_Y AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S40;
ELSIF (unsigned (wb_adr_reg) = WB_START5_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S41;
ELSIF (unsigned (wb_adr_reg) = WB_THRES AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S04;
ELSIF (unsigned (wb_adr_reg) = WB_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S08;
ELSIF (unsigned (wb_adr_reg) = WB_OFFSET AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S10;
ELSIF (unsigned (wb_adr_reg) = WB_MAXEPOCH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S12;
ELSIF (unsigned (wb_adr_reg) = WB_STARTI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S18;
ELSIF (unsigned (wb_adr_reg) = WB_STOPI AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S22;
ELSIF (unsigned (wb_adr_reg) = WB_STARTJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S20;
ELSIF (unsigned (wb_adr_reg) = WB_STOPJ AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S24;
ELSIF (unsigned (wb_adr_reg) = WB_START3 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S29;
ELSIF (unsigned (wb_adr_reg) = WB_START4 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S30;
ELSIF (unsigned (wb_adr_reg) = WB_START5_S AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S32;
ELSIF (unsigned (wb_adr_reg) = WB_START5_T AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S33;
ELSIF (unsigned (wb_adr_reg) = WB_START5_W AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S34;
ELSIF (unsigned (wb_adr_reg) = WB_START5_Y AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S35;
ELSIF (unsigned (wb_adr_reg) = WB_START5_BIAS AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S36;
ELSIF (unsigned (wb_adr_reg) = WB_START6 AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S31;
ELSIF (unsigned (wb_adr_reg) = WB_STAT_A AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '1') THEN
next_state <= S02;
ELSIF (unsigned (wb_adr_reg) = WB_JMAX AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S14;
ELSIF (unsigned (wb_adr_reg) = WB_MEMDATA_WIDTH AND wb_stb_reg = '1' AND wb_cyc_reg = '1' AND wb_we_reg = '0') THEN
next_state <= S15;
ELSIF (wb_stb_reg = '1' AND wb_cyc_reg = '1') THEN
next_state <= S48;
ELSE
next_state <= S01;
END IF;
-- WRITE Threshold
-- register
WHEN S04 =>
next_state <= S01a;
-- READ Threshold
-- register
WHEN S06 =>
next_state <= S01a;
-- READ Bias
-- register
WHEN S07 =>
next_state <= S01a;
-- WRITE Bias
-- register
WHEN S08 =>
next_state <= S01a;
-- READ Offset
-- register
WHEN S09 =>
next_state <= S01a;
-- WRITE Offset
-- register
WHEN S10 =>
next_state <= S01a;
-- READ Maxepochs
-- register
WHEN S11 =>
next_state <= S01a;
-- WRITE Maxepochs
-- register
WHEN S12 =>
next_state <= S01a;
-- READ maximum
-- rows i
WHEN S13 =>
next_state <= S01a;
-- READ Start i
-- register
WHEN S17 =>
next_state <= S01a;
-- WRITE Start i
-- register
WHEN S18 =>
next_state <= S01a;
-- READ Start j
-- register
WHEN S19 =>
next_state <= S01a;
-- WRITE Start j
-- register
WHEN S20 =>
next_state <= S01a;
-- READ Stop i
-- register
WHEN S21 =>
next_state <= S01a;
-- WRITE Stop i
-- register
WHEN S22 =>
next_state <= S01a;
-- READ Stop j
-- register
WHEN S23 =>
next_state <= S01a;
-- WRITE Stop j
-- register
WHEN S24 =>
next_state <= S01a;
-- READ Epochs
-- register
WHEN S25 =>
next_state <= S01a;
-- READ coded
-- WR Lat
-- register
WHEN S26 =>
next_state <= S01a;
-- READ coded
-- RD Lat
-- register
WHEN S27 =>
next_state <= S01a;
-- READ decimal
-- Latency register
WHEN S28 =>
next_state <= S01a;
-- Start INIT
WHEN S29 =>
IF (ctrl_rdy3_i = '0') THEN
next_state <= S01a;
ELSE
next_state <= S29;
END IF;
-- Start TEST
WHEN S30 =>
IF (ctrl_rdy4_i = '0') THEN
next_state <= S01a;
ELSE
next_state <= S30;
END IF;
-- Start TRAIN
WHEN S31 =>
next_state <= S01a;
-- WRITE SMEM
WHEN S32 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S47;
END IF;
-- WRITE TMEM
WHEN S33 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S47;
END IF;
-- WRITE WMEM
WHEN S34 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S47;
END IF;
-- WRITE YMEM
WHEN S35 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S47;
END IF;
-- WRITE BIASMEM
WHEN S36 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S47;
END IF;
-- READ SMEM
WHEN S37 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S46;
END IF;
-- READ TMEM
WHEN S38 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S46;
END IF;
-- READ WMEM
WHEN S39 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S46;
END IF;
-- READ YMEM
WHEN S40 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S46;
END IF;
-- READ BIASMEM
WHEN S41 =>
IF (ctrl_rdy5_i = '0') THEN
next_state <= S46;
END IF;
-- Reset state
WHEN S00 =>
next_state <= S01;
-- READ xMEM
WHEN S46 =>
IF (ctrl_rdy5_i = '1') THEN
next_state <= S01a;
ELSE
next_state <= S46;
END IF;
-- WRITE xMEM
WHEN S47 =>
IF (ctrl_rdy5_i = '1') THEN
next_state <= S01a;
ELSE
next_state <= S47;
END IF;
-- WRITE Status A
WHEN S02 =>
next_state <= S01a;
-- Dummy
-- READ / WRITE
WHEN S48 =>
next_state <= S01a;
-- READ maximum
-- colums j
WHEN S14 =>
next_state <= S01a;
-- READ memory
-- data width
WHEN S15 =>
next_state <= S01a;
-- Waite State
WHEN S01a =>
next_state <= S01;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
ctrl_alllat_i,
ctrl_bias_reg,
ctrl_din_reg,
ctrl_dout_i,
ctrl_epoch_i,
ctrl_int_en_reg,
ctrl_int_test_reg,
ctrl_int_train_reg,
ctrl_maxepoch_reg,
ctrl_offset_reg,
ctrl_rd_vec_reg,
ctrl_rdlat_i,
ctrl_rdy3_i,
ctrl_rdy4_i,
ctrl_rdy5_i,
ctrl_starti_val_reg,
ctrl_startj_val_reg,
ctrl_stat_a_reg,
ctrl_stopi_val_reg,
ctrl_stopj_val_reg,
ctrl_thres_reg,
ctrl_wr_vec_reg,
ctrl_wrlat_i,
current_state,
wb_cyc_i,
wb_dat_reg,
wb_stb_i
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
ctrl_bias_o <= ctrl_bias_reg;
ctrl_clear_epoch_o <= '0';
ctrl_din_o <= ctrl_din_reg;
ctrl_int_o <= ctrl_int_en_reg AND (ctrl_int_train_reg OR ctrl_int_test_reg);
ctrl_maxepoch_o <= ctrl_maxepoch_reg;
ctrl_offset_o <= ctrl_offset_reg;
ctrl_rd_vec_o <= ctrl_rd_vec_reg;
ctrl_set_starti_o <= '0';
ctrl_set_startj_o <= '0';
ctrl_start3_o <= '0';
ctrl_start4_o <= '0';
ctrl_start5_o <= '0';
ctrl_start6_o <= '0';
ctrl_starti_val_o <= ctrl_starti_val_reg;
ctrl_startj_val_o <= ctrl_startj_val_reg;
ctrl_stopi_val_o <= ctrl_stopi_val_reg;
ctrl_stopj_val_o <= ctrl_stopj_val_reg;
ctrl_thres_o <= ctrl_thres_reg;
ctrl_wr_vec_o <= ctrl_wr_vec_reg;
wb_ack_o <= '0';
wb_dat_o <= (others => '0');
-- Default Assignment To Internals
zero_net_addrs <= (others => '0');
zero_net_addrt <= (others => '0');
 
-- Combined Actions
CASE current_state IS
-- READ Status A
WHEN S03 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stat_a_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Threshold
-- register
WHEN S04 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Threshold
-- register
WHEN S06 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_thres_reg ) )), WB_DATA_WIDTH ) );
-- READ Bias
-- register
WHEN S07 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_bias_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Bias
-- register
WHEN S08 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Offset
-- register
WHEN S09 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_offset_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Offset
-- register
WHEN S10 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Maxepochs
-- register
WHEN S11 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= ctrl_maxepoch_reg;
-- WRITE Maxepochs
-- register
WHEN S12 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ maximum
-- rows i
WHEN S13 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( I_MAX ) )), WB_DATA_WIDTH ) );
-- READ Start i
-- register
WHEN S17 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_starti_val_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Start i
-- register
WHEN S18 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Start j
-- register
WHEN S19 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_startj_val_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Start j
-- register
WHEN S20 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Stop i
-- register
WHEN S21 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stopi_val_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Stop i
-- register
WHEN S22 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Stop j
-- register
WHEN S23 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_stopj_val_reg ) )), WB_DATA_WIDTH ) );
-- WRITE Stop j
-- register
WHEN S24 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- READ Epochs
-- register
WHEN S25 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= ctrl_epoch_i;
-- READ coded
-- WR Lat
-- register
WHEN S26 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_wrlat_i ) )), WB_DATA_WIDTH ) );
-- READ coded
-- RD Lat
-- register
WHEN S27 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_rdlat_i ) )), WB_DATA_WIDTH ) );
-- READ decimal
-- Latency register
WHEN S28 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( unsigned ( ctrl_alllat_i ) )), WB_DATA_WIDTH ) );
-- Start INIT
WHEN S29 =>
wb_ack_o <= NOT ctrl_rdy3_i AND wb_stb_i AND wb_cyc_i;
ctrl_start3_o <= '1';
-- Start TEST
WHEN S30 =>
wb_ack_o <= NOT ctrl_rdy4_i AND wb_stb_i AND wb_cyc_i;
ctrl_start4_o <= '1';
-- Start TRAIN
WHEN S31 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
ctrl_start6_o <= '1';
ctrl_clear_epoch_o <= wb_dat_reg (0);
-- WRITE SMEM
WHEN S32 =>
ctrl_start5_o <= '1';
-- WRITE TMEM
WHEN S33 =>
ctrl_start5_o <= '1';
-- WRITE WMEM
WHEN S34 =>
ctrl_start5_o <= '1';
-- WRITE YMEM
WHEN S35 =>
ctrl_start5_o <= '1';
-- WRITE BIASMEM
WHEN S36 =>
ctrl_start5_o <= '1';
-- READ SMEM
WHEN S37 =>
ctrl_start5_o <= '1';
-- READ TMEM
WHEN S38 =>
ctrl_start5_o <= '1';
-- READ WMEM
WHEN S39 =>
ctrl_start5_o <= '1';
-- READ YMEM
WHEN S40 =>
ctrl_start5_o <= '1';
-- READ BIASMEM
WHEN S41 =>
ctrl_start5_o <= '1';
-- READ xMEM
WHEN S46 =>
wb_ack_o <= ctrl_rdy5_i AND wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_signed ( (conv_integer ( signed ( ctrl_dout_i ) )), WB_DATA_WIDTH ) );
-- WRITE xMEM
WHEN S47 =>
wb_ack_o <= ctrl_rdy5_i AND wb_stb_i AND wb_cyc_i;
-- WRITE Status A
WHEN S02 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
-- Dummy
-- READ / WRITE
WHEN S48 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= (others => '0');
-- READ maximum
-- colums j
WHEN S14 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( J_MAX ) )), WB_DATA_WIDTH ) );
-- READ memory
-- data width
WHEN S15 =>
wb_ack_o <= wb_stb_i AND wb_cyc_i;
wb_dat_o <= std_logic_vector ( conv_unsigned ( (conv_integer ( ( DATA_WIDTH ) )), WB_DATA_WIDTH ) );
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00022_s_v02_cal_y_fsm.vhd
0,0 → 1,375
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00022_s_v02_cal_y_fsm IS
PORT(
clk_i : IN std_logic;
cnti_end_i : IN std_logic;
cntj_end_i : IN std_logic;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_rdy7_i : IN std_logic;
ctrl_start_i : IN std_logic;
ctrl_thres_i : IN DATA_T;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
dbias_i : IN DATA_T;
ds_i : IN DATA_T;
dw_i : IN DATA_T;
rst_n_i : IN std_logic;
cnteni_o : OUT std_logic;
cntenj_o : OUT std_logic;
ctrl_rdy_o : OUT std_logic;
dout_o : OUT DATA_T;
we_y_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00022_s_v02_cal_y_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 2.0 2022/07/04
-- - Introduced latency for write
-- Revision 1.0 2022/06/25
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00022_s_v02_cal_y_fsm IS
 
-- Architecture Declarations
SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_start_reg : std_logic;
SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL dbias_reg : DATA_T;
SIGNAL dw_reg : DATA_T;
SIGNAL y_inj_reg : DATA_T;
 
TYPE STATE_TYPE IS (
S00,
S03,
S02,
S05,
S04,
S07,
S08,
S10,
S11,
S12,
S13,
S01,
S16,
S06,
S15,
S09,
S14
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
ctrl_rdlat_reg <= (others => '0');
ctrl_start_reg <= '0';
ctrl_wrlat_reg <= (others => '0');
dbias_reg <= (others => '0');
dw_reg <= (others => '0');
y_inj_reg <= (others => '0');
ELSE
current_state <= next_state;
-- Default Assignment To Internals
ctrl_rdlat_reg <= ctrl_rdlat_reg;
ctrl_start_reg <= ctrl_start_i;
ctrl_wrlat_reg <= ctrl_wrlat_reg;
dbias_reg <= dbias_i;
dw_reg <= dw_i;
y_inj_reg <= y_inj_reg;
 
-- Combined Actions
CASE current_state IS
-- ADD if
-- ds GT 0
WHEN S03 =>
--y_inj_reg <= signed (y_inj_reg) + signed (dw_i);
y_inj_reg <= signed (y_inj_reg) + signed (dw_reg);
-- Replacement of multiplication.
-- y_inj calculation and increment
-- i-address.
WHEN S02 =>
ctrl_rdlat_reg <= ctrl_rdlat_i;
-- SUB if
-- ds LT 0
WHEN S05 =>
--y_inj_reg <= signed (y_inj_reg) - signed (dw_i);
y_inj_reg <= signed (y_inj_reg) - signed (dw_reg);
-- Dummy cycles.
-- Loop path for
-- next y_inj-value..
WHEN S07 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Update y_inj-value
-- with bias
WHEN S08 =>
--y_inj_reg <= (signed (y_inj_reg)) + (signed (dbias_i));
y_inj_reg <= (signed (y_inj_reg)) + (signed (dbias_reg));
-- Replacement of
-- multiplication.
-- y calculation.
WHEN S10 =>
ctrl_wrlat_reg <= ctrl_wrlat_i;
-- Larency counter.
-- Return path last j
WHEN S16 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Dummy cycles to
-- equalize latency.
WHEN S06 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Increment
-- j-address
WHEN S15 =>
y_inj_reg <= (others => '0');
ctrl_rdlat_reg <= ctrl_rdlat_i;
-- Dummy cycles to
-- equalize latency.
WHEN S09 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Dummy cycles to
-- equalize latency.
WHEN S14 =>
ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnti_end_i,
cntj_end_i,
ctrl_rdlat_reg,
ctrl_rdy7_i,
ctrl_start_reg,
ctrl_thres_i,
ctrl_wrlat_reg,
current_state,
ds_i,
y_inj_reg
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Reset state
WHEN S00 =>
IF (ctrl_rdy7_i = '1') THEN
next_state <= S01;
ELSE
next_state <= S00;
END IF;
-- ADD if
-- ds GT 0
WHEN S03 =>
next_state <= S06;
-- Replacement of multiplication.
-- y_inj calculation and increment
-- i-address.
WHEN S02 =>
IF (cnti_end_i = '1') THEN
next_state <= S08;
ELSIF (signed (ds_i) > 0) THEN
next_state <= S03;
ELSIF (signed (ds_i) < 0) THEN
next_state <= S05;
ELSE
next_state <= S04;
END IF;
-- SUB if
-- ds LT 0
WHEN S05 =>
next_state <= S06;
-- No function
-- if ds EQ 0
WHEN S04 =>
next_state <= S06;
-- Dummy cycles.
-- Loop path for
-- next y_inj-value..
WHEN S07 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S02;
ELSE
next_state <= S07;
END IF;
-- Update y_inj-value
-- with bias
WHEN S08 =>
next_state <= S09;
-- Replacement of
-- multiplication.
-- y calculation.
WHEN S10 =>
IF (signed (y_inj_reg) < signed (ctrl_thres_i)) THEN
next_state <= S11;
ELSIF (signed (y_inj_reg) > signed (ctrl_thres_i)) THEN
next_state <= S13;
ELSE
next_state <= S12;
END IF;
-- ADD if
-- y_inj GT thres
WHEN S11 =>
next_state <= S14;
-- No function if
-- y_inj EQ thres
WHEN S12 =>
next_state <= S14;
-- SUB if
-- y_inj LT thres
WHEN S13 =>
next_state <= S14;
-- Wait for next
-- calculation of
-- y-values
WHEN S01 =>
IF (ctrl_start_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S01;
END IF;
-- Larency counter.
-- Return path last j
WHEN S16 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S01;
ELSE
next_state <= S16;
END IF;
-- Dummy cycles to
-- equalize latency.
WHEN S06 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
next_state <= S02;
ELSE
next_state <= S06;
END IF;
-- Increment
-- j-address
WHEN S15 =>
IF (cntj_end_i = '1') THEN
next_state <= S16;
ELSE
next_state <= S07;
END IF;
-- Dummy cycles to
-- equalize latency.
WHEN S09 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
next_state <= S10;
ELSE
next_state <= S09;
END IF;
-- Dummy cycles to
-- equalize latency.
WHEN S14 =>
IF (unsigned ( ctrl_wrlat_reg ) <= 3) THEN
next_state <= S15;
ELSE
next_state <= S14;
END IF;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnteni_o <= '0';
cntenj_o <= '0';
ctrl_rdy_o <= '0';
dout_o <= (others => '0');
we_y_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- Replacement of multiplication.
-- y_inj calculation and increment
-- i-address.
WHEN S02 =>
cnteni_o <= '1';
-- ADD if
-- y_inj GT thres
WHEN S11 =>
dout_o <= (others => '1');
we_y_o <= '1';
-- No function if
-- y_inj EQ thres
WHEN S12 =>
dout_o <= (others => '0');
we_y_o <= '1';
-- SUB if
-- y_inj LT thres
WHEN S13 =>
dout_o(0) <= '1';
we_y_o <= '1';
-- Wait for next
-- calculation of
-- y-values
WHEN S01 =>
ctrl_rdy_o <= '1';
-- Increment
-- j-address
WHEN S15 =>
cntenj_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00023_s_v02_cal_w_fsm.vhd
0,0 → 1,367
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00023_s_v02_cal_w_fsm IS
PORT(
clk_i : IN std_logic;
cnti_end_i : IN std_logic;
cntj_end_i : IN std_logic;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_rdy7_i : IN std_logic;
ctrl_start_i : IN std_logic;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
dbias_i : IN DATA_T;
ds_i : IN DATA_T;
dt_i : IN DATA_T;
dw_i : IN DATA_T;
dy_i : IN DATA_T;
rst_n_i : IN std_logic;
cnteni_o : OUT std_logic;
cntenj_o : OUT std_logic;
ctrl_rdy_o : OUT std_logic;
ctrl_wchgd_o : OUT std_logic;
dout_o : OUT DATA_T;
we_bias_o : OUT std_logic;
we_w_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00023_s_v02_cal_w_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 2.0 2022/07/02
-- - Introduced latency for write
-- Revision 1.0 2022/06/29
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00023_s_v02_cal_w_fsm IS
 
-- Architecture Declarations
SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_start_reg : std_logic;
SIGNAL ctrl_wchgd_reg : std_logic;
SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL dbias_reg : DATA_T;
SIGNAL dt_reg : DATA_T;
SIGNAL dw_reg : DATA_T;
 
TYPE STATE_TYPE IS (
S00,
S14,
S06,
S05,
S08,
S07,
S11,
S13,
S03,
S12,
S04,
S15,
S01,
S02,
S10,
S09
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
ctrl_rdlat_reg <= (others => '0');
ctrl_start_reg <= '0';
ctrl_wchgd_reg <= '0';
ctrl_wrlat_reg <= (others => '0');
dbias_reg <= (others => '0');
dt_reg <= (others => '0');
dw_reg <= (others => '0');
ELSE
current_state <= next_state;
-- Default Assignment To Internals
ctrl_rdlat_reg <= ctrl_rdlat_reg;
ctrl_start_reg <= ctrl_start_i;
ctrl_wchgd_reg <= ctrl_wchgd_reg;
ctrl_wrlat_reg <= ctrl_wrlat_reg;
dbias_reg <= dbias_i;
dt_reg <= dt_i;
dw_reg <= dw_i;
 
-- Combined Actions
CASE current_state IS
-- Larency counter.
-- Loop path for
-- next w-/bias-value..
WHEN S14 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Replacement of
-- multiplication.
-- W matrix calculation.
WHEN S05 =>
ctrl_rdlat_reg <= ctrl_rdlat_i;
ctrl_wrlat_reg <= ctrl_wrlat_i;
-- Larency counter.
-- Loop path for
-- next w-value.
WHEN S11 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Increment
-- j-address
WHEN S13 =>
ctrl_rdlat_reg <= ctrl_rdlat_i;
-- w-value
-- changed.
-- Last i
WHEN S12 =>
ctrl_wchgd_reg <= '1';
-- Larency counter.
-- Return path last j
WHEN S15 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Reset "w-value
-- changed"
WHEN S02 =>
ctrl_wchgd_reg <= '0';
-- Dummy cycles to
-- equalize latency.
WHEN S09 =>
ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnti_end_i,
cntj_end_i,
ctrl_rdlat_reg,
ctrl_rdy7_i,
ctrl_start_reg,
ctrl_wrlat_reg,
current_state,
ds_i,
dt_i,
dy_i
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Reset state
WHEN S00 =>
IF (ctrl_rdy7_i = '1') THEN
next_state <= S01;
ELSE
next_state <= S00;
END IF;
-- Larency counter.
-- Loop path for
-- next w-/bias-value..
WHEN S14 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S03;
ELSE
next_state <= S14;
END IF;
-- ADD if
-- ds GT 0
WHEN S06 =>
next_state <= S09;
-- Replacement of
-- multiplication.
-- W matrix calculation.
WHEN S05 =>
IF (signed (ds_i) > 0) THEN
next_state <= S06;
ELSIF (signed (ds_i) < 0) THEN
next_state <= S08;
ELSE
next_state <= S07;
END IF;
-- SUB if
-- ds LT 0
WHEN S08 =>
next_state <= S09;
-- No function
-- if ds EQ 0
WHEN S07 =>
next_state <= S09;
-- Larency counter.
-- Loop path for
-- next w-value.
WHEN S11 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S05;
ELSE
next_state <= S11;
END IF;
-- Increment
-- j-address
WHEN S13 =>
IF (cntj_end_i = '1') THEN
next_state <= S15;
ELSE
next_state <= S14;
END IF;
-- Test for
-- dt EQ dy
WHEN S03 =>
IF (dt_i = dy_i) THEN
next_state <= S13;
ELSE
next_state <= S04;
END IF;
-- w-value
-- changed.
-- Last i
WHEN S12 =>
next_state <= S13;
-- Compute
-- new bias
WHEN S04 =>
next_state <= S05;
-- Larency counter.
-- Return path last j
WHEN S15 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S01;
ELSE
next_state <= S15;
END IF;
-- Wait for next
-- calculation of
-- w-/bias-values
WHEN S01 =>
IF (ctrl_start_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S01;
END IF;
-- Reset "w-value
-- changed"
WHEN S02 =>
next_state <= S03;
-- Increment
-- i-address
WHEN S10 =>
IF (cnti_end_i = '1') THEN
next_state <= S12;
ELSE
next_state <= S11;
END IF;
-- Dummy cycles to
-- equalize latency.
WHEN S09 =>
IF (unsigned ( ctrl_wrlat_reg ) <= 3) THEN
next_state <= S10;
ELSE
next_state <= S09;
END IF;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
ctrl_wchgd_reg,
current_state,
dbias_reg,
dt_reg,
dw_reg
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnteni_o <= '0';
cntenj_o <= '0';
ctrl_rdy_o <= '0';
ctrl_wchgd_o <= ctrl_wchgd_reg;
dout_o <= (others => '0');
we_bias_o <= '0';
we_w_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- ADD if
-- ds GT 0
WHEN S06 =>
--dout_o <= signed (dw_i) + signed (dt_i);
dout_o <= signed (dw_reg) + signed (dt_reg);
we_w_o <= '1';
-- SUB if
-- ds LT 0
WHEN S08 =>
--dout_o <= signed (dw_i) - signed (dt_i);
dout_o <= signed (dw_reg) - signed (dt_reg);
we_w_o <= '1';
-- Increment
-- j-address
WHEN S13 =>
cntenj_o <= '1';
-- Compute
-- new bias
WHEN S04 =>
--dout_o <= signed (dbias_i) + signed (dt_i);
dout_o <= signed (dbias_reg) + signed (dt_reg);
we_bias_o <= '1';
-- Wait for next
-- calculation of
-- w-/bias-values
WHEN S01 =>
ctrl_rdy_o <= '1';
-- Increment
-- i-address
WHEN S10 =>
cnteni_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00024_s_v02_test_fsm.vhd
0,0 → 1,361
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00024_s_v02_test_fsm IS
PORT(
clk_i : IN std_logic;
cnti_end_i : IN std_logic;
cntj_end_i : IN std_logic;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_rdy7_i : IN std_logic;
ctrl_start_i : IN std_logic;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
ds_i : IN DATA_T;
dt_i : IN DATA_T;
dw_i : IN DATA_T;
offset_i : IN DATA_T;
rst_n_i : IN std_logic;
cnteni_o : OUT std_logic;
cntenj_o : OUT std_logic;
ctrl_int_o : OUT std_logic;
ctrl_rdy_o : OUT std_logic;
dout_o : OUT DATA_T;
we_s_o : OUT std_logic;
we_t_o : OUT std_logic;
we_w_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00024_s_v02_test_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 2.0 2022/07/02
-- - Introduced latency for write
-- Revision 1.0 2022/06/17
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00024_s_v02_test_fsm IS
 
-- Architecture Declarations
SIGNAL ctrl_int_reg : std_logic;
SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_start_reg : std_logic;
SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL dt_reg : DATA_T;
SIGNAL dw_reg : DATA_T;
 
TYPE STATE_TYPE IS (
S02,
S05,
S04,
S07,
S06,
S11,
S12,
S13,
S14,
S15,
S01,
S00,
S09,
S08,
S10,
S03
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
ctrl_int_reg <= '0';
ctrl_rdlat_reg <= (others => '0');
ctrl_start_reg <= '0';
ctrl_wrlat_reg <= (others => '0');
dt_reg <= (others => '0');
dw_reg <= (others => '0');
ELSE
current_state <= next_state;
-- Default Assignment To Internals
ctrl_int_reg <= '0';
ctrl_rdlat_reg <= ctrl_rdlat_reg;
ctrl_start_reg <= ctrl_start_i;
ctrl_wrlat_reg <= ctrl_wrlat_reg;
dt_reg <= dt_i;
dw_reg <= dw_i;
 
-- Combined Actions
CASE current_state IS
-- Clear T
WHEN S02 =>
ctrl_wrlat_reg <= ctrl_wrlat_i;
-- Replace
-- multiplication
WHEN S04 =>
ctrl_wrlat_reg <= ctrl_wrlat_i;
-- Dummy cycles to
-- equalize latency.
-- j-path
WHEN S13 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Set interrupt
-- flag
WHEN S14 =>
ctrl_int_reg <= '1';
-- Dummy cycles to
-- equalize latency.
-- End-path
WHEN S15 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Next i
WHEN S09 =>
ctrl_rdlat_reg <= ctrl_rdlat_i;
-- Dummy cycles to
-- equalize latency.
-- Write-path (i)
WHEN S08 =>
ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Dummy cycles to
-- equalize latency.
-- i-path
WHEN S10 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Dummy cycles to
-- equalize latency.
-- Write-path (i)
WHEN S03 =>
ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnti_end_i,
cntj_end_i,
ctrl_rdlat_reg,
ctrl_rdy7_i,
ctrl_start_reg,
ctrl_wrlat_reg,
current_state,
ds_i
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Clear T
WHEN S02 =>
next_state <= S03;
-- ADD if
-- DS > 0
WHEN S05 =>
next_state <= S08;
-- Replace
-- multiplication
WHEN S04 =>
IF (signed (ds_i) > 0) THEN
next_state <= S05;
ELSIF (signed (ds_i) < 0) THEN
next_state <= S07;
ELSE
next_state <= S06;
END IF;
-- SUB if
-- DS < 0
WHEN S07 =>
next_state <= S08;
-- Do nothing if
-- DS = 0
WHEN S06 =>
next_state <= S08;
-- Add offset to T
WHEN S11 =>
next_state <= S12;
-- Next j
WHEN S12 =>
IF (cntj_end_i = '1') THEN
next_state <= S14;
ELSE
next_state <= S13;
END IF;
-- Dummy cycles to
-- equalize latency.
-- j-path
WHEN S13 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S02;
ELSE
next_state <= S13;
END IF;
-- Set interrupt
-- flag
WHEN S14 =>
next_state <= S15;
-- Dummy cycles to
-- equalize latency.
-- End-path
WHEN S15 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
next_state <= S01;
ELSE
next_state <= S15;
END IF;
-- Wait for next
-- TEST request
WHEN S01 =>
IF (ctrl_start_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S01;
END IF;
-- Reset state
WHEN S00 =>
IF (ctrl_rdy7_i = '1') THEN
next_state <= S01;
ELSE
next_state <= S00;
END IF;
-- Next i
WHEN S09 =>
IF (cnti_end_i = '1') THEN
next_state <= S11;
ELSE
next_state <= S10;
END IF;
-- Dummy cycles to
-- equalize latency.
-- Write-path (i)
WHEN S08 =>
IF (unsigned ( ctrl_wrlat_reg ) <= 3) THEN
next_state <= S09;
ELSE
next_state <= S08;
END IF;
-- Dummy cycles to
-- equalize latency.
-- i-path
WHEN S10 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3) THEN
next_state <= S04;
ELSE
next_state <= S10;
END IF;
-- Dummy cycles to
-- equalize latency.
-- Write-path (i)
WHEN S03 =>
IF (unsigned ( ctrl_wrlat_reg ) <= 1) THEN
next_state <= S04;
ELSE
next_state <= S03;
END IF;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
ctrl_int_reg,
current_state,
dt_reg,
dw_reg,
offset_i
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnteni_o <= '0';
cntenj_o <= '0';
ctrl_int_o <= ctrl_int_reg;
ctrl_rdy_o <= '0';
dout_o <= (others => '0');
we_s_o <= '0';
we_t_o <= '0';
we_w_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- Clear T
WHEN S02 =>
dout_o <= (others => '0');
we_t_o <= '1';
-- ADD if
-- DS > 0
WHEN S05 =>
--dout_o <= signed (dt_i) + signed (dw_i);
dout_o <= signed (dt_reg) + signed (dw_reg);
we_t_o <= '1';
-- SUB if
-- DS < 0
WHEN S07 =>
--dout_o <= signed (dt_i) - signed (dw_i);
dout_o <= signed (dt_reg) - signed (dw_reg);
we_t_o <= '1';
-- Add offset to T
WHEN S11 =>
--dout_o <= signed (dt_i) + signed (offset_i);
dout_o <= signed (dt_reg) + signed (offset_i);
we_t_o <= '1';
-- Next j
WHEN S12 =>
cntenj_o <= '1';
-- Wait for next
-- TEST request
WHEN S01 =>
ctrl_rdy_o <= '1';
-- Next i
WHEN S09 =>
cnteni_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00025_s_v02_init_fsm.vhd
0,0 → 1,272
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00025_s_v02_init_fsm IS
PORT(
clk_i : IN std_logic;
cnti_end_i : IN std_logic;
cntj_end_i : IN std_logic;
ctrl_bias_i : IN DATA_T;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_rdy7_i : IN std_logic;
ctrl_start_i : IN std_logic;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
rst_n_i : IN std_logic;
cnteni_o : OUT std_logic;
cntenj_o : OUT std_logic;
ctrl_rdy_o : OUT std_logic;
dout_o : OUT DATA_T;
we_bias_o : OUT std_logic;
we_s_o : OUT std_logic;
we_t_o : OUT std_logic;
we_w_o : OUT std_logic;
we_y_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00025_s_v02_init_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 2.0 2022/07/03
-- - Introduced latency for write
-- Revision 1.0 2022/06/12
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00025_s_v02_init_fsm IS
 
-- Architecture Declarations
SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_start_reg : std_logic;
SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
 
TYPE STATE_TYPE IS (
S00,
S06,
S02,
S03,
S04,
S01,
S08,
S07,
S05
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
ctrl_rdlat_reg <= (others => '0');
ctrl_start_reg <= '0';
ctrl_wrlat_reg <= (others => '0');
ELSE
current_state <= next_state;
-- Default Assignment To Internals
ctrl_rdlat_reg <= ctrl_rdlat_reg;
ctrl_start_reg <= ctrl_start_i;
ctrl_wrlat_reg <= ctrl_wrlat_reg;
 
-- Combined Actions
CASE current_state IS
-- Write W, S. Next i.
-- S also on j-path
WHEN S04 =>
ctrl_rdlat_reg <= ctrl_rdlat_i;
ctrl_wrlat_reg <= ctrl_wrlat_i;
-- Dummy cycles to
-- equalize latency.
-- End-path
WHEN S08 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Dummy cycles to
-- equalize latency.
-- j-path
WHEN S07 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
-- Dummy cycles to
-- equalize latency.
-- i-path
WHEN S05 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnti_end_i,
cntj_end_i,
ctrl_rdlat_reg,
ctrl_rdy7_i,
ctrl_start_reg,
ctrl_wrlat_reg,
current_state
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Reset state
WHEN S00 =>
IF (ctrl_rdy7_i = '1') THEN
next_state <= S01;
ELSE
next_state <= S00;
END IF;
-- Next j
WHEN S06 =>
IF (cntj_end_i = '1') THEN
next_state <= S08;
ELSE
next_state <= S07;
END IF;
-- Write BIAS
WHEN S02 =>
next_state <= S03;
-- Write T and Y
WHEN S03 =>
next_state <= S04;
-- Write W, S. Next i.
-- S also on j-path
WHEN S04 =>
IF (cnti_end_i = '1') THEN
next_state <= S06;
ELSE
next_state <= S05;
END IF;
-- Wait for next
-- INIT request
WHEN S01 =>
IF (ctrl_start_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S01;
END IF;
-- Dummy cycles to
-- equalize latency.
-- End-path
WHEN S08 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
next_state <= S01;
ELSE
next_state <= S08;
END IF;
-- Dummy cycles to
-- equalize latency.
-- j-path
WHEN S07 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
next_state <= S02;
ELSE
next_state <= S07;
END IF;
-- Dummy cycles to
-- equalize latency.
-- i-path
WHEN S05 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 7 AND
unsigned ( ctrl_wrlat_reg ) <= 7) THEN
next_state <= S04;
ELSE
next_state <= S05;
END IF;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
ctrl_bias_i,
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnteni_o <= '0';
cntenj_o <= '0';
ctrl_rdy_o <= '0';
dout_o <= (others => '0');
we_bias_o <= '0';
we_s_o <= '0';
we_t_o <= '0';
we_w_o <= '0';
we_y_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- Next j
WHEN S06 =>
cntenj_o <= '1';
-- Write BIAS
WHEN S02 =>
dout_o <= ctrl_bias_i;
we_bias_o <= '1';
-- Write T and Y
WHEN S03 =>
dout_o <= (others => '0');
we_t_o <= '1';
we_y_o <= '1';
-- Write W, S. Next i.
-- S also on j-path
WHEN S04 =>
dout_o <= (others => '0');
we_w_o <= '1';
we_s_o <= '1';
cnteni_o <= '1';
-- Wait for next
-- INIT request
WHEN S01 =>
ctrl_rdy_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00026_s_v02_rd_wr_fsm.vhd
0,0 → 1,306
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00026_s_v02_rd_wr_fsm IS
PORT(
clk_i : IN std_logic;
cnti_end_i : IN std_logic;
cntj_end_i : IN std_logic;
ctrl_din_i : IN DATA_T;
ctrl_rd_vec_i : IN MEM_WR_LINES_T;
ctrl_rdlat_i : IN MEM_LAT_CNT_WIDTH_T;
ctrl_rdy7_i : IN std_logic;
ctrl_start_i : IN std_logic;
ctrl_wr_vec_i : IN MEM_WR_LINES_T;
ctrl_wrlat_i : IN MEM_LAT_CNT_WIDTH_T;
dbias_i : IN DATA_T;
ds_i : IN DATA_T;
dt_i : IN DATA_T;
dw_i : IN DATA_T;
dy_i : IN DATA_T;
rst_n_i : IN std_logic;
cnteni_o : OUT std_logic;
cntenj_o : OUT std_logic;
ctrl_complete_o : OUT std_logic;
ctrl_dout_o : OUT DATA_T;
ctrl_dout_valid_o : OUT std_logic;
ctrl_rdy_o : OUT std_logic;
dout_o : OUT DATA_T;
we_bias_o : OUT std_logic;
we_s_o : OUT std_logic;
we_t_o : OUT std_logic;
we_w_o : OUT std_logic;
we_y_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00026_s_v02_rd_wr_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 2.0 2022/07/02
-- - Introduced latency for write
-- Revision 1.0 2022/06/09
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00026_s_v02_rd_wr_fsm IS
 
-- Architecture Declarations
SIGNAL ctrl_complete_reg : std_logic;
SIGNAL ctrl_dout_reg : DATA_T;
SIGNAL ctrl_dout_valid_reg : std_logic;
SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_start_reg : std_logic;
SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
 
TYPE STATE_TYPE IS (
S01,
S02,
S12,
S22,
S32,
S42,
S03,
S00
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
ctrl_complete_reg <= '0';
ctrl_dout_reg <= (others => '0');
ctrl_dout_valid_reg <= '0';
ctrl_rdlat_reg <= (others => '0');
ctrl_start_reg <= '0';
ctrl_wrlat_reg <= (others => '0');
ELSE
current_state <= next_state;
-- Default Assignment To Internals
ctrl_complete_reg <= '0';
ctrl_dout_reg <= ctrl_dout_reg;
ctrl_dout_valid_reg <= '0';
ctrl_rdlat_reg <= ctrl_rdlat_reg;
ctrl_start_reg <= ctrl_start_i;
ctrl_wrlat_reg <= ctrl_wrlat_reg;
 
-- Combined Actions
CASE current_state IS
-- Wait for next
-- RD/WR.
WHEN S01 =>
ctrl_rdlat_reg <= ctrl_rdlat_i;
ctrl_wrlat_reg <= ctrl_wrlat_i;
-- RD/WR W
WHEN S02 =>
ctrl_dout_reg <= dw_i;
ctrl_dout_valid_reg <= '1';
ctrl_complete_reg <= cnti_end_i AND cntj_end_i;
-- RD/WR S
WHEN S12 =>
ctrl_dout_reg <= ds_i;
ctrl_dout_valid_reg <= '1';
ctrl_complete_reg <= cnti_end_i;
-- RD/WR Y
WHEN S22 =>
ctrl_dout_reg <= dy_i;
ctrl_dout_valid_reg <= '1';
ctrl_complete_reg <= cntj_end_i;
-- RD/WR BIAS
WHEN S32 =>
ctrl_dout_reg <= dbias_i;
ctrl_dout_valid_reg <= '1';
ctrl_complete_reg <= cntj_end_i;
-- RD/WR T
WHEN S42 =>
ctrl_dout_reg <= dt_i;
ctrl_dout_valid_reg <= '1';
ctrl_complete_reg <= cntj_end_i;
-- Dummy cycles to
-- equalize latency.
WHEN S03 =>
ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
ctrl_rd_vec_i,
ctrl_rdlat_reg,
ctrl_rdy7_i,
ctrl_start_reg,
ctrl_wrlat_reg,
current_state
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Wait for next
-- RD/WR.
WHEN S01 =>
IF (ctrl_start_reg = '1' AND
(ctrl_rd_vec_i( MEM_W_BITPOS ) = '1')) THEN
next_state <= S02;
ELSIF (ctrl_start_reg = '1' AND
(ctrl_rd_vec_i( MEM_S_BITPOS ) = '1')) THEN
next_state <= S12;
ELSIF (ctrl_start_reg = '1' AND
(ctrl_rd_vec_i( MEM_Y_BITPOS ) = '1')) THEN
next_state <= S22;
ELSIF (ctrl_start_reg = '1' AND
(ctrl_rd_vec_i( MEM_BIAS_BITPOS ) = '1')) THEN
next_state <= S32;
ELSIF (ctrl_start_reg = '1' AND
(ctrl_rd_vec_i( MEM_T_BITPOS ) = '1')) THEN
next_state <= S42;
ELSE
next_state <= S01;
END IF;
-- RD/WR W
WHEN S02 =>
next_state <= S03;
-- RD/WR S
WHEN S12 =>
next_state <= S03;
-- RD/WR Y
WHEN S22 =>
next_state <= S03;
-- RD/WR BIAS
WHEN S32 =>
next_state <= S03;
-- RD/WR T
WHEN S42 =>
next_state <= S03;
-- Dummy cycles to
-- equalize latency.
WHEN S03 =>
IF (unsigned ( ctrl_rdlat_reg ) <= 3 AND
unsigned ( ctrl_wrlat_reg ) <= 3) THEN
next_state <= S01;
ELSE
next_state <= S03;
END IF;
-- Reset state
WHEN S00 =>
IF (ctrl_rdy7_i = '1') THEN
next_state <= S01;
ELSE
next_state <= S00;
END IF;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
cnti_end_i,
ctrl_complete_reg,
ctrl_din_i,
ctrl_dout_reg,
ctrl_dout_valid_reg,
ctrl_wr_vec_i,
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnteni_o <= '0';
cntenj_o <= '0';
ctrl_complete_o <= ctrl_complete_reg;
ctrl_dout_o <= ctrl_dout_reg;
ctrl_dout_valid_o <= ctrl_dout_valid_reg;
ctrl_rdy_o <= '0';
dout_o <= (others => '0');
we_bias_o <= '0';
we_s_o <= '0';
we_t_o <= '0';
we_w_o <= '0';
we_y_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- Wait for next
-- RD/WR.
WHEN S01 =>
ctrl_rdy_o <= '1';
-- RD/WR W
WHEN S02 =>
cnteni_o <= '1';
cntenj_o <= cnti_end_i;
dout_o <= ctrl_din_i;
we_w_o <= ctrl_wr_vec_i( MEM_W_BITPOS );
-- RD/WR S
WHEN S12 =>
cnteni_o <= '1';
dout_o <= ctrl_din_i;
we_s_o <= ctrl_wr_vec_i( MEM_S_BITPOS );
-- RD/WR Y
WHEN S22 =>
cntenj_o <= '1';
dout_o <= ctrl_din_i;
we_y_o <= ctrl_wr_vec_i( MEM_Y_BITPOS );
-- RD/WR BIAS
WHEN S32 =>
cntenj_o <= '1';
dout_o <= ctrl_din_i;
we_bias_o <= ctrl_wr_vec_i( MEM_BIAS_BITPOS );
-- RD/WR T
WHEN S42 =>
cntenj_o <= '1';
dout_o <= ctrl_din_i;
we_t_o <= ctrl_wr_vec_i( MEM_T_BITPOS );
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00027_s_v01_train_fsm.vhd
0,0 → 1,308
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00027_s_v01_train_fsm IS
PORT(
clk_i : IN std_logic;
cnti_rdy_i : IN std_logic;
cntj_rdy_i : IN std_logic;
ctrl_clear_epoch_i : IN std_logic;
ctrl_maxepoch_i : IN WB_DATA_WIDTH_T;
ctrl_rdy1_i : IN std_logic;
ctrl_rdy2_i : IN std_logic;
ctrl_rdy7_i : IN std_logic;
ctrl_start_i : IN std_logic;
ctrl_wchgd_i : IN std_logic;
rst_n_i : IN std_logic;
ctrl_epoch_o : OUT WB_DATA_WIDTH_T;
ctrl_int_o : OUT std_logic;
ctrl_not_rdy_o : OUT std_logic;
ctrl_rdy_o : OUT std_logic;
ctrl_start1_o : OUT std_logic;
ctrl_start2_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00027_s_v01_train_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.0 2022/07/04
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00027_s_v01_train_fsm IS
 
-- Architecture Declarations
SIGNAL cnti_rdy_reg : std_logic;
SIGNAL cntj_rdy_reg : std_logic;
SIGNAL ctrl_clear_epoch_reg : std_logic;
SIGNAL ctrl_epoch_reg : WB_DATA_WIDTH_T;
SIGNAL ctrl_int_reg : std_logic;
SIGNAL ctrl_not_rdy_reg : std_logic;
SIGNAL ctrl_rdy1_reg : std_logic;
SIGNAL ctrl_rdy2_reg : std_logic;
SIGNAL ctrl_start_reg : std_logic;
 
TYPE STATE_TYPE IS (
S00,
S02,
S03,
S06,
S07,
S10,
S01,
S11,
S12,
S05,
S08,
S04,
S09,
S13
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
cnti_rdy_reg <= '0';
cntj_rdy_reg <= '0';
ctrl_clear_epoch_reg <= '0';
ctrl_epoch_reg <= (others => '0');
ctrl_int_reg <= '0';
ctrl_not_rdy_reg <= '0';
ctrl_rdy1_reg <= '0';
ctrl_rdy2_reg <= '0';
ctrl_start_reg <= '0';
ELSE
current_state <= next_state;
-- Default Assignment To Internals
cnti_rdy_reg <= cnti_rdy_i;
cntj_rdy_reg <= cntj_rdy_i;
ctrl_clear_epoch_reg <= ctrl_clear_epoch_i;
ctrl_epoch_reg <= ctrl_epoch_reg;
ctrl_int_reg <= '0';
ctrl_not_rdy_reg <= ctrl_not_rdy_reg;
ctrl_rdy1_reg <= ctrl_rdy1_i;
ctrl_rdy2_reg <= ctrl_rdy2_i;
ctrl_start_reg <= ctrl_start_i;
 
-- Combined Actions
CASE current_state IS
-- Clear NOT READY
-- register and test for
-- READY
WHEN S02 =>
ctrl_not_rdy_reg <= '0';
-- Set interrupt
-- flag
WHEN S11 =>
ctrl_int_reg <= '1';
-- Set NOT READY
-- register if modules
-- are NOT READY
WHEN S12 =>
ctrl_not_rdy_reg <= '1';
-- Dummy cycle
-- and update
-- EPOCH
WHEN S04 =>
ctrl_epoch_reg <= unsigned (ctrl_epoch_reg) + ctrl_wchgd_i;
-- Clear EPOCH
-- register
WHEN S13 =>
ctrl_epoch_reg <= (others => '0');
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnti_rdy_reg,
ctrl_clear_epoch_reg,
ctrl_epoch_reg,
ctrl_maxepoch_i,
ctrl_rdy1_reg,
ctrl_rdy2_reg,
ctrl_rdy7_i,
ctrl_start_reg,
ctrl_wchgd_i,
current_state
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Reset state
WHEN S00 =>
IF (ctrl_rdy7_i = '1') THEN
next_state <= S01;
ELSE
next_state <= S00;
END IF;
-- Clear NOT READY
-- register and test for
-- READY
WHEN S02 =>
IF (ctrl_rdy1_reg = '0' OR
ctrl_rdy2_reg = '0' OR
cnti_rdy_reg = '0') THEN
next_state <= S12;
ELSE
next_state <= S03;
END IF;
-- Start calculation
-- of Y
WHEN S03 =>
next_state <= S04;
-- Wait for CAL_Y
-- is ready
WHEN S06 =>
IF (ctrl_rdy1_reg = '1') THEN
next_state <= S07;
ELSE
next_state <= S06;
END IF;
-- Start calculation
-- of BIAS and W
WHEN S07 =>
next_state <= S08;
-- Loop again if
-- W was changed
WHEN S10 =>
IF (ctrl_rdy2_reg = '1' AND
ctrl_wchgd_i = '1' AND
( unsigned (ctrl_maxepoch_i) = 0 OR
unsigned (ctrl_maxepoch_i) >= unsigned (ctrl_epoch_reg) )) THEN
next_state <= S03;
ELSIF (ctrl_rdy2_reg = '1') THEN
next_state <= S11;
ELSE
next_state <= S10;
END IF;
-- Wait for next
-- training or clear
-- EPOCH register
WHEN S01 =>
IF (ctrl_start_reg = '1' AND
ctrl_clear_epoch_reg = '1') THEN
next_state <= S13;
ELSIF (ctrl_start_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S01;
END IF;
-- Set interrupt
-- flag
WHEN S11 =>
next_state <= S01;
-- Set NOT READY
-- register if modules
-- are NOT READY
WHEN S12 =>
next_state <= S01;
-- Dummy cycle
WHEN S05 =>
next_state <= S06;
-- Dummy cycle
WHEN S08 =>
next_state <= S09;
-- Dummy cycle
-- and update
-- EPOCH
WHEN S04 =>
next_state <= S05;
-- Dummy cycle
WHEN S09 =>
next_state <= S10;
-- Clear EPOCH
-- register
WHEN S13 =>
next_state <= S02;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
ctrl_epoch_reg,
ctrl_int_reg,
ctrl_not_rdy_reg,
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
ctrl_epoch_o <= ctrl_epoch_reg;
ctrl_int_o <= ctrl_int_reg;
ctrl_not_rdy_o <= ctrl_not_rdy_reg;
ctrl_rdy_o <= '0';
ctrl_start1_o <= '0';
ctrl_start2_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- Start calculation
-- of Y
WHEN S03 =>
ctrl_start1_o <= '1';
-- Start calculation
-- of BIAS and W
WHEN S07 =>
ctrl_start2_o <= '1';
-- Wait for next
-- training or clear
-- EPOCH register
WHEN S01 =>
ctrl_rdy_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00028_s_v02_latency_fsm.vhd
0,0 → 1,358
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00028_s_v02_latency_fsm IS
PORT(
clk_i : IN std_logic;
dw_i : IN DATA_T;
rst_n_i : IN std_logic;
cnt_alllat_o : OUT MEM_LAT_CNT_WIDTH_T;
cnteni_o : OUT std_logic;
cntenj_o : OUT std_logic;
ctrl_memerr_o : OUT std_logic;
ctrl_rdlat_o : OUT MEM_LAT_CNT_WIDTH_T;
ctrl_rdy_o : OUT std_logic;
ctrl_run_o : OUT std_logic;
ctrl_wrlat_o : OUT MEM_LAT_CNT_WIDTH_T;
dout_o : OUT DATA_T;
we_w_o : OUT std_logic
);
 
-- Declarations
 
END p0300_m00028_s_v02_latency_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 2.0 2022/07/04
-- - Introsuced latency for write
-- Revision 1.0 2022/07/02
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm OF p0300_m00028_s_v02_latency_fsm IS
 
-- Architecture Declarations
SIGNAL cnt_alllat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_memerr_reg : std_logic;
SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL ctrl_rdy_reg : std_logic;
SIGNAL ctrl_run_reg : std_logic;
SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
SIGNAL dw_reg : DATA_T;
 
TYPE STATE_TYPE IS (
S00,
S01,
S02,
S03,
S04,
S06,
S05,
S08,
SERR,
S07,
SRDY,
S11,
S7,
S8
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
cnt_alllat_reg <= (others => '0');
ctrl_memerr_reg <= '0';
ctrl_rdlat_reg <= (others => '0');
ctrl_rdy_reg <= '0';
ctrl_run_reg <= '0';
ctrl_wrlat_reg <= (others => '0');
dw_reg <= (others => '0');
ELSE
current_state <= next_state;
-- Default Assignment To Internals
cnt_alllat_reg <= cnt_alllat_reg;
ctrl_memerr_reg <= ctrl_memerr_reg;
ctrl_rdlat_reg <= ctrl_rdlat_reg;
ctrl_rdy_reg <= ctrl_rdy_reg;
ctrl_run_reg <= ctrl_run_reg;
ctrl_wrlat_reg <= ctrl_wrlat_reg;
dw_reg <= dw_i;
 
-- Combined Actions
CASE current_state IS
-- Reset state
WHEN S00 =>
ctrl_run_reg <= '1';
ctrl_rdy_reg <= '0';
-- Init values
WHEN S01 =>
ctrl_wrlat_reg <= (others => '0');
ctrl_memerr_reg <= '0';
-- Wait for max
-- latency
WHEN S03 =>
ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1';
-- Last address
-- [1][1]
WHEN S04 =>
ctrl_wrlat_reg <= (others => '0');
-- Write -1 to
-- last address
-- [1][1]
WHEN S06 =>
ctrl_wrlat_reg <= (others => '0');
-- Wait for max
-- latency
WHEN S05 =>
ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1';
-- Release END
-- conditions (for)
WHEN S08 =>
cnt_alllat_reg <= (others => '0');
ctrl_wrlat_reg <= (others => '0');
ctrl_rdlat_reg <= (others => '0');
-- Memory
-- ERROR
WHEN SERR =>
ctrl_memerr_reg <= '1';
ctrl_run_reg <= '0';
-- Wait for max
-- latency
WHEN S07 =>
ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1';
-- END / READY
-- state
WHEN SRDY =>
ctrl_rdy_reg <= '1';
ctrl_run_reg <= '0';
-- Address [0][0]
-- reaches memory
-- WS=1...max
WHEN S11 =>
cnt_alllat_reg <= unsigned (cnt_alllat_reg) + 1;
ctrl_rdlat_reg <= ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1';
IF (signed (dw_reg) = 0) THEN
cnt_alllat_reg <= cnt_alllat_reg;
ctrl_rdlat_reg <= ctrl_rdlat_reg;
END IF;
-- Wait for
-- dw_i = -1
WHEN S8 =>
ctrl_wrlat_reg <= ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH-2 downto 0 ) & '1';
IF (signed (dw_reg) = -1) THEN
ctrl_wrlat_reg <= ctrl_wrlat_reg;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
ctrl_rdlat_reg,
ctrl_wrlat_reg,
current_state,
dw_reg
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Reset state
WHEN S00 =>
next_state <= S01;
-- Init values
WHEN S01 =>
next_state <= S02;
-- Write 0 to
-- first address
-- [0][0]
WHEN S02 =>
next_state <= S03;
-- Wait for max
-- latency
WHEN S03 =>
IF (signed (ctrl_wrlat_reg) = -1) THEN
next_state <= S04;
ELSE
next_state <= S03;
END IF;
-- Last address
-- [1][1]
WHEN S04 =>
next_state <= S05;
-- Write -1 to
-- last address
-- [1][1]
WHEN S06 =>
next_state <= S07;
-- Wait for max
-- latency
WHEN S05 =>
IF (signed (ctrl_wrlat_reg) = -1) THEN
next_state <= S06;
ELSE
next_state <= S05;
END IF;
-- Release END
-- conditions (for)
WHEN S08 =>
IF (signed (dw_reg) = -1) THEN
next_state <= S11;
ELSE
-- -1 not read on dw
-- after max latency
-- time causes ERROR
next_state <= SERR;
END IF;
-- Memory
-- ERROR
WHEN SERR =>
next_state <= SERR;
-- Wait for max
-- latency
WHEN S07 =>
IF (signed (ctrl_wrlat_reg) = -1) THEN
next_state <= S08;
ELSE
next_state <= S07;
END IF;
-- END / READY
-- state
WHEN SRDY =>
next_state <= SRDY;
-- Address [0][0]
-- reaches memory
-- WS=1...max
WHEN S11 =>
IF (signed (dw_reg) = 0) THEN
next_state <= S7;
ELSIF (signed (ctrl_rdlat_reg) = -1) THEN
next_state <= SERR;
ELSE
next_state <= S11;
END IF;
-- Write -1 to
-- last address
-- [1][1]
WHEN S7 =>
next_state <= S8;
-- Wait for
-- dw_i = -1
WHEN S8 =>
IF (signed (dw_reg) = -1) THEN
next_state <= SRDY;
ELSIF (signed (ctrl_wrlat_reg) = -1) THEN
next_state <= SERR;
ELSE
next_state <= S8;
END IF;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
cnt_alllat_reg,
ctrl_memerr_reg,
ctrl_rdlat_reg,
ctrl_rdy_reg,
ctrl_run_reg,
ctrl_wrlat_reg,
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnt_alllat_o <= cnt_alllat_reg;
cnteni_o <= '0';
cntenj_o <= '0';
ctrl_memerr_o <= ctrl_memerr_reg;
ctrl_rdlat_o <= ctrl_rdlat_reg;
ctrl_rdy_o <= ctrl_rdy_reg;
ctrl_run_o <= ctrl_run_reg;
ctrl_wrlat_o <= ctrl_wrlat_reg;
dout_o <= (others => '0');
we_w_o <= '0';
 
-- Combined Actions
CASE current_state IS
-- Write 0 to
-- first address
-- [0][0]
WHEN S02 =>
dout_o <= (others => '0');
we_w_o <= '1';
-- Last address
-- [1][1]
WHEN S04 =>
cnteni_o <= '1';
cntenj_o <= '1';
-- Write -1 to
-- last address
-- [1][1]
WHEN S06 =>
dout_o <= (others => '1');
we_w_o <= '1';
-- Release END
-- conditions (for)
WHEN S08 =>
cnteni_o <= '1';
cntenj_o <= '1';
-- Write -1 to
-- last address
-- [1][1]
WHEN S7 =>
dout_o <= (others => '1');
we_w_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm;
/trunk/rtl/vhdl/p0300_m00033_s_v01_for_loop_memwi_fsm.vhd
0,0 → 1,252
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00033_s_v01_for_loop_memwi_fsm IS
PORT(
clk_i : IN std_logic;
cnten1_i : IN std_logic;
cnten2_i : IN std_logic;
cnten3_i : IN std_logic;
cnten4_i : IN std_logic;
cnten5_i : IN std_logic;
cnten7_i : IN std_logic;
rst_n_i : IN std_logic;
set_init_i : IN std_logic;
start_vali_i : IN ADDRESS_S_T;
stop_vali_i : IN ADDRESS_S_T;
cnt_end_o : OUT std_logic;
cnt_rdy_o : OUT std_logic;
cnt_val_o : OUT ADDRESS_S_T
);
 
-- Declarations
 
END p0300_m00033_s_v01_for_loop_memwi_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.0 2022/06/09
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm_behv OF p0300_m00033_s_v01_for_loop_memwi_fsm IS
 
-- Architecture Declarations
SIGNAL cnt_end_reg : std_logic;
SIGNAL cnt_reg : ADDRESS_S_T;
SIGNAL cnten_reg : std_logic;
SIGNAL set_init_reg : std_logic;
 
TYPE STATE_TYPE IS (
S01,
S02,
S03,
S06,
S04,
S05,
S00
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
cnt_end_reg <= '0';
cnt_reg <= (others => '0');
cnten_reg <= '0';
set_init_reg <= '0';
ELSE
current_state <= next_state;
-- Default Assignment To Internals
cnt_end_reg <= '0';
cnt_reg <= cnt_reg;
cnten_reg <= cnten1_i OR cnten2_i OR cnten3_i OR cnten4_i OR cnten5_i OR cnten7_i;
set_init_reg <= set_init_i;
 
-- Combined Actions
CASE current_state IS
-- Start loop
WHEN S01 =>
cnt_reg <= start_vali_i;
-- COUNT +
WHEN S02 =>
cnt_reg <= unsigned (cnt_reg) + 1;
IF (cnt_reg = unsigned (stop_vali_i) - 1 OR
set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
-- Wait for next
-- count enable.
WHEN S03 =>
IF (set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
-- COUNT -
WHEN S04 =>
cnt_reg <= unsigned (cnt_reg) - 1;
IF (cnt_reg = unsigned (stop_vali_i) + 1 OR
set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
-- Wait for next
-- count enable.
WHEN S05 =>
IF (set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnt_reg,
cnten_reg,
current_state,
set_init_reg,
start_vali_i,
stop_vali_i
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Start loop
WHEN S01 =>
IF (cnten_reg = '1' AND
unsigned (stop_vali_i) > unsigned (start_vali_i)) THEN
next_state <= S02;
ELSIF (cnten_reg = '1' AND
unsigned (stop_vali_i) < unsigned (start_vali_i)) THEN
next_state <= S04;
ELSE
next_state <= S01;
END IF;
-- COUNT +
WHEN S02 =>
IF (cnt_reg = unsigned (stop_vali_i) - 1 OR
set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '0') THEN
next_state <= S03;
ELSE
next_state <= S02;
END IF;
-- Wait for next
-- count enable.
WHEN S03 =>
IF (set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S03;
END IF;
-- End-of-count
-- or cancel.
WHEN S06 =>
IF (cnten_reg = '1' OR
set_init_reg = '1') THEN
next_state <= S01;
ELSE
next_state <= S06;
END IF;
-- COUNT -
WHEN S04 =>
IF (cnt_reg = unsigned (stop_vali_i) + 1 OR
set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '0') THEN
next_state <= S05;
ELSE
next_state <= S04;
END IF;
-- Wait for next
-- count enable.
WHEN S05 =>
IF (set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '1') THEN
next_state <= S04;
ELSE
next_state <= S05;
END IF;
-- Reset state
WHEN S00 =>
next_state <= S01;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
cnt_end_reg,
cnt_reg,
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnt_end_o <= cnt_end_reg;
cnt_rdy_o <= '0';
cnt_val_o <= cnt_reg;
 
-- Combined Actions
CASE current_state IS
-- Start loop
WHEN S01 =>
cnt_rdy_o <= '1';
-- End-of-count
-- or cancel.
WHEN S06 =>
cnt_end_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm_behv;
/trunk/rtl/vhdl/p0300_m00034_s_v01_for_loop_memwj_fsm.vhd
0,0 → 1,252
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00034_s_v01_for_loop_memwj_fsm IS
PORT(
clk_i : IN std_logic;
cnten1_i : IN std_logic;
cnten2_i : IN std_logic;
cnten3_i : IN std_logic;
cnten4_i : IN std_logic;
cnten5_i : IN std_logic;
cnten7_i : IN std_logic;
rst_n_i : IN std_logic;
set_init_i : IN std_logic;
start_valj_i : IN ADDRESS_T_T;
stop_valj_i : IN ADDRESS_T_T;
cnt_end_o : OUT std_logic;
cnt_rdy_o : OUT std_logic;
cnt_val_o : OUT ADDRESS_T_T
);
 
-- Declarations
 
END p0300_m00034_s_v01_for_loop_memwj_fsm ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.0 2022/06/09
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
ARCHITECTURE fsm_behv OF p0300_m00034_s_v01_for_loop_memwj_fsm IS
 
-- Architecture Declarations
SIGNAL cnt_end_reg : std_logic;
SIGNAL cnt_reg : ADDRESS_T_T;
SIGNAL cnten_reg : std_logic;
SIGNAL set_init_reg : std_logic;
 
TYPE STATE_TYPE IS (
S01,
S02,
S03,
S06,
S04,
S05,
S00
);
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
 
BEGIN
 
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_i
)
-----------------------------------------------------------------
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_n_i = '0') THEN
current_state <= S00;
-- Default Reset Values
cnt_end_reg <= '0';
cnt_reg <= (others => '0');
cnten_reg <= '0';
set_init_reg <= '0';
ELSE
current_state <= next_state;
-- Default Assignment To Internals
cnt_end_reg <= '0';
cnt_reg <= cnt_reg;
cnten_reg <= cnten1_i OR cnten2_i OR cnten3_i OR cnten4_i OR cnten5_i OR cnten7_i;
set_init_reg <= set_init_i;
 
-- Combined Actions
CASE current_state IS
-- Start loop
WHEN S01 =>
cnt_reg <= start_valj_i;
-- COUNT +
WHEN S02 =>
cnt_reg <= unsigned (cnt_reg) + 1;
IF (cnt_reg = unsigned (stop_valj_i) - 1 OR
set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
-- Wait for next
-- count enable.
WHEN S03 =>
IF (set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
-- COUNT -
WHEN S04 =>
cnt_reg <= unsigned (cnt_reg) - 1;
IF (cnt_reg = unsigned (stop_valj_i) + 1 OR
set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
-- Wait for next
-- count enable.
WHEN S05 =>
IF (set_init_reg = '1') THEN
cnt_end_reg <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
cnt_reg,
cnten_reg,
current_state,
set_init_reg,
start_valj_i,
stop_valj_i
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
-- Start loop
WHEN S01 =>
IF (cnten_reg = '1' AND
unsigned (stop_valj_i) > unsigned (start_valj_i)) THEN
next_state <= S02;
ELSIF (cnten_reg = '1' AND
unsigned (stop_valj_i) < unsigned (start_valj_i)) THEN
next_state <= S04;
ELSE
next_state <= S01;
END IF;
-- COUNT +
WHEN S02 =>
IF (cnt_reg = unsigned (stop_valj_i) - 1 OR
set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '0') THEN
next_state <= S03;
ELSE
next_state <= S02;
END IF;
-- Wait for next
-- count enable.
WHEN S03 =>
IF (set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '1') THEN
next_state <= S02;
ELSE
next_state <= S03;
END IF;
-- End-of-count
-- or cancel.
WHEN S06 =>
IF (cnten_reg = '1' OR
set_init_reg = '1') THEN
next_state <= S01;
ELSE
next_state <= S06;
END IF;
-- COUNT -
WHEN S04 =>
IF (cnt_reg = unsigned (stop_valj_i) + 1 OR
set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '0') THEN
next_state <= S05;
ELSE
next_state <= S04;
END IF;
-- Wait for next
-- count enable.
WHEN S05 =>
IF (set_init_reg = '1') THEN
next_state <= S06;
ELSIF (cnten_reg = '1') THEN
next_state <= S04;
ELSE
next_state <= S05;
END IF;
-- Reset state
WHEN S00 =>
next_state <= S01;
WHEN OTHERS =>
next_state <= S00;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
cnt_end_reg,
cnt_reg,
current_state
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
cnt_end_o <= cnt_end_reg;
cnt_rdy_o <= '0';
cnt_val_o <= cnt_reg;
 
-- Combined Actions
CASE current_state IS
-- Start loop
WHEN S01 =>
cnt_rdy_o <= '1';
-- End-of-count
-- or cancel.
WHEN S06 =>
cnt_end_o <= '1';
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
END fsm_behv;
/trunk/rtl/vhdl/p0300_m00100_s_v01_mem_gen_blk.vhd
0,0 → 1,185
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
ENTITY p0300_m00100_s_v01_mem_gen_blk IS
PORT(
addr_i_i : IN ADDRESS_S_T;
addr_j_i : IN ADDRESS_T_T;
clk_i : IN std_logic;
din1_i : IN DATA_T;
din2_i : IN DATA_T;
din3_i : IN DATA_T;
din4_i : IN DATA_T;
din5_i : IN DATA_T;
din7_i : IN DATA_T;
we_bias2_i : IN std_logic;
we_bias3_i : IN std_logic;
we_bias5_i : IN std_logic;
we_s3_i : IN std_logic;
we_s4_i : IN std_logic;
we_s5_i : IN std_logic;
we_t3_i : IN std_logic;
we_t4_i : IN std_logic;
we_t5_i : IN std_logic;
we_w2_i : IN std_logic;
we_w3_i : IN std_logic;
we_w4_i : IN std_logic;
we_w5_i : IN std_logic;
we_w7_i : IN std_logic;
we_y1_i : IN std_logic;
we_y3_i : IN std_logic;
we_y5_i : IN std_logic;
dbias_o : OUT DATA_T;
ds_o : OUT DATA_T;
dt_o : OUT DATA_T;
dw_o : OUT DATA_T;
dy_o : OUT DATA_T
);
 
-- Declarations
 
END p0300_m00100_s_v01_mem_gen_blk ;
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
-- VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- Versions:
-- Revision 1.0 2022/05/25
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.ALL;
 
 
ARCHITECTURE struct OF p0300_m00100_s_v01_mem_gen_blk IS
 
-- Architecture declarations
 
-- Internal signal declarations
SIGNAL addr_ij_oi : ADDRESS_W_T;
SIGNAL din_oi : DATA_T;
SIGNAL we_bias_oi : std_logic;
SIGNAL we_s_oi : std_logic;
SIGNAL we_t_oi : std_logic;
SIGNAL we_w_oi : std_logic;
SIGNAL we_y_oi : std_logic;
 
 
-- Component Declarations
COMPONENT p0300_m00101_m_v01_mem_t
PORT (
addr_i : IN ADDRESS_T_T;
clk_i : IN std_logic;
d_i : IN DATA_T;
we_i : IN std_logic;
d_o : OUT DATA_T
);
END COMPONENT;
COMPONENT p0300_m00102_s_v01_mem_w
PORT (
addr_i : IN ADDRESS_W_T;
clk_i : IN std_logic;
d_i : IN DATA_T;
we_i : IN std_logic;
d_o : OUT DATA_T
);
END COMPONENT;
COMPONENT p0300_m00103_s_v01_mem_s
PORT (
addr_i : IN ADDRESS_S_T;
clk_i : IN std_logic;
d_i : IN DATA_T;
we_i : IN std_logic;
d_o : OUT DATA_T
);
END COMPONENT;
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : p0300_m00101_m_v01_mem_t USE ENTITY work.p0300_m00101_m_v01_mem_t;
FOR ALL : p0300_m00102_s_v01_mem_w USE ENTITY work.p0300_m00102_s_v01_mem_w;
FOR ALL : p0300_m00103_s_v01_mem_s USE ENTITY work.p0300_m00103_s_v01_mem_s;
-- pragma synthesis_on
 
 
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
-- eb1 1
addr_ij_oi <= addr_j_i & addr_i_i;
we_s_oi <= we_s3_i OR we_s4_i OR we_s5_i;
we_t_oi <= we_t3_i OR we_t4_i OR we_t5_i;
we_w_oi <= we_w2_i OR we_w3_i OR we_w4_i OR we_w5_i OR we_w7_i;
we_y_oi <= we_y1_i OR we_y3_i OR we_y5_i;
we_bias_oi <= we_bias2_i OR we_bias3_i OR we_bias5_i;
din_oi <= din1_i OR din2_i OR din3_i OR din4_i OR din5_i OR din7_i;
 
 
-- Instance port mappings.
U_1 : p0300_m00101_m_v01_mem_t
PORT MAP (
clk_i => clk_i,
we_i => we_t_oi,
d_i => din_oi,
addr_i => addr_j_i,
d_o => dt_o
);
U_2 : p0300_m00101_m_v01_mem_t
PORT MAP (
clk_i => clk_i,
we_i => we_y_oi,
d_i => din_oi,
addr_i => addr_j_i,
d_o => dy_o
);
U_3 : p0300_m00101_m_v01_mem_t
PORT MAP (
clk_i => clk_i,
we_i => we_bias_oi,
d_i => din_oi,
addr_i => addr_j_i,
d_o => dbias_o
);
U_4 : p0300_m00102_s_v01_mem_w
PORT MAP (
clk_i => clk_i,
we_i => we_w_oi,
d_i => din_oi,
addr_i => addr_ij_oi,
d_o => dw_o
);
U_0 : p0300_m00103_s_v01_mem_s
PORT MAP (
clk_i => clk_i,
we_i => we_s_oi,
d_i => din_oi,
addr_i => addr_i_i,
d_o => ds_o
);
 
END struct;
/trunk/rtl/vhdl/p0300_m00101_m_v01_mem_t.vhd
0,0 → 1,69
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- Versions:
--
-- Revision 1.0 2022/06/12
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.all;
 
LIBRARY work;
 
entity p0300_m00101_m_v01_mem_t is
port(
clk_i : in std_logic; -- Single Clock Input
we_i : in std_logic; -- Write Enable Input
d_i : in DATA_T; -- Data Input
addr_i : in ADDRESS_T_T; -- Address Input
d_o : out DATA_T -- Data Output
);
end entity p0300_m00101_m_v01_mem_t;
 
--
architecture p0300_mem_t_arch of p0300_m00101_m_v01_mem_t is
 
signal addr_reg : ADDRESS_T_T; -- Address register
signal din_reg : DATA_T;
signal we_reg : std_logic;
signal t_ram : T_RAM_T; -- "t output" memory array
attribute logic_block : boolean;
attribute logic_block of t_ram : signal is true;
 
 
begin
 
mem_s_proc: process (clk_i)
begin
if (clk_i'event and clk_i='1') then
if (we_reg = '1') then
t_ram(CONV_INTEGER(unsigned(addr_i))) <= din_reg;
end if;
addr_reg <= addr_i;
din_reg <= d_i;
we_reg <= we_i;
end if;
end process mem_s_proc;
d_o <= t_ram(CONV_INTEGER(unsigned(addr_reg)));
 
end architecture p0300_mem_t_arch;
 
/trunk/rtl/vhdl/p0300_m00102_s_v01_mem_w.vhd
0,0 → 1,69
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- Versions:
--
-- Revision 1.0 2022/06/12
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.all;
 
LIBRARY work;
 
entity p0300_m00102_s_v01_mem_w is
port(
clk_i : in std_logic; -- Single Clock Input
we_i : in std_logic; -- Write Enable Input
d_i : in DATA_T; -- Data Input
addr_i : in ADDRESS_W_T; -- Address Input
d_o : out DATA_T -- Data Output
);
end entity p0300_m00102_s_v01_mem_w;
 
--
architecture p0300_mem_w_arch of p0300_m00102_s_v01_mem_w is
 
signal addr_reg : ADDRESS_W_T; -- Address register
signal din_reg : DATA_T;
signal we_reg : std_logic;
signal w_ram : W_RAM_T; -- w (weights) memory
attribute logic_block : boolean;
attribute logic_block of w_ram : signal is true;
 
 
begin
 
mem_s_proc: process (clk_i)
begin
if (clk_i'event and clk_i='1') then
if (we_reg = '1') then
w_ram(CONV_INTEGER(unsigned(addr_i))) <= din_reg;
end if;
addr_reg <= addr_i;
din_reg <= d_i;
we_reg <= we_i;
end if;
end process mem_s_proc;
d_o <= w_ram(CONV_INTEGER(unsigned(addr_reg)));
 
end architecture p0300_mem_w_arch;
 
/trunk/rtl/vhdl/p0300_m00103_s_v01_mem_s.vhd
0,0 → 1,69
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
-- (email: opencores@vivare-services.com)
--
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- Versions:
--
-- Revision 1.0 2022/06/12
-- -- First draft
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--USE ieee.numeric_std.all;
LIBRARY work;
USE work.memory_vhd_v03_pkg.all;
 
LIBRARY work;
 
entity p0300_m00103_s_v01_mem_s is
port(
clk_i : in std_logic; -- Single Clock Input
we_i : in std_logic; -- Write Enable Input
d_i : in DATA_T; -- Data Input
addr_i : in ADDRESS_S_T; -- Address Input
d_o : out DATA_T -- Data Output
);
end entity p0300_m00103_s_v01_mem_s;
 
--
architecture p0300_mem_s_arch of p0300_m00103_s_v01_mem_s is
 
signal addr_reg : ADDRESS_S_T; -- Address register
signal din_reg : DATA_T;
signal we_reg : std_logic;
signal s_ram : S_RAM_T; -- "s input" memory array
attribute logic_block : boolean;
attribute logic_block of s_ram : signal is true;
 
 
begin
 
mem_s_proc: process (clk_i)
begin
if (clk_i'event and clk_i='1') then
if (we_reg = '1') then
s_ram(CONV_INTEGER(unsigned(addr_i))) <= din_reg;
end if;
addr_reg <= addr_i;
din_reg <= d_i;
we_reg <= we_i;
end if;
end process mem_s_proc;
d_o <= s_ram(CONV_INTEGER(unsigned(addr_reg)));
 
end architecture p0300_mem_s_arch;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.