URL
https://opencores.org/ocsvn/next186/next186/trunk
Subversion Repositories next186
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- This comparison shows the changes necessary to convert path
/next186/trunk
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/Next186_CPU.v
52,7 → 52,8
// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN |
// |
// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item |
// 23Dec2012 - fixed DIV bug (exception on sign bit) |
// 23Dec2012 - fixed DIV bug (exception on sign bit) |
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug |
/////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
861,6 → 862,7
3'b100, 3'b101: begin // MUL, IMUL |
ISIZE = ISIZES; |
ALUOP = {4'b1000, REG[0]}; // BASEL = FETCH[0][1] = 1 |
WE[4] = 1'b1; // fix MUL/IMUL 8bit flags bug |
case(STAGE[1:0]) |
2'b00: begin // stage1, RA -> TMP16, RB (mem) -> FETCH |
MREQ = ~&MOD; |
869,14 → 871,14
DOSEL = 2'b11; |
IFETCH = 1'b0; |
end |
2'b01: begin // stage2, write AX |
WE[1:0] = 2'b11; |
2'b01: begin // stage2, write AX |
WE[1:0] = 2'b11; // flags, RASEL_HI, RASEL_LO |
RASEL = 3'b000; // AX |
MREQ = 1'b0; |
IFETCH = ~FETCH[0][0]; |
end |
2'b10: begin // stage 2, write DX |
WE = 5'b10011; |
WE[1:0] = 2'b11; // flags, RASEL_HI, RASEL_LO |
RASEL = 3'b010; // DX |
MREQ = 1'b0; |
end |