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  • This comparison shows the changes necessary to convert path 
    /npigrctrl/trunk/npi_vga_v1_00_b/data
    from Rev 2 to Rev 5
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Rev 2 → Rev 5

/npi_vga_v2_1_0.bbd
0,0 → 1,11
C_FAMILY C_NPI_DATA_WIDTH FILES
virtex4 32 fifo_v4_32.ngc
virtex4 64 fifo_v4_64.ngc
virtex5 32 fifo_v5_32.ngc
virtex5 64 fifo_v5_64.ngc
virtex5lx 32 fifo_v5_32.ngc
virtex5lx 64 fifo_v5_64.ngc
spartan3e 32 fifo_sp_32.ngc
spartan3e 64 fifo_sp_64.ngc
 
 
/npi_vga_v2_1_0.mui
0,0 → 1,84
<?xml version="1.0" encoding="ISO-8859-1"?>
 
<!--
########################################################################
##
## Copyright (c) 2005 Xilinx, Inc. All rights reserved.
##
########################################################################
-->
 
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!ENTITY C_DATA_BITS '
<widget id="C_DATA_BITS">
<key>C_DATA_BITS</key>
<label>Number of Data Bits in a Serial Frame</label>
<tip></tip>
</widget>
'>
<!ENTITY C_CLK_FREQ '
<widget id="C_CLK_FREQ">
<key>C_CLK_FREQ</key>
<label>OPB Clock Frequency </label>
<tip></tip>
<unit>Hz</unit>
</widget>
'>
<!ENTITY C_BAUDRATE '
<widget id="C_BAUDRATE">
<key>C_BAUDRATE</key>
<label>UART Lite Baud Rate </label>
<tip></tip>
</widget>
'>
<!ENTITY C_USE_PARITY '
<widget id="C_USE_PARITY">
<key>C_USE_PARITY</key>
<label>Use Parity </label>
<tip>Select parity or no parity</tip>
</widget>
'>
<!ENTITY C_ODD_PARITY '
<widget id="C_ODD_PARITY">
<key>C_ODD_PARITY</key>
<label>Parity Type </label>
<tip>Select odd or even parity</tip>
</widget>
'>
]>
 
<doc>
<view id="User">
<display>User</display>
<group id="All">
<display>All</display>
<item>&C_BAUDRATE;</item>
<item>&C_DATA_BITS;</item>
<item>&C_USE_PARITY;</item>
<item>&C_ODD_PARITY;</item>
</group>
</view>
<view id="System">
<display>System</display>
<group id="Addresses">
<display>Addresses</display>
<item>&C_BASEADDR;</item>
<item>&C_HIGHADDR;</item>
</group>
<group id="PLB">
<display>PLB</display>
<item>&C_SPLB_DWIDTH;</item>
<item>&C_SPLB_AWIDTH;</item>
<item>&C_SPLB_P2P;</item>
<item>&C_SPLB_MID_WIDTH;</item>
<item>&C_SPLB_NATIVE_DWIDTH;</item>
<item>&C_SPLB_NUM_MASTERS;</item>
<item>&C_SPLB_SUPPORT_BURSTS;</item>
<item>&C_SPLB_CLK_FREQ_HZ;</item>
</group>
<group id="Hidden">
<display>Hidden</display>
<item>&C_FAMILY;</item>
</group>
</view>
</doc>
/npi_vga_v2_1_0.pao
0,0 → 1,38
################################################################################
##
## Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
##
## mch_opb_ipif.pao
##
## Peripheral Analyze Order file
##
################################################################################
 
lib npi_vga_v1_00_b video_cfg vhdl
lib npi_vga_v1_00_b npi_eng vhdl
lib npi_vga_v1_00_b npi_vga vhdl
lib npi_vga_v1_00_b graphics vhdl
lib npi_vga_v1_00_b hsync_gen vhdl
lib npi_vga_v1_00_b vsync_gen vhdl
lib npi_vga_v1_00_b reclock vhdl
lib npi_vga_v1_00_b video_clk_gen vhdl
lib npi_vga_v1_00_b video_clk_gen_v4 vhdl
lib npi_vga_v1_00_b delay vhdl
lib npi_vga_v1_00_b fifo vhdl
lib npi_vga_v1_00_b video_ctrl vhdl
lib npi_vga_v1_00_b data_rgb vhdl
 
 
lib proc_common_v2_00_a proc_common_pkg vhdl
lib proc_common_v2_00_a ipif_pkg vhdl
lib proc_common_v2_00_a or_muxcy vhdl
lib proc_common_v2_00_a or_gate128 vhdl
lib proc_common_v2_00_a family_support vhdl
lib proc_common_v2_00_a pselect_f vhdl
lib proc_common_v2_00_a counter_f vhdl
lib plbv46_slave_single_v1_00_a plb_address_decoder vhdl
lib plbv46_slave_single_v1_00_a plb_slave_attachment vhdl
lib plbv46_slave_single_v1_00_a plbv46_slave_single vhdl
lib npi_vga_v1_00_b user_logic vhdl
lib npi_vga_v1_00_b plbbr vhdl
 
/npi_vga_v2_1_0.mpd
0,0 → 1,149
## Written by SaVa (c)DFC Design
 
BEGIN npi_vga
 
## Peripheral Options
OPTION RUN_NGCBUILD = TRUE
OPTION STYLE = MIX
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION DESC = npi_vga
OPTION LONG_DESC = Simple NPI VGA Controller
OPTION ARCH_SUPPORT_MAP = (virtex2p = DEVELOPMENT, virtex4 = DEVELOPMENT, spartan3a = DEVELOPMENT, spartan3e = DEVELOPMENT, virtex5fx = DEVELOPMENT, virtex5lx = DEVELOPMENT)
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION IPTYPE = PERIPHERAL
 
## Bus Interfaces
BUS_INTERFACE BUS = MPMC_PIM, BUS_STD = XIL_NPI, BUS_TYPE = INITIATOR
BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
 
## Generics for VHDL or Parameters for Verilog
PARAMETER C_VD_PIXEL_DEPTH = 6, DT = integer
 
 
PARAMETER C_NPI_BURST_SIZE = 128, DT = integer, range = (256, 128, 64, 32, 16, 8)
PARAMETER C_NPI_ADDR_WIDTH = 32, DT = INTEGER
PARAMETER C_NPI_DATA_WIDTH = 64, DT = integer, range = (64, 32)
PARAMETER C_NPI_BE_WIDTH = 8, DT = integer, range = (8, 4)
PARAMETER C_NPI_RDWDADDR_WIDTH = 4, DT = integer
 
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 1, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_FAMILY = virtex5, DT = STRING
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR, MIN_SIZE = 0x10000, ASSIGNMENT = REQUIRE
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR, ASSIGNMENT = REQUIRE
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM1_HIGHADDR, MIN_SIZE = 0x10000, ASSIGNMENT = REQUIRE
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM1_BASEADDR, ASSIGNMENT = REQUIRE
PARAMETER C_VD_ADDR = 0x00800000, DT = std_logic_vector
PARAMETER C_VD_STRIDE = 640, DT = integer
PARAMETER C_VD_WIDTH = 640, DT = integer
PARAMETER C_VD_HEIGHT = 480, DT = integer
PARAMETER C_VD_PIXEL_D = 32, DT = integer, range = (8, 16, 32)
PARAMETER C_VD_H_BP = 56, DT = integer
PARAMETER C_VD_H_FP = 16, DT = integer
PARAMETER C_VD_H_SYNC_W = 96, DT = integer
PARAMETER C_VD_H_POL = 0, DT = std_logic
PARAMETER C_VD_V_BP = 33, DT = integer
PARAMETER C_VD_V_FP = 10, DT = integer
PARAMETER C_VD_V_SYNC_W = 2, DT = integer
PARAMETER C_VD_V_POL = 0, DT = std_logic
 
## Ports
#
PORT NPI_Clk = "", DIR = I
PORT NPI_RST = "", DIR = I
PORT NPI_Addr = Addr, DIR = O, BUS = MPMC_PIM, VEC = [31:0]
PORT NPI_AddrReq = AddrReq, DIR = O, BUS = MPMC_PIM
PORT NPI_AddrAck = AddrAck, DIR = I, BUS = MPMC_PIM
PORT NPI_RNW = RNW, DIR = O, BUS = MPMC_PIM
PORT NPI_Size = Size, DIR = O, BUS = MPMC_PIM, VEC = [3:0]
PORT NPI_RdModWr = RdModWr, DIR = O, BUS = MPMC_PIM
PORT NPI_WrFIFO_Data = WrFIFO_Data, DIR = O, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH-1):0]
PORT NPI_WrFIFO_BE = WrFIFO_BE, DIR = O, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH/8-1):0]
PORT NPI_WrFIFO_Push = WrFIFO_Push, DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_Data = RdFIFO_Data, DIR = I, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH-1):0]
PORT NPI_RdFIFO_Pop = RdFIFO_Pop, DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_RdWdAddr = RdFIFO_RdWdAddr, DIR = I, BUS = MPMC_PIM, VEC = [3:0]
PORT NPI_WrFIFO_Empty = WrFIFO_Empty, DIR = I, BUS = MPMC_PIM
PORT NPI_WrFIFO_AlmostFull= WrFIFO_AlmostFull, DIR = I, BUS = MPMC_PIM
PORT NPI_WrFIFO_Flush = WrFIFO_Flush, DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_Empty = RdFIFO_Empty, DIR = I, BUS = MPMC_PIM
PORT NPI_RdFIFO_Flush = RdFIFO_Flush, DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_Latency = RDFIFO_Latency, DIR = I, BUS = MPMC_PIM, VEC = [1:0]
PORT NPI_InitDone = InitDone, DIR = I, BUS = MPMC_PIM
 
PORT VIDEO_CLK = "", DIR = I
PORT VIDEO_VSYNC = "", DIR = O
PORT VIDEO_HSYNC = "", DIR = O
PORT VIDEO_DE = "", DIR = O
PORT VIDEO_CLK_OUT = "", DIR = O
PORT VIDEO_R = "", DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]
PORT VIDEO_G = "", DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]
PORT VIDEO_B = "", DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]
 
PORT X1 = "", DIR = O
PORT X2 = "", DIR = O
PORT X3 = "", DIR = O
PORT X4 = "", DIR = O
PORT X5 = "", DIR = O
PORT X6 = "", DIR = O
PORT X7 = "", DIR = O
PORT X8 = "", DIR = O
PORT X9 = "", DIR = O
 
PORT X = "", DIR = O, VEC = [7 : 0]
 
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
 
 
 
END

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