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URL https://opencores.org/ocsvn/nysa_sata/nysa_sata/trunk

Subversion Repositories nysa_sata

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  • This comparison shows the changes necessary to convert path 
    /nysa_sata/trunk/rtl/transport
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/sata_transport_layer.v
66,6 → 66,7
input [15:0] h2d_sector_count,
 
//Device to Host Registers
output reg [7:0] d2h_fis,
output reg d2h_interrupt,
output reg d2h_notification,
output reg [3:0] d2h_port_mult,
100,7 → 101,7
input ll_write_strobe,
input ll_write_finished,
output [31:0] ll_write_data,
output [31:0] ll_write_size,
output [23:0] ll_write_size,
output ll_write_hold,
output ll_write_abort,
input ll_xmit_error,
136,9 → 137,9
 
//Registers/Wires
reg [3:0] fis_id_state;
reg [7:0] current_fis;
reg [3:0] state;
reg detect_fis;
reg [7:0] current_fis;
wire processing_fis;
 
//data direction
159,7 → 160,7
 
reg reg_write_start;
wire [31:0] reg_write_data;
wire [31:0] reg_write_size;
wire [23:0] reg_write_size;
reg reg_write_ready;
wire reg_write_hold;
wire reg_write_abort;
177,7 → 178,7
reg data_write_start;
wire data_write_strobe;
wire data_read_strobe;
wire [31:0] data_write_size;
wire [23:0] data_write_size;
wire [31:0] data_write_data;
wire data_write_hold;
wire data_write_abort;
185,8 → 186,10
reg data_read_ready;
reg send_data_fis_id;
 
reg ll_write_finished_en;
 
 
 
//Asnchronous Logic
assign lax_state = state;
assign transport_layer_ready = (state == IDLE) && link_layer_ready;
199,26 → 202,25
assign ll_write_start = (reg_write) ? reg_write_start : data_write_start;
assign ll_write_data = (reg_write) ? register_fis[register_fis_ptr] : data_write_data;
assign ll_write_size = (reg_write) ? reg_write_size : data_write_size;
assign ll_write_hold = (reg_write) ? 0 : data_write_hold;
assign ll_write_abort = (reg_write) ? 0 : data_write_abort;
assign cl_if_strobe = (reg_write) ? 0 : (!send_data_fis_id && data_write_strobe);
assign ll_write_hold = (reg_write) ? 1'b0 : data_write_hold;
assign ll_write_abort = (reg_write) ? 1'b0 : data_write_abort;
assign cl_if_strobe = (reg_write) ? 1'b0 : (!send_data_fis_id && data_write_strobe);
 
//Read Control
assign ll_read_ready = (reg_read) ? 1 : data_read_ready;
assign cl_of_strobe = (reg_read) ? 0 : ((state == READ_DATA) && data_read_strobe);
assign ll_read_ready = (reg_read) ? 1'b1 : data_read_ready;
assign cl_of_strobe = (reg_read) ? 1'b0 : ((state == READ_DATA) && data_read_strobe);
assign cl_of_data = ll_read_data;
 
//Data Register Write Control Signals
assign data_write_data = (send_data_fis_id) ? `FIS_DATA : cl_if_data;
assign data_write_data = (send_data_fis_id) ? {24'h000, `FIS_DATA} : cl_if_data;
//the first DWORD is the FIS ID
assign data_write_size = (cl_if_size + 1);
//assign data_write_size = cl_if_size;
assign data_write_size = cl_if_size + 24'h1;
//Add 1 to the size so that there is room for the FIS ID
assign data_write_strobe = ll_write_strobe;
assign data_read_strobe = ll_read_strobe;
assign data_write_hold = 0;
assign data_write_hold = 1'b0;
//There should never be a hold on the data becuase the CL will set it up
assign data_write_abort = 0;
assign data_write_abort = 1'b0;
assign read_crc_error = !ll_read_crc_ok;
 
 
225,8 → 227,8
//H2D Register Write control signals
assign reg_write_strobe = ll_write_strobe;
assign reg_write_size = `FIS_H2D_REG_SIZE;
assign reg_write_hold = 0;
assign reg_write_abort = 0;
assign reg_write_hold = 1'b0;
assign reg_write_abort = 1'b0;
assign reg_write = (state == WRITE_H2D_REG) || (send_command_stb || send_control_stb);
 
//D2H Register Read control signals
258,41 → 260,43
//FIS ID State machine
always @ (posedge clk) begin
if (rst) begin
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
fis_id_state <= IDLE;
detect_fis <= 0;
current_fis <= 0;
d2h_fis <= 0;
end
else begin
//in order to set all the detect_* high when the actual fis is detected send this strobe
if(ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
current_fis <= 0;
fis_id_state <= IDLE;
end
else begin
case (fis_id_state)
IDLE: begin
current_fis <= 0;
detect_fis <= 0;
current_fis <= 0;
detect_fis <= 0;
if (ll_read_start) begin
detect_fis <= 1;
fis_id_state <= READ_FIS;
detect_fis <= 1;
fis_id_state <= READ_FIS;
end
end
READ_FIS: begin
if (ll_read_strobe) begin
detect_fis <= 0;
detect_fis <= 0;
current_fis <= ll_read_data[7:0];
d2h_fis <= ll_read_data[7:0];
fis_id_state <= WAIT_FOR_END;
end
end
WAIT_FOR_END: begin
if (ll_read_finished) begin
current_fis <= 0;
fis_id_state <= IDLE;
current_fis <= 0;
fis_id_state <= IDLE;
end
end
default: begin
fis_id_state <= IDLE;
fis_id_state <= IDLE;
end
endcase
end
347,11 → 351,12
 
data_write_start <= 0;
 
ll_write_finished_en <= 0;
end
else begin
//Strobed signals
if (phy_ready) begin
//only deassert a link layer strobe when Phy is ready
//only deassert a link layer strobe when Phy is ready and not sending aligns
data_write_start <= 0;
reg_write_start <= 0;
end
388,11 → 393,16
cl_if_activate <= 1;
end
 
if (ll_write_finished) begin
ll_write_finished_en <= 1;
end
 
case (state)
IDLE: begin
register_fis_ptr <= 0;
reg_read_count <= 0;
cmd_bit <= 0;
ll_write_finished_en <= 0;
//Detect a FIS
if(ll_read_start) begin
//detect the start of a frame
424,13 → 434,13
CHECK_FIS_TYPE: begin
if (detect_dma_setup) begin
//XXX: Future work!
reg_read_count <= reg_read_count + 1;
reg_read_count <= reg_read_count + 8'h1;
state <= IDLE;
end
else if (detect_dma_activate) begin
//hard drive is ready to receive data
state <= DMA_ACTIVATE;
reg_read_count <= reg_read_count + 1;
reg_read_count <= reg_read_count + 8'h1;
//state <= IDLE;
end
else if (detect_d2h_data) begin
445,7 → 455,7
d2h_port_mult <= ll_read_data[11:8];
 
state <= READ_D2H_REG;
reg_read_count <= reg_read_count + 1;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_pio_setup) begin
//store the error, status, direction interrupt from this read
458,7 → 468,7
d2h_port_mult <= ll_read_data[11:8];
 
state <= READ_PIO_SETUP;
reg_read_count <= reg_read_count + 1;
reg_read_count <= reg_read_count + 8'h1;
end
else if (detect_set_device_bits) begin
//store the error, a subset of the status bit and the interrupt
480,10 → 490,10
WRITE_H2D_REG: begin
if (register_fis_ptr < `FIS_H2D_REG_SIZE) begin
if (reg_write_strobe) begin
register_fis_ptr <= register_fis_ptr + 1;
register_fis_ptr <= register_fis_ptr + 8'h1;
end
end
if (ll_write_finished) begin
if (ll_write_finished_en) begin
if (ll_xmit_error) begin
state <= RETRY;
end
494,6 → 504,7
end
RETRY: begin
if (link_layer_ready) begin
ll_write_finished_en <= 0;
reg_write_start <= 1;
register_fis_ptr <= 0;
state <= WRITE_H2D_REG;
517,7 → 528,7
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 1;
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
d2h_reg_stb <= 1;
544,7 → 555,7
end
endcase
if (reg_read_stb) begin
reg_read_count <= reg_read_count + 1;
reg_read_count <= reg_read_count + 8'h1;
end
if (ll_read_finished) begin
pio_setup_stb <= 1;
563,7 → 574,7
if (ll_write_strobe && send_data_fis_id) begin
send_data_fis_id <= 0;
end
if (ll_write_finished) begin
if (ll_write_finished_en) begin
cl_if_activate <= 0;
state <= IDLE;
if (pio_response) begin

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