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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

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  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk/rtl/lib
    from Rev 10 to Rev 36
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Rev 10 → Rev 36

/wb_crossbar.v
14,9 → 14,14
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Nov 26, 2016 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// Revision : Nov 26, 2016
//// v-0.0 - Dinesh.A, Nov 26, 2016
//// 1. Initial Version
//// v-0.1 - Dinesh.A, Jan 19, 2017
//// 1. Lint warning fixes, Seperated resetable and non
// resetable logic
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
253,7 → 258,6
reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0];
reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0];
 
reg [TAR_WD-1 :0] cur_target_id;
wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master
wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master
reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master
271,7 → 275,7
reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master
reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master
 
integer i,k,l;
integer i,k,l,n;
 
/**********************************************************
357,30 → 361,39
slave_busy <= 0;
end else begin
for(i = 0; i < WB_MASTER; i = i + 1) begin
cur_target_id = wbd_taddr_master_t[i];
if(master_busy[i] == 0) begin
if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
master_mx_id[i] <= wbd_taddr_master_t[i];
slave_mx_id [wbd_taddr_master_t[i]] <= i;
slave_busy[wbd_taddr_master_t[i]] <= 1;
master_busy[i] <= 1;
end
end else if(wbd_cyc_master[i] == 0) begin
master_busy[i] <= 0;
slave_busy[wbd_taddr_master_t[i]] <= 0;
end
end
end
end
 
// Seperated non resetable two dimensional reg
always @(posedge clk) begin
for(n = 0; n < WB_MASTER; n = n + 1) begin
if(master_busy[n] == 0) begin
if(wbd_stb_master[n] & slave_busy[wbd_taddr_master_t[n]] == 0) begin
master_mx_id[n] <= wbd_taddr_master_t[n];
slave_mx_id [wbd_taddr_master_t[n]] <= n;
// synopsys translate_off
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
// $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
// synopsys translate_on
end
end else if(wbd_cyc_master[i] == 0) begin
if(master_busy[i] == 1) begin
end else if(wbd_cyc_master[n] == 0) begin
if(master_busy[n] == 1) begin
// synopsys translate_off
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[i]);
// $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
// synopsys translate_on
end
master_busy[i] <= 0;
slave_busy[wbd_taddr_master_t[i]] <= 0;
end
end
end
end
 
 
 
endmodule
/wb_rd_mem2mem.v
236,6 → 236,7
mem_din <= 0;
tWrData <= 0;
mem_wr <= 0;
cnt <= 0;
end
else begin
case(state)
341,6 → 342,7
mem_wr <= 0;
end
end
default: state <= IDLE;
endcase
end
end

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