OpenCores
URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk/rtl/spi
    from Rev 2 to Rev 11
    ↔ Reverse comparison
  •

Rev 2 → Rev 11

/spi_cfg.v
99,11 → 99,11
input reg_cs ;
input reg_wr ;
input [3:0] reg_addr ;
input [31:0] reg_wdata ;
input [3:0] reg_be ;
input [7:0] reg_wdata ;
input reg_be ;
 
// Outputs
output [31:0] reg_rdata ;
output [7:0] reg_rdata ;
output reg_ack ;
 
 
115,28 → 115,17
wire sw_rd_en;
wire sw_wr_en;
wire [3:0] sw_addr ; // addressing 16 registers
wire [3:0] wr_be ;
wire wr_be ;
 
reg [31:0] reg_rdata ;
reg reg_ack ;
reg [7:0] reg_rdata;
reg reg_ack ;
 
wire [31:0] reg_0; // Software_Reg_0
wire [31:0] reg_1; // Software-Reg_1
wire [31:0] reg_2; // Software-Reg_2
wire [31:0] reg_3; // Software-Reg_3
wire [31:0] reg_4; // Software-Reg_4
wire [31:0] reg_5; // Software-Reg_5
wire [31:0] reg_6; // Software-Reg_6
wire [31:0] reg_7; // Software-Reg_7
wire [31:0] reg_8; // Software-Reg_8
wire [31:0] reg_9; // Software-Reg_9
wire [31:0] reg_10; // Software-Reg_10
wire [31:0] reg_11; // Software-Reg_11
wire [31:0] reg_12; // Software-Reg_12
wire [31:0] reg_13; // Software-Reg_13
wire [31:0] reg_14; // Software-Reg_14
wire [31:0] reg_15; // Software-Reg_15
reg [31:0] reg_out;
wire [31:0] spi_ctrl; // Software-Reg_12
wire [7:0] reg_12; // Software-Reg_12
wire [7:0] reg_13; // Software-Reg_13
wire [7:0] reg_14; // Software-Reg_14
wire [7:0] reg_15; // Software-Reg_15
reg [7:0] reg_out;
 
//-----------------------------------------------------------------------
// Main code starts here
159,12 → 148,12
begin : preg_out_Seq
if (reset_n == 1'b0)
begin
reg_rdata [31:0] <= 32'h0000_0000;
reg_rdata [7:0] <= 8'h00;
reg_ack <= 1'b0;
end
else if (sw_rd_en && !reg_ack)
begin
reg_rdata [31:0] <= reg_out [31:0];
reg_rdata [7:0] <= reg_out [7:0];
reg_ack <= 1'b1;
end
else if (sw_wr_en && !reg_ack)
216,25 → 205,25
always @( *)
begin : preg_sel_Com
 
reg_out [31:0] = 32'd0;
reg_out [7:0] = 8'd0;
 
case (sw_addr [3:0])
4'b0000 : reg_out [31:0] = reg_0 [31:0];
4'b0001 : reg_out [31:0] = reg_1 [31:0];
4'b0010 : reg_out [31:0] = reg_2 [31:0];
4'b0011 : reg_out [31:0] = reg_3 [31:0];
4'b0100 : reg_out [31:0] = reg_4 [31:0];
4'b0101 : reg_out [31:0] = reg_5 [31:0];
4'b0110 : reg_out [31:0] = reg_6 [31:0];
4'b0111 : reg_out [31:0] = reg_7 [31:0];
4'b1000 : reg_out [31:0] = reg_8 [31:0];
4'b1001 : reg_out [31:0] = reg_9 [31:0];
4'b1010 : reg_out [31:0] = reg_10 [31:0];
4'b1011 : reg_out [31:0] = reg_11 [31:0];
4'b1100 : reg_out [31:0] = reg_12 [31:0];
4'b1101 : reg_out [31:0] = reg_13 [31:0];
4'b1110 : reg_out [31:0] = reg_14 [31:0];
4'b1111 : reg_out [31:0] = reg_15 [31:0];
4'b0000 : reg_out [7:0] = spi_ctrl [7:0];
4'b0001 : reg_out [7:0] = spi_ctrl [15:8];
4'b0010 : reg_out [7:0] = spi_ctrl [23:16];
4'b0011 : reg_out [7:0] = spi_ctrl [31:24];
4'b0100 : reg_out [7:0] = cfg_datain [7:0];
4'b0101 : reg_out [7:0] = cfg_datain [15:8];
4'b0110 : reg_out [7:0] = cfg_datain [23:16];
4'b0111 : reg_out [7:0] = cfg_datain [31:24];
4'b1000 : reg_out [7:0] = cfg_dataout [7:0];
4'b1001 : reg_out [7:0] = cfg_dataout [15:8];
4'b1010 : reg_out [7:0] = cfg_dataout [23:16];
4'b1011 : reg_out [7:0] = cfg_dataout [31:24];
4'b1100 : reg_out [7:0] = reg_12 [7:0];
4'b1101 : reg_out [7:0] = reg_13 [7:0];
4'b1110 : reg_out [7:0] = reg_14 [7:0];
4'b1111 : reg_out [7:0] = reg_15 [7:0];
endcase
end
 
245,59 → 234,56
//-----------------------------------------------------------------------
// Logic for Register 0 : SPI Control Register
//-----------------------------------------------------------------------
wire cfg_op_req = reg_0[31]; // cpu request
wire [1:0] cfg_tgt_sel = reg_0[24:23]; // target chip select
wire [1:0] cfg_op_type = reg_0[22:21]; // SPI operation type
wire [1:0] cfg_transfer_size = reg_0[20:19]; // SPI transfer size
wire [5:0] cfg_sck_period = reg_0[18:13]; // sck clock period
wire [4:0] cfg_sck_cs_period = reg_0[12:8]; // cs setup/hold period
wire [7:0] cfg_cs_byte = reg_0[7:0]; // cs bit information
wire cfg_op_req = spi_ctrl[31]; // cpu request
wire [1:0] cfg_tgt_sel = spi_ctrl[24:23]; // target chip select
wire [1:0] cfg_op_type = spi_ctrl[22:21]; // SPI operation type
wire [1:0] cfg_transfer_size = spi_ctrl[20:19]; // SPI transfer size
wire [5:0] cfg_sck_period = spi_ctrl[18:13]; // sck clock period
wire [4:0] cfg_sck_cs_period = spi_ctrl[12:8]; // cs setup/hold period
wire [7:0] cfg_cs_byte = spi_ctrl[7:0]; // cs bit information
 
 
generic_register #(8,0 ) u_spi_ctrl_be0 (
.we ({8{sw_wr_en_0 &
wr_be[0] }} ),
.we ({8{sw_wr_en_0 & wr_be }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_0[7:0] )
.data_out (spi_ctrl[7:0] )
);
 
generic_register #(8,0 ) u_spi_ctrl_be1 (
.we ({8{sw_wr_en_0 &
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
.we ({8{sw_wr_en_1 & wr_be }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_0[15:8] )
.data_out (spi_ctrl[15:8] )
);
 
generic_register #(8,0 ) u_spi_ctrl_be2 (
.we ({8{sw_wr_en_0 &
wr_be[2] }} ),
.data_in (reg_wdata[23:16] ),
.we ({8{sw_wr_en_2 & wr_be}} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_0[23:16] )
.data_out (spi_ctrl[23:16] )
);
 
assign reg_0[30:24] = 7'h0;
assign spi_ctrl[30:24] = 7'h0;
 
req_register #(0 ) u_spi_ctrl_req (
.cpu_we ({sw_wr_en_0 &
wr_be[3] } ),
.cpu_req (reg_wdata[31] ),
.cpu_we ({sw_wr_en_3 & wr_be}),
.cpu_req (reg_wdata[7] ),
.hware_ack (hware_op_done ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_0[31] )
.data_out (spi_ctrl[31] )
);
 
 
306,56 → 292,51
//-----------------------------------------------------------------------
// Logic for Register 1 : SPI Data In Register
//-----------------------------------------------------------------------
wire [31:0] cfg_datain = reg_1[31:0];
 
generic_register #(8,0 ) u_spi_din_be0 (
.we ({8{sw_wr_en_1 &
wr_be[0] }} ),
.we ({8{sw_wr_en_4 & wr_be }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_1[7:0] )
.data_out (cfg_datain[7:0] )
);
 
generic_register #(8,0 ) u_spi_din_be1 (
.we ({8{sw_wr_en_1 &
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
.we ({8{sw_wr_en_5 & wr_be }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_1[15:8] )
.data_out (cfg_datain[15:8] )
);
 
generic_register #(8,0 ) u_spi_din_be2 (
.we ({8{sw_wr_en_1 &
wr_be[2] }} ),
.data_in (reg_wdata[23:16] ),
.we ({8{sw_wr_en_6 & wr_be }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_1[23:16] )
.data_out (cfg_datain[23:16] )
);
 
 
generic_register #(8,0 ) u_spi_din_be3 (
.we ({8{sw_wr_en_1 &
wr_be[3] }} ),
.data_in (reg_wdata[31:24] ),
.we ({8{sw_wr_en_7 & wr_be }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
.data_out (reg_1[31:24] )
.data_out (cfg_datain[31:24] )
);
 
 
//-----------------------------------------------------------------------
// Logic for Register 2 : SPI Data output Register
// Logic for Register : SPI Data output Register
//-----------------------------------------------------------------------
assign reg_2 = cfg_dataout;
 
/spi_core.v
44,27 → 44,28
//////////////////////////////////////////////////////////////////////
module spi_core (
 
clk,
reset_n,
clk ,
reset_n ,
// Reg Bus Interface Signal
reg_cs,
reg_wr,
reg_addr,
reg_wdata,
reg_be,
reg_cs ,
reg_wr ,
reg_addr ,
reg_wdata ,
reg_be ,
 
// Outputs
reg_rdata,
reg_ack,
reg_rdata ,
reg_ack ,
 
// line interface
sck ,
so ,
si ,
sck ,
so ,
si ,
cs_n
);
 
);
 
input clk ;
input reset_n ;
76,11 → 77,11
input reg_cs ;
input reg_wr ;
input [3:0] reg_addr ;
input [31:0] reg_wdata ;
input [3:0] reg_be ;
input [7:0] reg_wdata ;
input reg_be ;
 
// Outputs
output [31:0] reg_rdata ;
output [7:0] reg_rdata ;
output reg_ack ;
 
//-------------------------------------------
112,8 → 113,7
wire [31:0] cfg_dataout ; // data for received
wire hware_op_done ; // operation done
 
spi_if u_spi_if
(
spi_if u_spi_if (
. clk (clk ),
. reset_n (reset_n ),
 
133,6 → 133,7
. so (so ),
. si (si ),
. cs_n (cs_n )
 
);
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.