OpenCores
URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /oms8051mini/trunk/verif/glog/modelsim
    from Rev 5 to Rev 9
    ↔ Reverse comparison
  •

Rev 5 → Rev 9

/complie.log
0,0 → 1,76
+ +Model Technology ModelSim ACTEL vlog 10.1b Compiler 2012.04 Apr 27 2012 +-- Compiling module tb_top +-- Compiling module tb_glbl +-- Compiling module uart_agent +-- Compiling module AT45DB321 +-- Compiling module acdc_check +-- Compiling module internal_logic +-- Compiling module memory_access +-- Compiling module m25p20 +-- Compiling module oc8051_xram +-- Compiling module oc8051_xrom +-- Compiling module digital_core +-- Compiling module g_dpath_ctrl +-- Compiling module spi_core +-- Compiling module spi_ctl +-- Compiling module spi_if +-- Compiling module spi_cfg +-- Compiling module uart_rxfsm +-- Compiling module uart_txfsm +-- Compiling module uart_core +-- Compiling module uart_cfg +-- Compiling module clkgen +-- Compiling module clk_ctl +-- Compiling module wb_crossbar +-- Compiling module wb_rd_mem2mem +-- Compiling module wb_wr_mem2mem +-- Compiling module oc8051_top +-- Compiling module oc8051_rom +-- Compiling module oc8051_alu_src_sel +-- Compiling module oc8051_alu +-- Compiling module oc8051_decoder +-- Compiling module oc8051_divide +-- Compiling module oc8051_multiply +-- Compiling module oc8051_memory_interface +-- Compiling module oc8051_ram_top +-- Compiling module oc8051_acc +-- Compiling module oc8051_comp +-- Compiling module oc8051_sp +-- Compiling module oc8051_dptr +-- Compiling module oc8051_cy_select +-- Compiling module oc8051_psw +-- Compiling module oc8051_indi_addr +-- Compiling module oc8051_ports +-- Compiling module oc8051_b_register +-- Compiling module oc8051_uart +-- Compiling module oc8051_int +-- Compiling module oc8051_tc +-- Compiling module oc8051_tc2 +-- Compiling module oc8051_sfr +-- Compiling module oc8051_ram_256x8_two_bist +-- Scanning library file '../../rtl/lib/registers.v' +-- Compiling module req_register +-- Compiling module stat_register +-- Compiling module generic_register +-- Scanning library file '../../rtl/lib/stat_counter.v' +-- Scanning library file '../../rtl/lib/toggle_sync.v' +-- Scanning library file '../../rtl/lib/double_sync_low.v' +-- Compiling module double_sync_low +-- Scanning library file '../../rtl/lib/async_fifo.v' +-- Compiling module async_fifo +-- Scanning library file '../../rtl/lib/registers.v' +-- Compiling module bit_register +-- Scanning library file '../../rtl/lib/stat_counter.v' +-- Scanning library file '../../rtl/lib/toggle_sync.v' +-- Scanning library file '../../rtl/lib/double_sync_low.v' +-- Scanning library file '../../rtl/lib/async_fifo.v' + +Top level modules: + tb_top + g_dpath_ctrl + wb_rd_mem2mem + wb_wr_mem2mem + oc8051_rom + oc8051_uart
/ext_cast.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 65
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/ext_divmul.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/ext_fib.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 01
# i : 51
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/ext_gcd.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/ext_sort.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 01
# i : 1f
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/ext_xram.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +EXTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/int_cast.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 65
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/int_divmul.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/int_fib.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 01
# i : 51
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/int_gcd.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/int_sort.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 01
# i : 1f
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/int_xram.log
0,0 → 1,110
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
################################
# TEST STATUS : PASSED
################################
/spi_test_1.log
0,0 → 1,476
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +spi_test_1 +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
############################################
# Testing ST Flash Read/Write Access
############################################
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201
# 6775 : tb_top.spi_sector_errase : Sending Sector Errase for Address : 000000
# NOTE : Sector erase cycle has begun
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
# NOTE : Only a Read Status Register instruction will be valid
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 03000000
# NOTE : Sector erase cycle is finished
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 00000000
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 02000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 00010203
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 00010203
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 04050607
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 04050607
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 08090a0b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 08090a0b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 0c0d0e0f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 0c0d0e0f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 10111213
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 10111213
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 14151617
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 14151617
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 18191a1b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 18191a1b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 1c1d1e1f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 1c1d1e1f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 20212223
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 20212223
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 24252627
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 24252627
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 28292a2b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 28292a2b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 2c2d2e2f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 2c2d2e2f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 30313233
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 30313233
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 34353637
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 34353637
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 38393a3b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 38393a3b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 3c3d3e3f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 3c3d3e3f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 40414243
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 40414243
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 44454647
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 44454647
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 48494a4b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 48494a4b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 4c4d4e4f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 4c4d4e4f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 50515253
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 50515253
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 54555657
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 54555657
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 58595a5b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 58595a5b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 5c5d5e5f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 5c5d5e5f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 60616263
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 60616263
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 64656667
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 64656667
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 68696a6b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 68696a6b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 6c6d6e6f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 6c6d6e6f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 70717273
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 70717273
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 74757677
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 74757677
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 78797a7b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 78797a7b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 7c7d7e7f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 7c7d7e7f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 80818283
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 80818283
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 84858687
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 84858687
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 88898a8b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 88898a8b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 8c8d8e8f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 8c8d8e8f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 90919293
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 90919293
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 94959697
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 94959697
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 98999a9b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 98999a9b
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 9c9d9e9f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : 9c9d9e9f
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a0a1a2a3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : a0a1a2a3
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a4a5a6a7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : a4a5a6a7
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = a8a9aaab
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : a8a9aaab
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = acadaeaf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : acadaeaf
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b0b1b2b3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : b0b1b2b3
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b4b5b6b7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : b4b5b6b7
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = b8b9babb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : b8b9babb
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = bcbdbebf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : bcbdbebf
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c0c1c2c3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : c0c1c2c3
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c4c5c6c7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : c4c5c6c7
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = c8c9cacb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : c8c9cacb
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = cccdcecf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : cccdcecf
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d0d1d2d3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : d0d1d2d3
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d4d5d6d7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : d4d5d6d7
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8d9dadb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : d8d9dadb
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = dcdddedf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : dcdddedf
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e0e1e2e3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : e0e1e2e3
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e4e5e6e7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : e4e5e6e7
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = e8e9eaeb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : e8e9eaeb
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = ecedeeef
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : ecedeeef
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f0f1f2f3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : f0f1f2f3
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f4f5f6f7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : f4f5f6f7
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = f8f9fafb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# tb_top.spi_page_write : Writing Data : f8f9fafb
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = fcfdfeff
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201
# NOTE : Page program cycle is started
# tb_top.spi_page_write : Writing Data : fcfdfeff
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
# NOTE : Only a Read Status Register instruction will be valid
# NOTE : Page program cycle is finished
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
# Total time Elapsed: 0(us): tb_top.spi_wait_busy : Checking the SPI RDStatus : 00000000
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 03000000
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0200
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 00010203
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 04050607
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 08090a0b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 0c0d0e0f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 10111213
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 14151617
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 18191a1b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 1c1d1e1f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 20212223
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 24252627
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 28292a2b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 2c2d2e2f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 30313233
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 34353637
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 38393a3b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 3c3d3e3f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 40414243
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 44454647
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 48494a4b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 4c4d4e4f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 50515253
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 54555657
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 58595a5b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 5c5d5e5f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 60616263
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 64656667
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 68696a6b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 6c6d6e6f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 70717273
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 74757677
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 78797a7b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 7c7d7e7f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 80818283
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 84858687
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 88898a8b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 8c8d8e8f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 90919293
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 94959697
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 98999a9b
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : 9c9d9e9f
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : a0a1a2a3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : a4a5a6a7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : a8a9aaab
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : acadaeaf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : b0b1b2b3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : b4b5b6b7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : b8b9babb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : bcbdbebf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : c0c1c2c3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : c4c5c6c7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : c8c9cacb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : cccdcecf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : d0d1d2d3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : d4d5d6d7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : d8d9dadb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : dcdddedf
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : e0e1e2e3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : e4e5e6e7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : e8e9eaeb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : ecedeeef
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : f0f1f2f3
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : f4f5f6f7
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : f8f9fafb
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 803a0200
# tb_top.spi_page_read_verify : STATUS : Data Matched : fcfdfeff
#############################
# Test Statistic
# TEST STATUS : PASSED
#############################
#
# -------------------------------------------------
# Test Status
# warnings: 0, errors: 0
#
# -------------------------------------------------
# Test Status
# warnings: 0, errors: 0
#
# =========
# Test Status: TEST PASSED
# =========
#
/uart_test_1.log
0,0 → 1,379
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
# 10.1b
 
# vsim +uart_test_1 +INTERNAL_ROM -do run.do -c tb_top
# // ModelSim ACTEL 10.1b Apr 27 2012
# //
# // Copyright 1991-2012 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading sv_std.std
# Loading work.tb_top
# Loading work.digital_core
# Loading work.clkgen
# Loading work.clk_ctl
# Loading work.wb_crossbar
# Loading work.uart_core
# Loading work.uart_cfg
# Loading work.generic_register
# Loading work.stat_register
# Loading work.uart_txfsm
# Loading work.uart_rxfsm
# Loading work.async_fifo
# Loading work.double_sync_low
# Loading work.spi_core
# Loading work.spi_if
# Loading work.spi_ctl
# Loading work.spi_cfg
# Loading work.req_register
# Loading work.oc8051_top
# Loading work.oc8051_decoder
# Loading work.oc8051_alu
# Loading work.oc8051_multiply
# Loading work.oc8051_divide
# Loading work.oc8051_ram_top
# Loading work.oc8051_ram_256x8_two_bist
# Loading work.oc8051_alu_src_sel
# Loading work.oc8051_comp
# Loading work.oc8051_cy_select
# Loading work.oc8051_indi_addr
# Loading work.oc8051_memory_interface
# Loading work.oc8051_sfr
# Loading work.oc8051_acc
# Loading work.oc8051_b_register
# Loading work.oc8051_sp
# Loading work.oc8051_dptr
# Loading work.oc8051_psw
# Loading work.oc8051_ports
# Loading work.oc8051_int
# Loading work.oc8051_tc
# Loading work.oc8051_tc2
# Loading work.oc8051_xrom
# Loading work.oc8051_xram
# Loading work.uart_agent
# Loading work.m25p20
# Loading work.memory_access
# Loading work.acdc_check
# Loading work.internal_logic
# Loading work.AT45DB321
# Loading work.tb_glbl
# Loading work.bit_register
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(324): [TOFD] - System task or function '$shm_open' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(325): [TOFD] - System task or function '$shm_probe' is not defined.
#
# Region: /tb_top
# ** Warning: (vsim-3017) ../tb/tb_top.v(221): [TFMPC] - Too few port connections. Expected 40, found 38.
#
# Region: /tb_top/u_core
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_mode'.
#
# ** Warning: (vsim-3722) ../tb/tb_top.v(221): [TFMPC] - Missing connection for port 'scan_enable'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(244): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_rxfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(244): [TFMPC] - Missing connection for port 'aempty'.
#
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(260): [TFMPC] - Too few port connections. Expected 14, found 12.
#
# Region: /tb_top/u_core/u_uart_core/u_txfifo
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'afull'.
#
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(260): [TFMPC] - Missing connection for port 'aempty'.
#
# do run.do
# i : 02
# i : 00
# i : 08
# i : 12
# i : 00
# i : 64
# i : 80
# i : fe
# i : 75
# i : 81
# NOTE : Load memory with Initial delivery content
# NOTE : Initial Load End
# --> Dumpping the design
# NOTE: COMMUNICATION (RE)STARTED
# Config-Write: Id: 3 Addr = 0000, Cfg. Data = 00000007
#
# ... Writing char 24 ...
# ... Write data 24 to UART done cnt : 1 ...
#
#
# ... Writing char 81 ...
# ... Write data 81 to UART done cnt : 2 ...
#
#
# ... Writing char 09 ...
# ... Write data 09 to UART done cnt : 3 ...
#
#
# ... Writing char 63 ...
# ... Write data 63 to UART done cnt : 4 ...
#
#
# ... Writing char 0d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 24
# ... Read Data from UART done cnt : 1...
# ... Write data 0d to UART done cnt : 5 ...
#
#
# ... Writing char 8d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 81
# ... Read Data from UART done cnt : 2...
# ... Write data 8d to UART done cnt : 6 ...
#
#
# ... Writing char 65 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 09
# ... Read Data from UART done cnt : 3...
# ... Write data 65 to UART done cnt : 7 ...
#
#
# ... Writing char 12 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63
# ... Read Data from UART done cnt : 4...
# ... Write data 12 to UART done cnt : 8 ...
#
#
# ... Writing char 01 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
# ... Read Data from UART done cnt : 5...
# ... Write data 01 to UART done cnt : 9 ...
#
#
# ... Writing char 0d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8d
# ... Read Data from UART done cnt : 6...
# ... Write data 0d to UART done cnt : 10 ...
#
#
# ... Writing char 76 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65
# ... Read Data from UART done cnt : 7...
# ... Write data 76 to UART done cnt : 11 ...
#
#
# ... Writing char 3d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12
# ... Read Data from UART done cnt : 8...
# ... Write data 3d to UART done cnt : 12 ...
#
#
# ... Writing char ed ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 01
# ... Read Data from UART done cnt : 9...
# ... Write data ed to UART done cnt : 13 ...
#
#
# ... Writing char 8c ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
# ... Read Data from UART done cnt : 10...
# ... Write data 8c to UART done cnt : 14 ...
#
#
# ... Writing char f9 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 76
# ... Read Data from UART done cnt : 11...
# ... Write data f9 to UART done cnt : 15 ...
#
#
# ... Writing char c6 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 3d
# ... Read Data from UART done cnt : 12...
# ... Write data c6 to UART done cnt : 16 ...
#
#
# ... Writing char c5 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match ed
# ... Read Data from UART done cnt : 13...
# ... Write data c5 to UART done cnt : 17 ...
#
#
# ... Writing char aa ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8c
# ... Read Data from UART done cnt : 14...
# ... Write data aa to UART done cnt : 18 ...
#
#
# ... Writing char e5 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match f9
# ... Read Data from UART done cnt : 15...
# ... Write data e5 to UART done cnt : 19 ...
#
#
# ... Writing char 77 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c6
# ... Read Data from UART done cnt : 16...
# ... Write data 77 to UART done cnt : 20 ...
#
#
# ... Writing char 12 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5
# ... Read Data from UART done cnt : 17...
# ... Write data 12 to UART done cnt : 21 ...
#
#
# ... Writing char 8f ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa
# ... Read Data from UART done cnt : 18...
# ... Write data 8f to UART done cnt : 22 ...
#
#
# ... Writing char f2 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match e5
# ... Read Data from UART done cnt : 19...
# ... Write data f2 to UART done cnt : 23 ...
#
#
# ... Writing char ce ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 77
# ... Read Data from UART done cnt : 20...
# ... Write data ce to UART done cnt : 24 ...
#
#
# ... Writing char e8 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12
# ... Read Data from UART done cnt : 21...
# ... Write data e8 to UART done cnt : 25 ...
#
#
# ... Writing char c5 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8f
# ... Read Data from UART done cnt : 22...
# ... Write data c5 to UART done cnt : 26 ...
#
#
# ... Writing char 5c ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match f2
# ... Read Data from UART done cnt : 23...
# ... Write data 5c to UART done cnt : 27 ...
#
#
# ... Writing char bd ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match ce
# ... Read Data from UART done cnt : 24...
# ... Write data bd to UART done cnt : 28 ...
#
#
# ... Writing char 2d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match e8
# ... Read Data from UART done cnt : 25...
# ... Write data 2d to UART done cnt : 29 ...
#
#
# ... Writing char 65 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5
# ... Read Data from UART done cnt : 26...
# ... Write data 65 to UART done cnt : 30 ...
#
#
# ... Writing char 63 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 5c
# ... Read Data from UART done cnt : 27...
# ... Write data 63 to UART done cnt : 31 ...
#
#
# ... Writing char 0a ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match bd
# ... Read Data from UART done cnt : 28...
# ... Write data 0a to UART done cnt : 32 ...
#
#
# ... Writing char 80 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 2d
# ... Read Data from UART done cnt : 29...
# ... Write data 80 to UART done cnt : 33 ...
#
#
# ... Writing char 20 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65
# ... Read Data from UART done cnt : 30...
# ... Write data 20 to UART done cnt : 34 ...
#
#
# ... Writing char aa ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63
# ... Read Data from UART done cnt : 31...
# ... Write data aa to UART done cnt : 35 ...
#
#
# ... Writing char 9d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0a
# ... Read Data from UART done cnt : 32...
# ... Write data 9d to UART done cnt : 36 ...
#
#
# ... Writing char 96 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 80
# ... Read Data from UART done cnt : 33...
# ... Write data 96 to UART done cnt : 37 ...
#
#
# ... Writing char 13 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 20
# ... Read Data from UART done cnt : 34...
# ... Write data 13 to UART done cnt : 38 ...
#
#
# ... Writing char 0d ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa
# ... Read Data from UART done cnt : 35...
# ... Write data 0d to UART done cnt : 39 ...
#
#
# ... Writing char 53 ...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 9d
# ... Read Data from UART done cnt : 36...
# ... Write data 53 to UART done cnt : 40 ...
#
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 96
# ... Read Data from UART done cnt : 37...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 13
# ... Read Data from UART done cnt : 38...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
# ... Read Data from UART done cnt : 39...
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 53
# ... Read Data from UART done cnt : 40...
# -------------------- Reporting Configuration --------------------
# Data bit number setting is : 8
# Stop bit number setting is : 1
# Divisor of Uart clock is : 15
# Parity is disable
# Even parity setting
# FIFO mode is disable
# -----------------------------------------------------------------
# -------------------- Reporting Status --------------------
#
# Number of character received is : 40
# Number of character sent is : 40
# Number of parity error rxd is : 0
# Number of stop1 error rxd is : 0
# Number of stop2 error rxd is : 0
# Number of timeout error is : 0
# Number of error is : 0
# -----------------------------------------------------------------
#
# -------------------------------------------------
# Test Status
# warnings: 0, errors: 0
#
# -------------------------------------------------
# Test Status
# warnings: 0, errors: 0
#
# =========
# Test Status: TEST PASSED
# =========
#

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