URL
https://opencores.org/ocsvn/onewire/onewire/trunk
Subversion Repositories onewire
Compare Revisions
- This comparison shows the changes necessary to convert path
/onewire
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/HDL/ds1820_mstr.vhd
227,7 → 227,7
------------------------------------- |
-- ID RAM --- |
------------------------------------- |
-- ow_idram - store and recalls the device ids for devices on the ow bus. |
-- ow_idram - bit indexed ram, store and recalls the device ids for devices on the ow bus. |
-- this is implemented in a seperate module to ensure that it uses a internal ram |
-- which greatly reduces the FPGA utilization (saves a lot of FFs and LUTs) |
u_idram : entity work.ow_idram(rtl) |
/trunk/HDL/ds1820_mstr_tb.vhd
110,6 → 110,7
signal owin : std_logic; --one wire input to dut |
signal owout : std_logic; --one wire output from dut |
signal dio : std_logic; --one wire bus |
signal pio : std_logic; --switch of ds2405 |
|
begin |
|
306,7 → 307,7
u_ds18b20_3 : entity work.ds18b20_sim(sim) |
generic map ( |
timing => "min", |
devid => x"0083726dab32bf28" |
devid => x"0083726d2b32bf28" |
) |
port map ( |
--dio => dio3, |
314,5 → 315,29
dio => dio, |
tempin => 57.25 |
); |
|
u_ds18b20_4 : entity work.ds18b20_sim(sim) |
generic map ( |
timing => "min", |
devid => x"0083726d3b32bf28" |
) |
port map ( |
--dio => dio3, |
pwrin => '1', |
dio => dio, |
tempin => 57.25 |
); |
|
--simulated addressable switch |
u_ds2405 : entity work.ds2405_sim(sim) |
generic map ( |
timing => "min", |
devid => x"0034756483522105" |
) |
port map ( |
--dio => dio3, |
pio => pio, |
dio => dio |
); |
pio <= 'H'; |
|
end sim; |
/trunk/HDL/ds2405_sim.vhd
0,0 → 1,456
---------------------------------------------------------------------------------- |
-- <c>2018 william b hunter |
-- This file is part of ow2rtd. |
-- |
-- ow2rtd is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU Lessor General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- ow2rtd is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lessor General Public License |
-- along with ow2rtd. If not, see <https://www.gnu.org/licenses/>. |
----------------------------------------------------------------------------------- |
-- Create Date: 10/13/2023 |
-- file: ds2405_sim.vhd |
-- description: A simulation model for the DS2405 addressable switch |
-- |
-- Generics are used to set the device ID and the timing model |
-- |
-- This only simulates the SEARCH, ROM, SKIP, CONFIG, CONV, and READ commands |
----------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
------------------------------------------------------------------------------------- |
-- Entity declaration |
------------------------------------------------------------------------------------- |
entity ds2405_sim is |
generic ( |
timing : in string := "ave"; |
devid : in std_logic_vector(63 downto 0) := x"1234567123456705" |
); |
port ( |
--global signals |
pio : inout std_logic; |
dio : inout std_logic --synchronous reset |
); |
end ds2405_sim; |
|
|
--library unisim; |
--use unisim.vcomponents.all; |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.numeric_std.all; |
library work; |
|
architecture sim of ds2405_sim is |
|
--low time to trigger a reaset |
constant tmin_rstl : time := 240 us; |
constant tave_rstl : time := 400 us; |
constant tmax_rstl : time := 480 us; |
signal trstl : time := tmin_rstl; |
--high time between reset pulse and presence pulse |
signal tpdih : time; |
constant tmin_pdih : time := 15 us; |
constant tave_pdih : time := 45 us; |
constant tmax_pdih : time := 60 us; |
--presence pulse low time |
signal tpdlo : time; |
constant tmin_pdlo : time := 60 us; |
constant tave_pdlo : time := 180 us; |
constant tmax_pdlo : time := 240 us; |
--write 0 low time |
signal tlow0 : time; |
constant tmin_low0 : time := 60 us; |
constant tave_low0 : time := 100 us; |
constant tmax_low0 : time := 120 us; |
--write 1 low time |
signal tlow1 : time; |
constant tmin_low1 : time := 1 us; |
constant tave_low1 : time := 10 us; |
constant tmax_low1 : time := 15 us; |
--master write data sample time |
signal tsamp : time := 1 us; |
constant tmin_samp : time := 15 us; |
constant tave_samp : time := 30 us; |
constant tmax_samp : time := 60 us; |
--slave read recovery time |
signal trec : time := 1 us; |
constant tmin_rec : time := 1 us; |
constant tave_rec : time := 3 us; |
constant tmax_rec : time := 6 us; |
--slave read data valid time |
signal trdv : time := 15 us; |
constant tmin_rdv : time := 15 us; |
constant tave_rdv : time := 30 us; |
constant tmax_rdv : time := 60 us; |
|
--recall from eeprom timing |
--note: dallas part does not spec this timing |
signal trecall : time := 100 us; |
|
signal tcopy : time := 1 us; |
constant tmax_copy : time := 10 ms; |
constant tave_copy : time := 2 ms; |
constant tmin_copy : time := 1 ms; |
|
signal clk10m : std_logic; |
signal rstdet : std_logic := '0'; --indicates a detected a reset pulse from the master |
signal trise : time := now; |
signal tfall : time := now; |
signal rstdly : std_logic := '1'; |
--signal tdif : time; |
signal timertime : time; |
signal timer : unsigned(15 downto 0); |
signal timertrig : std_logic := '0'; |
signal timerdone : std_logic := '1'; |
signal switch : std_logic := '0'; |
|
|
|
type state_type is (S_IDLE, S_RSTRESP,S_RSTRESP2,S_RSTRESP3, |
S_GETBYTE, S_GETBYTE2, S_PARSE, |
S_READROM, S_READROM2, S_SRCHROM, S_SRCHROMNOT, S_SRCHROMWR, |
S_MATCHROM, S_MATCHROM2, S_SRCHALARM, S_SKIPROM, |
S_PARSE2, S_READSW, S_WRITE1, S_WRITE2, S_WRITE3, |
S_READ, S_READRCVR, S_CRC); |
signal state : state_type := S_IDLE; |
signal nxt_state : state_type := S_IDLE; |
signal dout : std_logic := 'Z'; --read output bit from slave to master |
signal rstdout : std_logic := '1'; --read output bit from main process |
signal recalldout : std_logic := '1'; --read output bit from recall process |
signal copydout : std_logic := '1'; --read output bit from copy process |
signal convdout : std_logic := '1'; --read output bit from conv process |
signal readdout : std_logic := '1'; -- output data from read state machine |
signal din : std_logic := '1'; --resolved input data bit |
--signal rstout : std_logic := 'Z'; |
signal bitcnt : integer; |
signal shiftbyte : std_logic_vector(7 downto 0); |
signal shiftid : std_logic_vector(63 downto 0); |
signal busy : std_logic := '0'; |
|
--These signals are for the read state machine |
signal bitout : std_logic := '1'; --bit value to be read by master |
signal wrbitin : std_logic := '0'; -- the bit value written by the master |
signal wrbiterr : std_logic := '0'; -- indicates a master write pulse with an illegal timing |
signal writedet : std_logic := '0'; -- strobe indicating the master wrote a bit |
signal readen : std_logic := '0'; --enables the slave responses to the master read pulses |
signal readdet : std_logic := '0'; -- strobe indicating the master read a bit |
signal readdly : std_logic := '0'; -- delayed version of din for detecting read strobes |
signal readbit : std_logic := '0'; -- data to output from read state machine |
|
signal crc : std_logic_vector(7 downto 0); |
begin |
trstl <= tmin_rstl when timing = "MIN" else tave_rstl when timing = "AVE" else tmax_rstl; |
tpdih <= tmin_pdih when timing = "MIN" else tave_pdih when timing = "AVE" else tmax_pdih; |
tpdlo <= tmin_pdlo when timing = "MIN" else tave_pdlo when timing = "AVE" else tmax_pdlo; |
tsamp <= tmin_samp when timing = "MIN" else tave_samp when timing = "AVE" else tmax_samp; |
trdv <= tmin_rdv when timing = "MIN" else tave_rdv when timing = "AVE" else tmax_rdv; |
|
p_clk10m : process |
begin |
clk10m <= '0'; |
wait for 50 ns; |
clk10m <= '1'; |
wait for 50 ns; |
end process; |
|
p_edges : process |
begin |
wait until din = '0'; |
tfall <= now; |
wait until din = '1'; |
trise <= now; |
end process; |
|
|
--this handles the master reseting this slave |
rstdly <= transport din after trstl; |
|
p_rst : process |
begin |
wait until rstdly = '0'; |
--if last transition was falling edge and it was long ago... |
if tfall > trise and now - tfall >= trstl then |
rstdet <= '1'; |
wait until din <= '1'; |
rstdet <= '0'; |
end if; |
end process; |
|
--p_readstb and p_read - work together to facilitate a read |
-- readen is set high to enable a read, then if din is low for 1 us the readdet signal triggers |
-- which causes readout to be driven low for a bit time if shift(0) is low |
-- after the bit time expires, din returns high, causing readdet to go low, and cycle is complete |
readdly <= transport din after 1us; |
p_readstb : process |
begin |
wait until readdly = '0'; |
if tfall > trise and now - tfall >= 1us and readen = '1' then |
readdet <= '1'; |
wait until din <= '1'; |
readdet <= '0'; |
end if; |
end process; |
|
p_read : process |
begin |
wait until readdet = '1' and readen = '1'; |
readdout <= readbit; |
wait for trdv; |
readdout <= '1'; |
end process; |
|
--this handles the master writing bits to this slave |
p_write : process |
begin |
wait until din = '1'; |
--dont detect writes during read operations |
if readen = '0' and readdet = '0' then |
if now - tfall > tmin_low0 and now-tfall < tmax_low0 then |
wrbitin <= '0'; |
writedet <= '1'; |
wrbiterr <= '0'; |
elsif now - tfall > tmin_low1 and now-tfall < tmax_low1 then |
wrbitin <= '1'; |
writedet <= '1'; |
wrbiterr <= '0'; |
elsif now - tfall < trstl then |
wrbiterr <= '1'; |
end if; |
end if; |
wait until din = '0'; |
writedet <= '0'; |
end process; |
|
|
p_timer : process(clk10m) |
begin |
if rising_edge(clk10m) then |
if timertrig = '1' then |
timer <= to_unsigned(integer(timertime/100 ns),16); |
timerdone <= '0'; |
elsif timer > 1 then |
timer <= timer -1; |
else |
timerdone <= '1'; |
end if; |
end if; |
end process; |
|
--this handles the master reading a bit from this slave |
--dout <= '0' when rdbiten = '1' and dout = '0' and now-tfall < trdv else '1'; |
|
p_state :process(clk10m) |
begin |
if rising_edge (clk10m) then |
if rstdet = '1' then |
state <= S_RSTRESP; |
rstdout <= '1'; |
readen <= '0'; |
else |
case state is |
when S_IDLE => |
rstdout <= '1'; |
readen <= '0'; |
bitcnt <= 0; |
shiftbyte <= x"00"; |
shiftid <= devid; |
when S_RSTRESP => |
readen <= '0'; |
bitcnt <= 0; |
rstdout <= '1'; |
shiftbyte <= x"00"; |
shiftid <= devid; |
if timertrig = '0' and din = '1' then |
timertime <= tpdih; |
timertrig <= '1'; |
elsif timertrig = '1' then |
timertrig <= '0'; |
state <= S_RSTRESP2; |
end if; |
when S_RSTRESP2 => |
if timertrig = '0' and timerdone = '1' then |
rstdout <= '0'; |
timertime <= tpdlo; |
timertrig <= '1'; |
elsif timertrig = '1' then |
timertrig <= '0'; |
state <= S_RSTRESP3; |
end if; |
when S_RSTRESP3 => |
if timerdone = '1' then |
rstdout <= '1'; |
state <= S_GETBYTE; |
nxt_state <= S_PARSE; |
end if; |
when S_GETBYTE => |
if writedet = '0' then |
state <= S_GETBYTE2; |
end if; |
when S_GETBYTE2 => |
if writedet = '1' then |
shiftbyte <= wrbitin & shiftbyte(7 downto 1); |
if bitcnt < 7 then |
bitcnt <= bitcnt + 1; |
state <= S_GETBYTE; |
else |
bitcnt <= 0; |
state <= nxt_state; |
end if; |
end if; |
when S_PARSE => |
shiftid <= devid; |
case shiftbyte is |
when x"33" => --read the rom id from the device, can only be used on single device bus |
state <= S_READROM; |
when x"55" => --match rom, used to address a single device on the bus |
state <= S_MATCHROM; |
when x"F0" => --use to find the devices on a multiple device bus |
state <= S_SRCHROM; |
when x"EC" => --search alarm, used to find devices that have the pio line pulled low |
if pio = '0' then |
state <= S_SRCHROM; |
else |
state <= S_IDLE; |
end if; |
when x"CC" => --skip rom, skips rom addressing, for single device busses or broadcast commands |
state <= S_GETBYTE; |
nxt_state <= S_PARSE2; |
when others => |
state <= S_IDLE; |
end case; |
when S_READROM => |
readen <= '1'; |
if readdet = '1' then |
shiftid <= shiftid(0) & shiftid(63 downto 1); |
if bitcnt < 55 then |
bitcnt <= bitcnt + 1; |
state <= S_READRCVR; |
nxt_state <= S_READROM; |
else |
state <= S_CRC; |
nxt_state <= S_READROM2; |
shiftid <= x"00000000000000" & crc; |
end if; |
end if; |
when S_READROM2 => |
state <= S_GETBYTE; |
nxt_state <= S_PARSE2; |
when S_MATCHROM => |
if writedet = '0' then |
state <= S_MATCHROM2; |
end if; |
when S_MATCHROM2 => |
if writedet = '1' then |
if wrbitin /= shiftid(0) then |
state <= S_IDLE; --this part is removed from search, goto idle, wait for rstdet |
else |
shiftid <= shiftid(0) & shiftid(63 downto 1); |
if bitcnt < 63 then |
bitcnt <= bitcnt + 1; |
state <= S_MATCHROM; |
else |
bitcnt <= 0; |
switch <= not switch; |
state <= S_READSW; |
end if; |
end if; |
end if; |
when S_READSW => |
shiftid <= x"000000000000000" & "000" & pio; |
readen <= '1'; |
if readdet = '1' then |
state <= S_READRCVR; |
nxt_state <= S_READSW; |
end if; |
when S_SRCHROM => |
readen <= '1'; |
readbit <= shiftid(0); |
if readdet = '1' then |
state <= S_READRCVR; |
nxt_state <= S_SRCHROMNOT; |
end if; |
when S_SRCHROMNOT => |
readen <= '1'; |
readbit <= not shiftid(0); |
if readdet = '1' then |
state <= S_READRCVR; |
nxt_state <= S_SRCHROMWR; |
end if; |
when S_SRCHROMWR => |
readen <= '0'; |
if writedet = '1' then |
if wrbitin /= shiftid(0) then |
state <= S_IDLE; --this part is removed from search, goto idle, wait for rstdet |
else |
shiftid <= shiftid(0) & shiftid(63 downto 1); |
if bitcnt < 63 then |
bitcnt <= bitcnt + 1; |
state <= S_SRCHROM; |
else |
bitcnt <= 0; |
state <= S_READSW; |
end if; |
end if; |
end if; |
when S_READRCVR => |
readen <= '0'; |
if readdet = '0' then |
state <= nxt_state; |
end if; |
when S_CRC => |
readen <= '1'; |
if readdet = '1' then |
shiftid <= shiftid(0) & shiftid(63 downto 1); |
if bitcnt < 7 then |
bitcnt <= bitcnt + 1; |
state <= S_READRCVR; |
nxt_state <= S_READ; |
else |
state <= S_READRCVR; |
nxt_state <= S_IDLE; |
bitcnt <= 0; |
shiftid <= x"00000000000000" & crc; |
end if; |
end if; |
when others => |
state <= S_IDLE; |
end case; |
end if; |
end if; |
end process; |
|
p_crc : process |
begin |
crc <= x"00"; |
wait until state = S_READ or state = S_READROM; |
crc <= x"00"; |
while state = S_READ or state = S_READROM loop |
wait until din = '0' or (state /= S_READ and state /= S_READROM); |
if din = '0' then |
if (crc(0) xor shiftid(0)) = '1' then |
crc <= ('0' & crc(7 downto 1)) xor x"8c"; |
else |
crc <= ('0' & crc(7 downto 1)); |
end if; |
end if; |
end loop; |
end process; |
|
|
din <= '0' when dio = '0' else '1'; |
dout <= rstdout and copydout and convdout and recalldout and readdout; |
dio <= '0' when dout = '0' else 'Z'; |
pio <= '0' when switch = '0' else 'H'; |
busy <= '0' when state = S_IDLE else '1'; |
|
end sim; |
/trunk/HDL/ow_search.vhd
63,14 → 63,14
architecture rtl of ow_search is |
|
|
type h_state_type is (H_IDLE, H_RST, H_SKIP, H_READBIT, H_READCMP, H_PARSE, H_INCLOOP, H_FILL, H_ERROR); |
type h_state_type is (H_IDLE, H_RST, H_WRCMD, H_READBIT, H_READCMP, H_PARSE, H_INCLOOP, H_FILL, H_ERROR); |
signal h_state : h_state_type := H_IDLE; |
type f_state_type is (F_IDLE, F_FIND, F_INC); |
signal f_state : f_state_type := F_IDLE; |
|
signal idcnt : integer range 0 to 31; |
signal lastfork : integer range 0 to 63; |
signal lastzero : integer range 0 to 63; |
signal lastfork : integer range 0 to 64; |
signal zerofork : integer range 0 to 64; |
signal idbitnum : integer range 0 to 63; |
signal lastdev : std_logic := '0'; |
signal h_err : std_logic := '0'; |
94,7 → 94,7
attribute mark_debug of h_state : signal is "true"; |
attribute mark_debug of idbitnum : signal is "true"; |
attribute mark_debug of lastfork : signal is "true"; |
attribute mark_debug of lastzero : signal is "true"; |
attribute mark_debug of zerofork : signal is "true"; |
attribute mark_debug of rxpat : signal is "true"; |
attribute mark_debug of iwrbyte : signal is "true"; |
attribute mark_debug of irdbit : signal is "true"; |
114,15 → 114,26
------------------------------------------------------ |
--p_hunt - hunts for the next device using the algorithm described in Maxim (Analog Devices) app note APP187 |
-- the app note is modified slightly for optimization in VHDL |
-- "restart" resets all parameters to rediscover all ROM iDs |
-- "hunt" searches for the next ROM ID in the sort order |
-- the algorithm works by taking successive passes through the address field with each pass revealing the next device |
-- address in alphabetic order. The first pass takes the 0 path at each conflicting address bit (or fork). By keeping |
-- track of the last conflicting bit in variable zerofork/lastfork, the algorithm knows were to deviate from the |
-- present address on the next pass. On subsequent passes, for all conflicts up to the lastfork, |
-- the same fork is taken as was taken on the previous pass, which could be a 1 or 0. At the fork at the lastfork, |
-- the 1 path is taken, because the 0 path was taken in the previous pass. The variable zerofork is used to keep track |
-- of the last fork for this pass at which a zero path was taken, and lastfork is the zerofork from the previous pass. |
-- zerofork and lastfork are set to 64 if there are no zero forks taken. |
-- If no zero forks were taken, then the last device was found and the lastdev is set, afterwhich the FILL state |
-- is used to zero out the remaining unused ID memeory locations |
-- |
p_hunt : process (clk) |
begin |
if rising_edge(clk) then |
if srst = '1' or restart = '1' then |
--Start a new search, put all signals into default state, and start in H_IDLE state |
h_state <= H_IDLE; |
idbitnum <= 0; |
lastfork <= 0; |
lastfork <= 64; |
zerofork <= 64; |
lastdev <= '0'; |
rxpat <= "00"; |
h_err <= '0'; |
136,8 → 147,9
else |
case h_state is |
when H_IDLE => |
idbitnum <= 0; |
lastzero <= 0; |
--when in idle, all signals in default state |
idbitnum <= 0; |
zerofork <= 64; |
rxpat <= "00"; |
iwrbyte <= '0'; |
irdbit <= '0'; |
146,9 → 158,11
iobit <= '0'; |
obyte <= x"00"; |
if h_start = '1' then |
--detected command to search for next onewire device |
if lastdev = '0' then |
--first time thorough, reset the one-wire bus |
h_state <= H_RST; |
izzbit <= '1'; |
izzbit <= '1'; --send reset signal |
h_err <= '0'; |
else |
h_state <= H_FILL; |
159,44 → 173,63
izzbit <= '0'; |
end if; |
when H_RST => |
--reset the bus at start of each pass, all devices are activated |
if izzbit = '1' then |
izzbit <= '0'; |
izzbit <= '0'; --terminate the reset request |
elsif busyin = '0' then |
--reset is completed, the devices should have responded |
if ibit = '1' then |
--no response, no devices on bus, so error out |
h_state <= H_ERROR; |
else |
--send "search rom" command |
obyte <= x"f0"; |
iwrbyte <= '1'; |
h_state <= H_SKIP; |
h_state <= H_WRCMD; |
end if; |
end if; |
when H_SKIP => |
when H_WRCMD => |
--waits for end write command byte, then reads a response bit |
if iwrbyte = '1' then |
iwrbyte <= '0'; |
iwrbyte <= '0'; --terminate write "search rom" command request |
elsif busyin = '0' then |
-- when the write command is completed |
-- read a bit, this will be the AND of the |
-- first address bit of all devices on the bus |
irdbit <= '1'; |
h_state <= H_READBIT; |
end if; |
when H_READBIT => |
--reads the address bit |
if irdbit = '1' then |
irdbit <= '0'; |
irdbit <= '0'; --terminate the read bit request |
elsif busyin = '0' then |
rxpat(1) <= ibit; |
--wait until bit is read |
--save the AND of the address bit of all devices |
rxpat(1) <= ibit; |
--and read the AND of the compliment of the address bit of all devices |
irdbit <= '1'; |
h_state <= H_READCMP; |
end if; |
when H_READCMP => |
--reads the complement of the address bit |
if irdbit = '1' then |
irdbit <= '0'; |
irdbit <= '0'; --terminate the read complement bit request |
elsif busyin = '0' then |
--when bit is read, |
--save the AND of the complimented address bit of all devices |
rxpat(0) <= ibit; |
h_state <= H_PARSE; |
end if; |
when H_PARSE => |
--with the AND of the address bit and the AND of the complimented address bit |
-- decide how to proceed (see APP note) |
case rxpat is |
when "11" => |
--no device responded |
h_state <= H_ERROR; |
when "00" => |
--00 indicates a conflict, devices disagree on this bit |
if idbitnum = lastfork then |
--last_romid(63 downto 0) <= last_romid(0) & last_romid(63 downto 1); |
--new_romid(63 downto 0) <= '1' & new_romid(63 downto 1); |
210,7 → 243,7
iobit <= '0'; |
iwrbit <= '1'; |
iwe <= '1'; |
lastzero <= idbitnum; |
zerofork <= idbitnum; |
h_state <= H_INCLOOP; |
else |
--last_romid(63 downto 0) <= last_romid(0) & last_romid(63 downto 1); |
219,7 → 252,7
iwrbit <= '1'; |
iwe <= '1'; |
if id_rbit = '0' then |
lastzero <= idbitnum; |
zerofork <= idbitnum; |
end if; |
h_state <= H_INCLOOP; |
end if; |
232,17 → 265,21
h_state <= H_INCLOOP; |
end case; |
when H_INCLOOP => |
--increments the search to the next bit and terminates when all bits are finished |
if iwrbit = '1' or iwe = '1' then |
--terminate the write request of the current bit |
iwrbit <= '0'; |
iwe <= '0'; |
elsif busyin = '0' then |
if idbitnum = 63 then |
--at end of the address, go back to idle, and move lastzero to lastfork |
h_state <= H_IDLE; |
lastfork <= lastzero; |
if lastzero = 0 then |
lastdev <= '1'; |
lastfork <= zerofork; |
if zerofork = 64 then |
lastdev <= '1'; --make last device if there no zero forks were taken |
end if; |
else |
-- continue on with next bit by requesting a read of the next address bit |
idbitnum <= idbitnum + 1; |
irdbit <= '1'; |
h_state <= H_READBIT; |
249,6 → 286,7
end if; |
end if; |
when H_FILL => |
--this fills the unused address feilds with zeros after the last device is found. |
if iwe = '1' then |
iwe <= '0'; |
elsif idbitnum = 63 then |
280,24 → 318,29
if srst = '1' then |
idcnt <= 0; |
f_state <= F_IDLE; |
h_start <= '0'; |
restart <= '0'; |
f_err <= '0'; |
else |
case f_state is |
when F_IDLE => |
when F_IDLE => |
if start = '1' then |
restart <= '1'; |
elsif restart = '1' then |
restart <= '0'; |
h_start <= '1'; |
f_state <= F_FIND; |
f_state <= F_FIND; |
idcnt <= 0; |
f_err <= '0'; |
end if; |
when F_FIND => |
if h_start = '1' then |
--terminate the h_start and wait for hunt state to finish |
if h_start = '1' then |
h_start <= '0'; |
elsif h_busy = '0' then |
if h_err = '1' then |
--hunt is finished, go to inc state if no error |
--error also indicates there are no more one-wire devices |
if h_err = '1' then |
f_state <= F_IDLE; |
f_err <= '1'; |
else |