URL
https://opencores.org/ocsvn/opb_usblite/opb_usblite/trunk
Subversion Repositories opb_usblite
Compare Revisions
- This comparison shows the changes necessary to convert path
/opb_usblite/trunk/pcores/opb_usblite_v1_00_a/hdl/vhdl
- from Rev 2 to Rev 5
- ↔ Reverse comparison
Rev 2 → Rev 5
/opb_usblite_core.vhd
187,6 → 187,14
constant STATUS_REG_ADR : std_logic_vector(0 to 1) := "10"; |
constant CTRL_REG_ADR : std_logic_vector(0 to 1) := "11"; |
|
-- ADDRESS MAP |
-- =========== |
-- RX FIFO base + $0 |
-- TX FIFO base + $4 |
-- CONTROL REG base + $8 |
-- STATUS REG base + $C |
|
|
-- Read Only |
signal status_Reg : std_logic_vector(7 downto 0); |
-- bit 0 rx_Data_Present |
194,15 → 202,18
-- bit 2 tx_Buffer_Empty |
-- bit 3 tx_Buffer_Full |
-- bit 4 interrupt flag |
-- bit 5 not used |
-- bit 6 online flag |
-- bit 7 suspend flag |
|
-- Write Only |
-- bit 0 Reset_TX_FIFO |
-- bit 1 Reset_RX_FIFO |
-- bit 0 Reset_TX_FIFO -- not used |
-- bit 1 Reset_RX_FIFO -- not used |
-- bit 2-3 Dont'Care |
-- bit 4 enable_rxinterrupts |
-- bit 5 Dont'Care |
-- bit 6 enable_txinterrupts |
-- bit 7 tx_enable |
-- bit 7 tx_enable -- not used |
|
signal enable_txinterrupts : std_logic; |
signal enable_rxinterrupts : std_logic; |
360,8 → 371,6
status_Reg(5) <= '0'; |
status_Reg(6) <= online; |
status_Reg(7) <= suspend; |
-- status_Reg(6) <= '0'; |
-- status_Reg(7) <= '0'; |
|
|
----------------------------------------------------------------------------- |
/opb_usblite.vhd
29,14 → 29,14
C_OPB_DWIDTH : integer := 32; |
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_0000"; |
C_HIGHADDR : std_logic_vector := X"FFFF_00FF"; |
C_SYSRST : std_logic := '1'; |
C_PHYMODE : std_logic := '1'; |
C_VENDORID : std_logic_vector(15 downto 0) := X"1234"; |
C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678"; |
C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200"; |
C_SELFPOWERED : boolean := false; |
C_RXBUFSIZE_BITS: integer range 7 to 12 := 10; |
C_TXBUFSIZE_BITS: integer range 7 to 12 := 10 |
C_SYSRST : std_logic := '1'; -- enable external reset |
C_PHYMODE : std_logic := '1'; -- phy mode |
C_VENDORID : std_logic_vector(15 downto 0) := X"1234"; -- VID |
C_PRODUCTID : std_logic_vector(15 downto 0) := X"5678"; -- PID |
C_VERSIONBCD : std_logic_vector(15 downto 0) := X"0200"; -- device version |
C_SELFPOWERED : boolean := false; -- self or bus powered |
C_RXBUFSIZE_BITS: integer range 7 to 12 := 10; -- size of rx buf (2^10 = 1024 bytes) |
C_TXBUFSIZE_BITS: integer range 7 to 12 := 10 -- size of tx buf (2^10 = 1024 bytes) |
); |
port ( |
-- Global signals |
61,12 → 61,12
Interrupt : out std_logic; |
|
-- USB signals |
txdp : out std_logic; |
txdn : out std_logic; |
txoe : out std_logic; |
rxd : in std_logic; |
rxdp : in std_logic; |
rxdn : in std_logic |
txdp : out std_logic; -- connect to VPO |
txdn : out std_logic; -- connect to VMO/FSEO |
txoe : out std_logic; -- connect to OE |
rxd : in std_logic; -- connect to RCV |
rxdp : in std_logic; -- connect to VP |
rxdn : in std_logic -- connect to VM |
); |
|
end entity OPB_USBLITE; |