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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 10 to Rev 8
    ↔ Reverse comparison
  •

Rev 10 → Rev 8

/Open8.vhd
73,7 → 73,6
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/19/06 Design Start
-- Seth Henry 01/18/11 Fixed BTT instruction to match V8
 
library ieee;
use ieee.std_logic_1164.all;
94,7 → 93,7
Enable_Auto_Increment : std_logic := '0' ); -- Modify indexed instr
port(
Clock : in std_logic;
Reset : in std_logic;
Reset_n : in std_logic;
CPU_Halt : in std_logic;
Interrupts : in INTERRUPT_BUNDLE;
--
134,8 → 133,8
constant ALU_LDX : OPCODE_TYPE := "11110"; -- x"1E"
 
constant ALU_IDLE : OPCODE_TYPE := "10000"; -- x"10"
constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"12"
constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"13"
constant ALU_UPP2 : OPCODE_TYPE := "10010"; -- x"11"
constant ALU_RFLG : OPCODE_TYPE := "10011"; -- x"12"
 
constant FL_ZERO : integer := 0;
constant FL_CARRY : integer := 1;
385,17 → 384,15
Flags_D(FL_NEG) <= Sum(7);
 
when ALU_STP => -- Sets bit(n) in the Flags register
Flags_D(Index) <= '1';
Flags_D(Index) <= '1';
 
when ALU_BTT => -- Z = !R0(N), N = R0(7)
Flags_D(FL_ZERO) <= not Regfile(0)(Index);
Flags_D(FL_NEG) <= Regfile(0)(7);
-- Temp := "0" & Regfile(Index);
-- Flags_D(FL_ZERO) <= '0';
-- if( Temp(7 downto 0) = 0 )then
-- Flags_D(FL_ZERO) <= '1';
-- end if;
-- Flags_D(FL_NEG) <= Temp(7);
when ALU_BTT => -- Tests if R0 is negative or zero. No change to R0
Temp := "0" & Regfile(Index);
Flags_D(FL_ZERO) <= '0';
if( Temp(7 downto 0) = 0 )then
Flags_D(FL_ZERO) <= '1';
end if;
Flags_D(FL_NEG) <= Temp(7);
 
when ALU_CLP => -- Clears bit(n) in the Flags register
Flags_D(Index) <= '0';
420,7 → 417,7
Flags_D(FL_CARRY) <= Sum(8);
Flags_D(FL_NEG) <= Sum(7);
 
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags N,Z
Regfile_D(0) <= Mult(7 downto 0);
Regfile_D(1) <= Mult(15 downto 8);
Flags_D(FL_ZERO) <= '0';
467,9 → 464,9
end if;
end process;
 
S_Regs: process( Reset, Clock )
S_Regs: process( Reset_n, Clock )
begin
if( Reset = '1' )then
if( Reset_n = '0' )then
for i in 0 to 7 loop
Regfile(i) <= (others => '0');
end loop;
506,12 → 503,12
end if;
end process;
 
Program_Counter: process( Reset, Clock, Halt, PC_Ctrl, PC_Q, Rewind_1_2n )
Program_Counter: process( Reset_n, Clock, Halt, PC_Ctrl, PC_Q, Rewind_1_2n )
variable PC_Offset_SX : ADDRESS_TYPE := x"0000";
begin
PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));
PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;
if( Reset = '1' )then
if( Reset_n = '0' )then
PC_Q <= Program_Start_Addr;
elsif( rising_edge(Clock) )then
if( Halt = '0' )then
542,9 → 539,9
 
SP <= SP_Q;
 
Stack_Pointer: process( Reset, Clock )
Stack_Pointer: process( Reset_n, Clock )
begin
if( Reset = '1' )then
if( Reset_n = '0' )then
SP_Q <= Stack_Start_Addr;
elsif( rising_edge(Clock) )then
if( Halt = '0' )then
669,9 → 666,9
end if;
end process;
 
S_Regs: process( Reset, Clock )
S_Regs: process( Reset_n, Clock )
begin
if( Reset = '1' )then
if( Reset_n = '0' )then
Int_Req <= '0';
Pending <= x"00";
Wait_for_FSM <= '0';
692,16 → 689,16
elsif( Int_Trig = '1' )then
Wait_for_FSM <= '1';
end if;
if( INT_Ctrl.Mask_Set = '1' )then
if( INT_Ctrl.Mask_Set = '1' )then
Mask <= INT_Ctrl.Mask_Data(7 downto 1);
end if;
ISR_Q <= ISR_D;
if( Int_Trig = '1' )then
History(Hist_Ptr+1) <= Hist_Level;
Hist_Ptr <= Hist_Ptr + 1;
elsif( Int_RTI = '1' and Hist_Ptr > 0 )then
Hist_Ptr <= Hist_Ptr - 1;
end if;
end if;
ISR_Q <= ISR_D;
if( Int_Trig = '1' )then
History(Hist_Ptr+1) <= Hist_Level;
Hist_Ptr <= Hist_Ptr + 1;
elsif( Int_RTI = '1' and Hist_Ptr > 0 )then
Hist_Ptr <= Hist_Ptr - 1;
end if;
end if;
end if;
end process;
1328,9 → 1325,9
 
end process;
 
S_Regs: process( Reset, Clock )
S_Regs: process( Reset_n, Clock )
begin
if( Reset = '1' )then
if( Reset_n = '0' )then
CPU_State <= PIPE_FILL_0;
Opcode <= OP_INC;
SubOp <= ACCUM;
1478,9 → 1475,9
end loop;
end process;
 
S_Regs: process( Reset, Clock )
S_Regs: process( Reset_n, Clock )
begin
if( Reset = '1' )then
if( Reset_n = '0' )then
Wr_Data <= (others => '0');
Wr_Enable <= '0';
Rd_Enable <= '1';
1495,5 → 1492,4
 
end block;
 
end rtl;
 
end rtl;
/Open8_pkg.vhd
65,4 → 65,4
end Open8_pkg;
 
package body Open8_pkg is
end package body;
end package body;

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