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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 185 to Rev 186
    ↔ Reverse comparison
  •

Rev 185 → Rev 186

/Open8_pkg.vhd
130,8 → 130,8
constant OP_LDO : OPCODE_TYPE := "11111";
 
-- OP_STK uses the lower 3 bits to further refine the instruction by
-- repurposing the source register field. These "sub opcodes" are
-- take the place of the register select for the OP_STK opcode
-- repurposing the source register field. These "sub opcodes" take
-- the place of the register select for the OP_STK opcode
constant SOP_RSP : SUBOP_TYPE := "000";
constant SOP_RTS : SUBOP_TYPE := "001";
constant SOP_RTI : SUBOP_TYPE := "010";
156,7 → 156,8
-- Stack
PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
-- Subroutines & Interrupts
WAIT_FOR_INT, ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
WAIT_FOR_INT,
ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6,
-- Debugging
BRK_C1 );
238,4 → 239,22
constant PSR_N : integer := 2;
constant PSR_I : integer := 3;
constant PSR_GP4 : integer := 4;
constant PSR_GP5 :
constant PSR_GP5 : integer := 5;
constant PSR_GP6 : integer := 6;
constant PSR_GP7 : integer := 7;
 
type ALU_CTRL_TYPE is record
Oper : OPCODE_TYPE;
Reg : SUBOP_TYPE;
end record;
 
constant ACCUM : SUBOP_TYPE := "000";
 
type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
 
subtype FLAG_TYPE is DATA_TYPE;
 
end Open8_pkg;
 
package body Open8_pkg is
end package body;
/o8_cpu.vhd
406,7 → 406,6
 
when SOP_RTS | SOP_RTI =>
CPU_Next_State <= RTS_C1;
Cache_Ctrl <= CACHE_IDLE;
SP_Ctrl.Oper <= SP_POP;
 
when SOP_BRK =>
507,6 → 506,19
 
end case;
 
if( Int_Req = '1' )then
CPU_Next_State <= ISR_C1;
Cache_Ctrl <= CACHE_IDLE;
-- Rewind the PC by 3 to compensate for the pipeline registers
PC_Ctrl.Offset <= PC_REV3;
-- Reset all of the sub-block controls to IDLE, to avoid unintended
-- operation due to the current instruction
ALU_Ctrl.Oper <= ALU_IDLE;
SP_Ctrl.Oper <= SP_IDLE;
DP_Ctrl.Src <= DATA_RD_MEM;
INT_Ctrl.Soft_Ints <= (others => '0');
end if;
 
-------------------------------------------------------------------------------
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
-------------------------------------------------------------------------------
695,8 → 707,15
-- Subroutines & Interrupts (RTS, JSR)
-------------------------------------------------------------------------------
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr
CPU_Next_State <= WAIT_FOR_INT;
DP_Ctrl.Src <= DATA_BUS_IDLE;
if( Int_Req = '1' )then
CPU_Next_State <= ISR_C1;
-- Rewind the PC by 3 to compensate for the pipeline registers
PC_Ctrl.Offset <= PC_REV3;
-- Reset all of the sub-block controls to IDLE, to avoid unintended
-- operation due to the current instruction
DP_Ctrl.Src <= DATA_RD_MEM;
end if;
 
when ISR_C1 =>
CPU_Next_State <= ISR_C2;
773,24 → 792,6
null;
end case;
 
-- Interrupt service routines can only begin during the decode and wait
-- states to avoid corruption due to incomplete instruction execution
if( Int_Req = '1' )then
if( CPU_State = INSTR_DECODE or CPU_State = WAIT_FOR_INT )then
CPU_Next_State <= ISR_C1;
Cache_Ctrl <= CACHE_IDLE;
-- Rewind the PC by 3 to compensate for the pipeline registers
PC_Ctrl.Offset <= PC_REV3;
-- Reset all of the sub-block controls to IDLE, to avoid unintended
-- operation due to the current instruction
ALU_Ctrl.Oper <= ALU_IDLE;
SP_Ctrl.Oper <= SP_IDLE;
DP_Ctrl.Src <= DATA_RD_MEM;
INT_Ctrl.Soft_Ints <= (others => '0');
 
end if;
end if;
 
end process;
 
-------------------------------------------------------------------------------
1177,4 → 1178,8
begin
if( rising_edge(Clock) )then
Mult <= Regfile(0) *
Regfile(conv_integer(ALU_Ctrl.Reg));
end if;
end process;
 
end architecture;

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