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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 190 to Rev 191
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  •

Rev 190 → Rev 191

/Open8_pkg.vhd
70,6 → 70,8
constant EXT_GP6 : integer := 2;
constant EXT_GP7 : integer := 3;
 
constant OPEN8_NULLBUS : DATA_TYPE := x"00";
 
-- Component declaration
-- (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
component o8_cpu is
/button_db.vhd
0,0 → 1,118
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : button_db
-- Description: Debounces a single button/switch and provides a change of
-- state signal as well as registered level.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
 
entity button_db is
generic(
Button_Level : std_logic;
Reset_Level : std_logic
);
port(
Clock : in std_logic;
Reset : in std_logic;
mSec_Tick : in std_logic;
--
Button_In : in std_logic;
--
Button_Pressed : out std_logic;
Button_CoS : out std_logic
);
end entity;
 
architecture behave of button_db is
 
signal Button_SR : std_logic_vector(2 downto 0);
alias Button_In_q is Button_SR(2);
 
signal Button_Dn_Tmr : std_logic_vector(5 downto 0);
signal Button_Dn : std_logic;
 
signal Button_Up_Tmr : std_logic_vector(5 downto 0);
signal Button_Up : std_logic;
 
signal Button_State : std_logic;
signal Button_State_q : std_logic;
 
begin
 
Button_Pressed <= Button_State_q;
 
Button_trap: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Button_SR <= (others => '0');
 
Button_Dn_Tmr <= (others => '0');
Button_Dn <= '0';
 
Button_Up_Tmr <= (others => '0');
Button_Up <= '0';
 
Button_State <= '0';
Button_State_q <= '0';
 
Button_CoS <= '0';
elsif( rising_edge(Clock) )then
Button_SR <= Button_SR(1 downto 0) & Button_In;
 
Button_Dn_Tmr <= (others => '0');
Button_Dn <= '0';
if( Button_In_q = Button_Level )then
Button_Dn_Tmr <= Button_Dn_Tmr + mSec_Tick;
if( and_reduce(Button_Dn_Tmr) = '1' )then
Button_Dn_Tmr <= Button_Dn_Tmr;
Button_Dn <= '1';
end if;
end if;
 
Button_Up_Tmr <= (others => '0');
Button_Up <= '0';
if( Button_In_q = not Button_Level )then
Button_Up_Tmr <= Button_Up_Tmr + mSec_Tick;
if( and_reduce(Button_Up_Tmr) = '1' )then
Button_Up_Tmr <= Button_Up_Tmr;
Button_Up <= '1';
end if;
end if;
 
if( Button_Dn = '1' )then
Button_State <= '1';
elsif( Button_Up = '1' )then
Button_State <= '0';
end if;
 
Button_State_q <= Button_State;
Button_CoS <= Button_State xor Button_State_q;
 
end if;
end process;
 
end architecture;
/o8_alu16.vhd
1,4 → 1,4
-- Copyright (c)2013 Jeremy Seth Henry
-- Copyright (c)2006, 2015, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
29,7 → 29,7
-- : offset 0x1F.
-- : The math unit is busy when the MSB of the status
-- : register is high, and done/ready when it reads low.
-- : Almost Equal checks to see if Addend 1 is no more, or less
-- : Almost Equal checks to see if Addend 1 is no more, or less,
-- : addend 2 within the specified tolerance. For example,
-- : addend_1 = 2 is almost equal to addend_2 = -1 with a
-- : tolerance of 3, but not a tolerance of 1. Actual function is
37,7 → 37,7
-- : This is an inherently signed function.
-- : Signed Overflow/Underflow is logically equivalent to
-- : S_Sum/Dif(16) xor S_Sum/Dif(15), since the apparent result
-- : changes sign while the internal sign bit does not. For example
-- : changes sign while the internal sign bit doesn't. For example
-- : |8000| will result in (-)8000 due to the way the internal
-- : logic handles sign extension. Thus, the O bit should be
-- : checked when performing signed math
47,11 → 47,11
-- : Byte and Word. Note that conversion times are fairly long,
-- : since we are repeatedly issuing division commands, but it is
-- : still faster than software emulation.
-- : The Byte conversion only operates on the lower 8 bits, and sets
-- : the Z and N flags. The N flag is only set when SDAB is used
-- : and the signed value of the register is negative. The O bit is
-- : set if the upper byte of the register is non-zero, but does
-- : not actually result in an calculation error.
-- : The Byte conversion only operates on the lower 8 bits, and
-- : sets the Z and N flags. The N flag is only set when SDAB is
-- : used and the signed value of the register is negative. The O
-- : bit is set if the upper byte of the register is non-zero, but
-- : does not actually result in an calculation error.
-- : Examples:
-- : UDAB 0x00FE -> 0x0254, Flags -> 0x0
-- : SDAB 0x00FE -> 0x0002, Flags -> 0x4
62,7 → 62,7
-- : Examples:
-- : UDAW 0xD431 -> 0x4321, Flags -> 0x5 ('0', MSB, MSB-1, MSB-2)
-- : SDAW 0xD431 -> 0x1216, Flags -> 0x5 ('0', N , MSB , MSB-1)
 
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA Register 0 ( 7:0) (RW)
95,15 → 95,15
-- 0x1B -------- Reserved (--)
-- 0x1C AAAAAAAA Tolerance ( 7:0) (RW)
-- 0x1D AAAAAAAA Tolerance (15:8) (RW)
-- 0x1E E---DCBA Status & Flags (RW)
-- 0x1E BBBBBAAA Instruction Register (RW)
-- A = Operand (register select)
-- B = Opcode (instruction select)
-- 0x1F E---DCBA Status & Flags (RW)
-- A = Zero Flag
-- B = Carry Flag
-- C = Negative Flag
-- D = Overflow / Error Flag
-- E = Busy Flag (1 = busy, 0 = idle)
-- 0x1F BBBBBAAA Instruction Register (RW)
-- A = Operand (register select)
-- B = Opcode (instruction select)
--
-- Instruction Map:
-- OP_T0X "0000 0xxx" : Transfer R0 to Rx R0 -> Rx (Sets Z,N)
147,6 → 147,13
-- OP_BROL "1110 1xxx" : Logical Rotate Left Rx<<1,C -> Rx,C
-- OP_BSFR "1111 0xxx" : Logical Shift Right 0,Rx>>1 -> Rx
-- OP_BROR "1111 1xxx" : Logical Rotate Right C,Rx>>1 -> Rx,C
--
-- Revision History
-- Author Date Change
------------------ -------- --------------------------------------------------
-- Seth Henry 07/19/06 Design Start
-- Seth Henry 03/13/15 Added "Almost Equal" instruction
-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
 
library ieee;
use ieee.std_logic_1164.all;
236,7 → 243,8
constant OP_BROR : std_logic_vector(4 downto 0) := "11111";
-------------------------------------------------------------------
 
constant User_Addr : std_logic_vector(15 downto 5):= Address(15 downto 5);
constant User_Addr : std_logic_vector(15 downto 5):=
Address(15 downto 5);
alias Comp_Addr is Bus_Address(15 downto 5);
signal Reg_Addr : std_logic_vector(4 downto 0);
 
308,11 → 316,11
signal IDIV_Start : std_logic;
signal IDIV_Busy : std_logic;
 
constant N : integer := 16; -- Width of Operands
constant DIV_WIDTH : integer := 16; -- Width of Operands
 
signal q : std_logic_vector(N*2-1 downto 0);
signal diff : std_logic_vector(N downto 0);
signal count : integer range 0 to N + 1;
signal q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
signal diff : std_logic_vector(DIV_WIDTH downto 0);
signal count : integer range 0 to DIV_WIDTH + 1;
 
signal Quotient_i : std_logic_vector(15 downto 0);
signal Quotient : std_logic_vector(15 downto 0);
346,9 → 354,10
DAA_result <= DAA_p4 & DAA_p3 & DAA_p2 & DAA_p1 & DAA_p0;
 
-- Combinational logic for the division logic
diff <= ('0' & Q(N*2-2 downto N-1)) - ('0' & Divisor);
Quotient_i <= q(N-1 downto 0);
Remainder_i <= q(N*2-1 downto N);
diff <= ('0' & Q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
('0' & Divisor);
Quotient_i <= q(DIV_WIDTH-1 downto 0);
Remainder_i <= q(DIV_WIDTH*2-1 downto DIV_WIDTH);
 
ALU_proc: process( Clock, Reset )
variable Reg_Sel : integer;
358,7 → 367,7
Wr_En <= '0';
Wr_Data_q <= (others => '0');
Rd_En <= '0';
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Reg_Addr <= (others => '0');
Opcode <= (others => '0');
Operand_Sel <= (others => '0');
389,7 → 398,7
DAA_p2 <= (others => '0');
IDIV_Start <= '0';
q <= (others => '0');
count <= N;
count <= DIV_WIDTH;
IDIV_Busy <= '0';
elsif( rising_edge(Clock) )then
-- For convenience, convert these to integers and assign them to
420,19 → 429,18
when "11101" => -- 0x1D -> Tolerance.u
Tolerance(15 downto 8) <= Wr_Data_q;
 
when "11110" => -- 0x1E -> Status register
null;
 
when "11111" => -- 0x1F -> Control register
Start <= '1';
when "11110" => -- 0x1E -> Opcode register
Opcode <= Wr_Data_q(7 downto 3);
Operand_Sel <= Wr_Data_q(2 downto 0);
 
when "11111" => -- 0x1F -> Status/Start register
Start <= '1';
 
when others => null;
end case;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
 
if( Rd_En = '1' )then
447,10 → 455,11
Rd_Data <= Tolerance(7 downto 0);
when "11101" => -- 0x1D -> Tolerance.u
Rd_Data <= Tolerance(15 downto 8);
when "11110" => -- 0x1E -> Flags & Status register
when "11110" => -- 0x1E -> Opcode register
Rd_Data <= Opcode & Operand_Sel;
when "11111" => -- 0x1F -> Flags & Status register
Rd_Data <= Busy & "000" & Flags;
when "11111" => -- 0x1F -> Control register
Rd_Data <= Opcode & Operand_Sel;
 
when others => null;
end case;
end if;
464,7 → 473,7
alu_ctrl <= LOAD;
end if;
 
-- Load the operands from the register file. We also check for specific
-- Load the operands from the reg file. We also check for specific
-- opcodes to set the DAA mode (signed vs unsigned). This is the only
-- place where we READ the register file outside of the bus interface
when LOAD =>
515,19 → 524,25
s_accum <= S_Addend_1 + S_Addend_2;
 
when OP_UADD =>
u_accum <= ('0' & Operand_1) + ('0' & Operand_2);
u_accum <= ('0' & Operand_1) +
('0' & Operand_2);
 
when OP_UADC =>
u_accum <= ('0' & Operand_1) + ('0' & Operand_2) + Flags(FLAG_C);
u_accum <= ('0' & Operand_1) +
('0' & Operand_2) +
Flags(FLAG_C);
 
when OP_SSUB | OP_SCMP =>
s_accum <= S_Addend_1 - S_Addend_2;
s_accum <= S_Addend_1 - S_Addend_2;
 
when OP_USUB | OP_UCMP =>
u_accum <= ('0' & U_Addend_1) - ('0' & U_Addend_2);
u_accum <= ('0' & U_Addend_1) -
('0' & U_Addend_2);
 
when OP_USBC =>
u_accum <= ('0' & U_Addend_1) - ('0' & U_Addend_2) - Flags(FLAG_C);
u_accum <= ('0' & U_Addend_1) -
('0' & U_Addend_2) -
Flags(FLAG_C);
 
when OP_ACMP =>
-- Perform the function
563,9 → 578,9
when OP_BXOR =>
u_accum <= '0' & (U_Operand_1 xor U_Operand_2);
 
-- Division unit has a longer latency, so we need to wait for its busy
-- signal to return low before storing results. Trigger the engine,
-- and then jump to the wait state for it to finish
-- Division unit has a longer latency, so we need to wait for its busy
-- signal to return low before storing results. Trigger the engine,
-- and then jump to the wait state for it to finish
when OP_IDIV =>
IDIV_Start<= '1';
alu_ctrl <= IDIV_INIT;
777,13 → 792,15
if( IDIV_Start = '1' )then
IDIV_Busy <= '1';
count <= 0;
q <= conv_std_logic_vector(0,N) & Dividend;
elsif( count < N )then
q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
elsif( count < DIV_WIDTH )then
IDIV_Busy <= '1';
count <= count + 1;
q <= diff(N-1 downto 0) & q(N-2 downto 0) & '1';
if( diff(N) = '1' )then
q <= q(N*2-2 downto 0) & '0';
q <= diff(DIV_WIDTH-1 downto 0) &
q(DIV_WIDTH-2 downto 0) &
'1';
if( diff(DIV_WIDTH) = '1' )then
q <= q(DIV_WIDTH*2-2 downto 0) & '0';
end if;
end if;
 
/o8_btn_int.vhd
1,4 → 1,4
-- Copyright (c)2013 Jeremy Seth Henry
-- Copyright (c)2013, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
18,8 → 18,8
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_btn_int
-- Description: Detects and reports when a user pushbutton is pressed with an
26,9 → 26,10
-- interrupt.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
35,22 → 36,22
 
entity o8_btn_int is
generic(
Button_Level : std_logic;
Address : ADDRESS_TYPE;
Reset_Level : std_logic
Num_Buttons : integer range 1 to 8 := 8;
Button_Level : std_logic := '0';
Address : ADDRESS_TYPE := x"0000";
Reset_Level : std_logic := '1'
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : in std_logic;
Clock : in std_logic := '0';
Reset : in std_logic := '0';
uSec_Tick : in std_logic := '0';
--
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Bus_Address : in ADDRESS_TYPE := x"0000";
Rd_Enable : in std_logic := '0';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
Button1_In : in std_logic;
Button2_In : in std_logic
Button_In : in DATA_TYPE := x"00"
);
end entity;
 
61,154 → 62,68
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
 
signal Button1_SR : std_logic_vector(2 downto 0);
alias Button1_In_q is Button1_SR(2);
constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
conv_std_logic_vector(1000,10);
 
signal Button1_Dn_Tmr : std_logic_vector(7 downto 0);
signal Button1_Dn : std_logic;
signal mSec_Timer : std_logic_vector(9 downto 0);
signal mSec_Tick : std_logic;
 
signal Button1_Up_Tmr : std_logic_vector(7 downto 0);
signal Button1_Up : std_logic;
signal Button_Pressed : DATA_TYPE := x"00";
signal Button_CoS : DATA_TYPE := x"00";
 
signal Button1_State : std_logic;
signal Button1_State_q: std_logic;
 
signal Button1_Int : std_logic;
 
signal Button2_SR : std_logic_vector(2 downto 0);
alias Button2_In_q is Button2_SR(2);
 
signal Button2_Dn_Tmr : std_logic_vector(7 downto 0);
signal Button2_Dn : std_logic;
 
signal Button2_Up_Tmr : std_logic_vector(7 downto 0);
signal Button2_Up : std_logic;
 
signal Button2_State : std_logic;
signal Button2_State_q: std_logic;
 
signal Button2_Int : std_logic;
 
begin
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= x"00";
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
Rd_En <= Addr_Match;
Rd_Data <= (others => '0');
Rd_En <= Addr_Match;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data(6) <= Button1_State;
Rd_Data(7) <= Button2_State;
Rd_Data <= Button_Pressed;
end if;
 
Interrupt <= or_reduce(Button_CoS);
end if;
end process;
 
Interrupt <= Button1_Int or Button2_Int;
 
Button1_trap: process( Clock, Reset )
mSec_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Button1_SR <= (others => '0');
 
Button1_Dn_Tmr <= (others => '0');
Button1_Dn <= '0';
 
Button1_Up_Tmr <= (others => '0');
Button1_Up <= '0';
 
Button1_State <= '0';
Button1_State_q <= '0';
 
Button1_Int <= '0';
mSec_Timer <= (others => '0');
mSec_Tick <= '0';
elsif( rising_edge(Clock) )then
Button1_SR <= Button1_SR(1 downto 0) & Button1_In;
 
Button1_Dn_Tmr <= (others => '0');
Button1_Dn <= '0';
if( Button1_In_q = Button_Level )then
Button1_Dn_Tmr <= Button1_Dn_Tmr + uSec_Tick;
if( and_reduce(Button1_Dn_Tmr) = '1' )then
Button1_Dn_Tmr<= Button1_Dn_Tmr;
Button1_Dn <= '1';
end if;
mSec_Timer <= mSec_Timer - uSec_Tick;
mSec_Tick <= '0';
if( mSec_Timer = 0 )then
mSec_Timer <= MSEC_DELAY;
mSec_Tick <= '1';
end if;
 
Button1_Up_Tmr <= (others => '0');
Button1_Up <= '0';
if( Button1_In_q = not Button_Level )then
Button1_Up_Tmr <= Button1_Up_Tmr + uSec_Tick;
if( and_reduce(Button1_Up_Tmr) = '1' )then
Button1_Up_Tmr<= Button1_Up_Tmr;
Button1_Up <= '1';
end if;
end if;
 
if( Button1_Dn = '1' )then
Button1_State <= '1';
elsif( Button1_Up = '1' )then
Button1_State <= '0';
end if;
 
Button1_State_q <= Button1_State;
Button1_Int <= Button1_State xor Button1_State_q;
 
end if;
end process;
 
Button2_trap: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Button2_SR <= (others => '0');
Create_Debouncers: for i in 0 to Num_Buttons - 1 generate
 
Button2_Dn_Tmr <= (others => '0');
Button2_Dn <= '0';
U_BTN : entity work.button_db
generic map(
Button_Level => Button_Level,
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
mSec_Tick => mSec_Tick,
--
Button_In => Button_In(i),
--
Button_Pressed => Button_Pressed(i),
Button_CoS => Button_CoS(i)
);
 
Button2_Up_Tmr <= (others => '0');
Button2_Up <= '0';
end generate;
 
Button2_State <= '0';
Button2_State_q <= '0';
 
Button2_Int <= '0';
elsif( rising_edge(Clock) )then
Button2_SR <= Button2_SR(1 downto 0) & Button2_In;
 
Button2_Dn_Tmr <= (others => '0');
Button2_Dn <= '0';
if( Button2_In_q = Button_Level )then
Button2_Dn_Tmr <= Button2_Dn_Tmr + uSec_Tick;
if( and_reduce(Button2_Dn_Tmr) = '1' )then
Button2_Dn_Tmr<= Button2_Dn_Tmr;
Button2_Dn <= '1';
end if;
end if;
 
Button2_Up_Tmr <= (others => '0');
Button2_Up <= '0';
if( Button2_In_q = not Button_Level )then
Button2_Up_Tmr <= Button2_Up_Tmr + uSec_Tick;
if( and_reduce(Button2_Up_Tmr) = '1' )then
Button2_Up_Tmr<= Button2_Up_Tmr;
Button2_Up <= '1';
end if;
end if;
 
if( Button2_Dn = '1' )then
Button2_State <= '1';
elsif( Button2_Up = '1' )then
Button2_State <= '0';
end if;
 
Button2_State_q <= Button2_State;
Button2_Int <= Button2_State xor Button2_State_q;
 
end if;
end process;
 
end architecture;
/o8_clk_detect.vhd
26,10 → 26,9
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 BB-----A VSD Engine PLL Reset (RO/RW)
-- A = Interrupt Enable (1 = enabled, 0 = masked) (RW)
-- B = Clock Line State (follows input, only valid if B = 1) (RO)
-- C = Clock Detect (1 = transition detected) (RO)
-- 0x00 BA------ VSD Engine PLL Reset (RO/RW)
-- A = Clock Line State (follows input) (RO)
-- B = Clock Detect (1 = transition detected) (RO)
 
library ieee;
use ieee.std_logic_1164.all;
42,88 → 41,64
 
entity o8_clk_detect is
generic(
Threshold_Count : integer;
Address : ADDRESS_TYPE;
Reset_Level : std_logic
Threshold_Count : integer;
Address : ADDRESS_TYPE;
Reset_Level : std_logic
);
port(
Clock : in std_logic;
Reset : in std_logic;
Clock : in std_logic;
Reset : in std_logic;
--
Ref_Clk_In : in std_logic;
Ref_Clk_In : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
end entity;
 
architecture behave of o8_clk_detect is
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
signal Addr_Match : std_logic;
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Wr_Data_Q : DATA_TYPE;
signal Wr_En : std_logic;
signal Rd_En : std_logic;
signal Rd_En : std_logic := '0';
 
signal Int_En : std_logic;
 
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end function;
 
constant Threshold_bits : integer := ceil_log2(Threshold_Count);
constant THRESHOLD : std_logic_vector(Threshold_bits - 1 downto 0) :=
conv_std_logic_vector(Threshold_Count,Threshold_bits);
 
signal RE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0);
signal FE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0);
signal RE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0) :=
(others => '0');
signal FE_Threshold_Ctr : std_logic_vector(Threshold_Bits - 1 downto 0) :=
(others => '0');
 
signal Ref_In_SR : std_logic_vector(3 downto 0);
signal Ref_In_SR : std_logic_vector(3 downto 0) := (others => '0');
alias Ref_In_q1 is Ref_In_SR(2);
alias Ref_In_q2 is Ref_In_SR(3);
signal Ref_In_RE : std_logic;
signal Ref_In_FE : std_logic;
signal Ref_In_RE : std_logic := '0';
signal Ref_In_FE : std_logic := '0';
 
signal Ref_Detect : std_logic;
signal Ref_Detect_q1 : std_logic;
signal Ref_Detect_CoS : std_logic;
signal Ref_Detect : std_logic := '0';
signal Ref_Detect_q1 : std_logic := '0';
signal Ref_Detect_CoS : std_logic := '0';
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_Data_Q <= x"00";
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= x"00";
Int_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_Data_Q <= Wr_Data;
Wr_En <= Wr_Enable and Addr_Match;
Rd_En <= Rd_Enable and Addr_Match;
Rd_En <= Addr_Match;
 
if( Wr_En = '1' )then
Int_En <= Wr_Data_Q(0);
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data(0) <= Int_En;
Rd_Data(6) <= Ref_In_q2;
Rd_Data(7) <= Ref_Detect;
end if;
166,7 → 141,7
Ref_Detect_q1 <= Ref_Detect;
Ref_Detect_CoS <= Ref_Detect xor Ref_Detect_q1;
 
Interrupt <= Ref_Detect_CoS and Int_En;
Interrupt <= Ref_Detect_CoS;
end if;
end process;
 
/o8_cpu.vhd
881,7 → 881,7
 
CPU_Halt_Req <= '0';
 
Wr_Data <= x"00";
Wr_Data <= OPEN8_NULLBUS;
Wr_Enable <= '0';
Rd_Enable <= '1';
 
914,7 → 914,7
CPU_Halt_Req <= CPU_Halt;
 
Wr_Enable <= '0';
Wr_Data <= x"00";
Wr_Data <= OPEN8_NULLBUS;
Rd_Enable <= '0';
 
-------------------------------------------------------------------------------
/o8_crc16_ccitt.vhd
107,10 → 107,10
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Rd_En <= '0';
Rd_Data <= x"00";
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Byte_Count <= x"00";
Calc_En <= '0';
118,39 → 118,11
Data <= x"00";
Reg <= x"0000";
elsif( rising_edge(Clock) )then
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Rd_Enable;
Reg_Sel <= Reg_Addr;
 
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Reg_Sel <= Reg_Addr;
 
Calc_En <= '0';
Buffer_En <= Calc_En;
 
if( Calc_En = '1' )then
Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
Reg(4) <= Reg(12) xor Exr(1) ;
Reg(5) <= Reg(13) xor Exr(2) ;
Reg(6) <= Reg(14) xor Exr(3) ;
Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
Reg(11) <= Exr(3) ;
Reg(12) <= Exr(4) xor Exr(0);
Reg(13) <= Exr(5) xor Exr(1);
Reg(14) <= Exr(6) xor Exr(2);
Reg(15) <= Exr(7) xor Exr(3);
end if;
 
if( Buffer_En = '1' )then
Byte_Count <= Byte_Count + 1;
Comp_Data <= Reg xor x"FFFF";
end if;
 
if( Wr_En = '1' )then
case( Reg_Sel )is
when "00" => -- Load next byte
165,6 → 137,8
end case;
end if;
 
Rd_En <= Addr_Match and Rd_Enable;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
case( Reg_Sel )is
when "00" => -- Read last byte
183,6 → 157,33
end case;
end if;
 
Calc_En <= '0';
Buffer_En <= Calc_En;
 
if( Calc_En = '1' )then
Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
Reg(4) <= Reg(12) xor Exr(1) ;
Reg(5) <= Reg(13) xor Exr(2) ;
Reg(6) <= Reg(14) xor Exr(3) ;
Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
Reg(11) <= Exr(3) ;
Reg(12) <= Exr(4) xor Exr(0);
Reg(13) <= Exr(5) xor Exr(1);
Reg(14) <= Exr(6) xor Exr(2);
Reg(15) <= Exr(7) xor Exr(3);
end if;
 
if( Buffer_En = '1' )then
Byte_Count <= Byte_Count + 1;
Comp_Data <= Reg xor x"FFFF";
end if;
 
end if;
end process;
 
/o8_datalatch.vhd
85,7 → 85,7
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
Strobe_sr <= (others => '0');
Interrupt <= '0';
LData_q1 <= x"00";
101,7 → 101,7
LData_q3 <= LData_q2;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match;
if( Rd_En = '1' )then
Rd_Data <= LData_q3;
/o8_epoch_timer.vhd
109,7 → 109,7
Reg_Addr_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
epoch_tmr <= epoch_tmr + uSec_Tick;
157,7 → 157,7
-- Fire on rising edge of epoch_alarm
Interrupt <= epoch_alarm and not epoch_alarm_q;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
/o8_gpin.vhd
62,7 → 62,7
alias Comp_Addr is Bus_Address(15 downto 0);
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
 
signal GPIN_q1 : DATA_TYPE;
signal GPIN_q2 : DATA_TYPE;
signal User_In : DATA_TYPE;
75,7 → 75,7
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
GPIN_q1 <= x"00";
GPIN_q2 <= x"00";
User_In <= x"00";
84,7 → 84,7
GPIN_q2 <= GPIN_q1;
User_In <= GPIN_q2;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match;
if( Rd_En = '1' )then
Rd_Data <= User_In;
/o8_gpio.vhd
77,7 → 77,7
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
if( not Input_Only )then
Wr_En <= '0';
Wr_Data_q <= x"00";
103,7 → 103,7
 
User_In <= GPIO;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
if( Input_Only )then
/o8_gpout.vhd
81,7 → 81,7
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
User_Out <= Default_Out;
if( not Disable_Tristate)then
User_En <= Default_En;
102,7 → 102,7
end if;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
Rd_Data <= User_Out;
/o8_hd44780_4b.vhd
260,7 → 260,7
Wr_Data_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
 
Reg_Valid <= '0';
Reg_Sel <= '0';
290,7 → 290,7
end case;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
/o8_hd44780_8b.vhd
52,18 → 52,18
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
signal Addr_Match : std_logic;
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(1 downto 0);
signal Reg_Addr_q : std_logic_vector(1 downto 0);
signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
 
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
 
signal Reg_Valid : std_logic;
signal Reg_Sel : std_logic;
signal Reg_Data : std_logic_vector(7 downto 0);
signal Reg_Valid : std_logic := '0';
signal Reg_Sel : std_logic := '0';
signal Reg_Data : DATA_TYPE := x"00";
 
signal Tx_Ready : std_logic;
 
110,7 → 110,7
constant LCD_CONFIG5 : std_logic_vector(7 downto 0) := x"2A"; -- Print a "*"
constant LCD_CONFIG6 : std_logic_vector(7 downto 0) := x"02"; -- Reset the cursor
 
signal init_count : std_logic_vector(2 downto 0);
signal init_count : std_logic_vector(2 downto 0) := (others => '0');
 
constant INIT_40MS : integer := 40000;
constant INIT_BITS : integer := ceil_log2(INIT_40MS);
129,7 → 129,7
constant BUSY_DELAY : std_logic_vector(INIT_BITS-1 downto 0) :=
conv_std_logic_vector(BUSY_50US-1, INIT_BITS);
 
signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
 
constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
constant SNH_BITS : integer := ceil_log2(SNH_600NS);
136,7 → 136,7
constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
 
signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0);
signal io_timer : std_logic_vector(SNH_BITS - 1 downto 0) := (others => '0');
 
type IO_STATES is (INIT, FN_JUMP, IDLE,
WR_PREP, WR_SETUP, WR_HOLD,
144,8 → 144,8
ISSUE_INT );
signal io_state : IO_STATES;
 
signal LCD_Data : std_logic_vector(7 downto 0);
signal LCD_Addr : std_logic;
signal LCD_Data : std_logic_vector(7 downto 0) := x"00";
signal LCD_Addr : std_logic := '0';
 
--------------------------------------------------------------------------------
-- Backlight & Contrast signals
200,47 → 200,47
 
constant CB : integer := ceil_log2(DIV_WIDTH);
 
signal LCD_Contrast : std_logic_vector(7 downto 0);
signal LCD_Contrast : std_logic_vector(7 downto 0) := x"00";
 
signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0);
signal CN_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
 
signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
signal CN_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
signal CN_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
 
signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
signal CN_diff : std_logic_vector(DIV_WIDTH downto 0);
signal CN_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
signal CN_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
 
signal CN_count : std_logic_vector(CB-1 downto 0);
signal CN_count : std_logic_vector(CB-1 downto 0) := (others => '0');
 
signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0);
signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0);
signal CN_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
signal CN_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
 
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0);
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0);
signal CN_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
signal CN_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
 
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0);
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0);
signal CN_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
signal CN_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
 
signal LCD_Bright : std_logic_vector(7 downto 0);
signal LCD_Bright : std_logic_vector(7 downto 0) := (others => '0');
 
signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0);
signal BL_DACin_q : std_logic_vector(DAC_WIDTH-1 downto 0) := (others => '0');
 
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0);
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0);
signal BL_Divisor : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
signal BL_Dividend : std_logic_vector(DIV_WIDTH-1 downto 0) := (others => '0');
 
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0);
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0);
signal BL_q : std_logic_vector(DIV_WIDTH*2-1 downto 0) := (others => '0');
signal BL_diff : std_logic_vector(DIV_WIDTH downto 0) := (others => '0');
 
signal BL_count : std_logic_vector(CB-1 downto 0);
signal BL_count : std_logic_vector(CB-1 downto 0) := (others => '0');
 
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0);
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0);
signal BL_Next_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
signal BL_Next_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
 
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0);
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0);
signal BL_PWM_Wdt : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
signal BL_PWM_Per : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
 
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0);
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0);
signal BL_Wdt_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
signal BL_Per_Ctr : std_logic_vector(DAC_Width-1 downto 0) := (others => '0');
 
begin
 
257,7 → 257,7
Wr_Data_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
 
Reg_Valid <= '0';
Reg_Sel <= '0';
287,7 → 287,7
end case;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
/o8_ltc2355_2p.vhd
0,0 → 1,233
-- VHDL units : ltc2355_2p
-- Description: Reads out a pair of LTC2355 14-bit ADCs which are wired with
-- : common clock and CONVERT START inputs. Because they are
-- : synchronized, this entity provides simultaneously updated
-- : parallel data buses.
--
-- Notes : Depends on the fact that the two LTC2355 converters are wired
-- : with their SCLK and CONV lines tied together, and DATA1 and
-- : DATA2 independently routed to separate I/O pins.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_ltc2355_2p is
generic(
Address : ADDRESS_TYPE;
Reset_Level : std_logic;
Sys_Freq : real
);
port(
Clock : in std_logic; -- 96MHz MAX for proper operation
Reset : in std_logic;
uSec_Tick : in std_logic;
-- Client IF
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
-- ADC IF
ADC_SCLK : out std_logic;
ADC_CONV : out std_logic;
ADC_DATA1 : in std_logic;
ADC_DATA2 : in std_logic
);
end entity;
 
architecture behave of o8_ltc2355_2p is
 
constant Divide_SCLK_by_2 : boolean := (Sys_Freq > 96000000.0);
 
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
alias Comp_Addr is Bus_Address(15 downto 3);
alias Reg_Sel is Bus_Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0);
signal Wr_Data_q : DATA_TYPE;
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Rd_En : std_logic;
signal User_In : DATA_TYPE;
 
signal User_Trig : std_logic;
 
signal Timer_Int : DATA_TYPE;
signal Timer_Cnt : DATA_TYPE;
signal Timer_Trig : std_logic;
 
type ADC_STATES is ( IDLE, START, CLK_HIGH, CLK_HIGH2, CLK_LOW, CLK_LOW2, UPDATE );
signal ad_state : ADC_STATES;
 
signal rx_buffer1 : std_logic_vector(16 downto 0);
signal rx_buffer2 : std_logic_vector(16 downto 0);
signal bit_cntr : std_logic_vector(4 downto 0);
constant BIT_COUNT : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(16,5);
 
signal ADC1_Data : std_logic_vector(13 downto 0);
signal ADC2_Data : std_logic_vector(13 downto 0);
signal ADC_Ready : std_logic;
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= (others => '0');
Wr_Data_q <= x"00";
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
User_Trig <= '0';
Timer_Int <= x"00";
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel;
Wr_Data_q <= Wr_Data;
Wr_En <= Wr_Enable and Addr_Match;
User_Trig <= '0';
if( Wr_En = '1' )then
if( Reg_Sel_q = "110" )then
Timer_Int <= Wr_Data_q;
end if;
if( Reg_Sel_q = "111" )then
User_Trig <= '1';
end if;
end if;
 
Rd_En <= Rd_Enable and Addr_Match;
Rd_Data <= OPEN8_NULLBUS;
 
if( Rd_En = '1' )then
case( Reg_Sel_q )is
-- Channel 1, Full resolution, lower byte
when "000" =>
Rd_Data <= ADC1_Data(7 downto 0);
-- Channel 1, Full resolution, upper byte
when "001" =>
Rd_Data <= "00" & ADC1_Data(13 downto 8);
-- Channel 2, Full resolution, lower byte
when "010" =>
Rd_Data <= ADC2_Data(7 downto 0);
-- Channel 2, Full resolution, upper byte
when "011" =>
Rd_Data <= "00" & ADC2_Data(13 downto 8);
-- Channel 1, 8-bit resolution
when "100" =>
Rd_Data <= ADC1_Data(13 downto 6);
-- Channel 2, 8-bit resolution
when "101" =>
Rd_Data <= ADC2_Data(13 downto 6);
-- Self-update rate
when "110" =>
Rd_Data <= Timer_Int;
-- Interface status
when "111" =>
Rd_Data(7) <= ADC_Ready;
when others =>
null;
end case;
end if;
end if;
end process;
 
Interval_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Timer_Cnt <= x"00";
Timer_Trig <= '0';
elsif( rising_edge(Clock) )then
Timer_Trig <= '0';
Timer_Cnt <= Timer_Cnt - uSec_Tick;
if( or_reduce(Timer_Cnt) = '0' )then
Timer_Cnt <= Timer_Int;
Timer_Trig <= or_reduce(Timer_Int); -- Only issue output on Int > 0
end if;
end if;
end process;
 
ADC_IO_FSM: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
ad_state <= IDLE;
ADC_Ready <= '0';
 
rx_buffer1 <= (others => '0');
rx_buffer2 <= (others => '0');
 
bit_cntr <= (others => '0');
 
ADC1_Data <= (others => '0');
ADC2_Data <= (others => '0');
 
ADC_SCLK <= '1';
ADC_CONV <= '0';
 
Interrupt <= '0';
elsif( rising_edge(Clock) )then
ADC_Ready <= '0';
ADC_SCLK <= '1';
ADC_CONV <= '0';
 
Interrupt <= '0';
 
case( ad_state )is
when IDLE =>
ADC_Ready <= '1';
if( (User_Trig or Timer_Trig) = '1' )then
ad_state <= START;
end if;
 
when START =>
ADC_SCLK <= '0';
ADC_CONV <= '1';
bit_cntr <= BIT_COUNT;
ad_state <= CLK_HIGH;
 
when CLK_HIGH =>
ad_state <= CLK_LOW;
if( Divide_SCLK_by_2 )then
ad_state <= CLK_HIGH2;
end if;
 
when CLK_HIGH2 =>
ad_state <= CLK_LOW;
 
when CLK_LOW =>
ADC_SCLK <= '0';
rx_buffer1(conv_integer(bit_cntr)) <= ADC_DATA1;
rx_buffer2(conv_integer(bit_cntr)) <= ADC_DATA2;
bit_cntr <= bit_cntr - 1;
ad_state <= CLK_HIGH;
if( bit_cntr = 0 )then
ad_state <= UPDATE;
elsif( Divide_SCLK_by_2 )then
ad_state <= CLK_LOW2;
end if;
 
when CLK_LOW2 =>
ADC_SCLK <= '0';
ad_state <= CLK_HIGH;
 
when UPDATE =>
ADC_SCLK <= '0';
ad_state <= IDLE;
ADC1_Data <= rx_buffer1(14 downto 1);
ADC2_Data <= rx_buffer2(14 downto 1);
Interrupt <= '1';
 
when others =>
null;
end case;
 
end if;
end process;
 
end architecture;
/o8_max7221.vhd
0,0 → 1,197
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_max7221 is
generic(
Bit_Rate : real := 5000000.0;
Sys_Freq : real;
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
--
Mx_Data : out std_logic;
Mx_Clock : out std_logic;
MX_LDCSn : out std_logic
);
end entity;
 
architecture behave of o8_max7221 is
 
signal FIFO_Reset : std_logic;
 
constant User_Addr : std_logic_vector(15 downto 4) := Address(15 downto 4);
alias Comp_Addr is Bus_Address(15 downto 4);
 
signal FIFO_Wr_En : std_logic;
signal FIFO_Wr_Data : std_logic_vector(11 downto 0);
 
signal FIFO_Rd_En : std_logic;
signal FIFO_Empty : std_logic;
signal FIFO_Rd_Data : std_logic_vector(11 downto 0);
 
type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
signal TX_Ctrl : TX_CTRL_STATES;
 
signal TX_En : std_logic;
signal TX_Idle : std_logic;
 
constant BAUD_DLY_VAL : integer := integer((Sys_Freq / Bit_Rate) / 2.0 );
constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
constant BAUD_DLY : std_logic_vector :=
conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
 
signal Baud_Cntr : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
:= (others => '0');
signal Baud_Tick : std_logic;
 
type IO_STATES is ( IDLE, SYNC_CLK, SCLK_L, SCLK_H, ADV_BIT, DONE );
signal io_state : IO_STATES;
signal bit_cntr : std_logic_vector(3 downto 0);
signal tx_buffer : std_logic_vector(15 downto 0);
 
begin
 
FIFO_Wr_En <= Wr_Enable when Comp_Addr = User_Addr else '0';
FIFO_Wr_Data <= Bus_Address(3 downto 0) & Wr_Data;
FIFO_Reset <= Reset when Reset_Level = '1' else (not Reset);
 
U_FIFO : entity work.o8_max7221_fifo
port map(
aclr => FIFO_Reset,
clock => Clock,
data => FIFO_Wr_Data,
rdreq => FIFO_Rd_En,
wrreq => FIFO_Wr_En,
empty => FIFO_Empty,
q => FIFO_Rd_Data
);
 
tx_FSM: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
TX_Ctrl <= IDLE;
TX_En <= '0';
FIFO_Rd_En <= '0';
elsif( rising_edge(Clock) )then
TX_En <= '0';
FIFO_Rd_En <= '0';
 
case( TX_Ctrl )is
when IDLE =>
if( FIFO_Empty = '0' )then
FIFO_Rd_En <= '1';
TX_Ctrl <= TX_BYTE;
end if;
 
when TX_BYTE =>
TX_En <= '1';
TX_Ctrl <= TX_START;
 
when TX_START =>
if( TX_Idle = '0' )then
TX_Ctrl <= TX_WAIT;
end if;
 
when TX_WAIT =>
if( TX_Idle = '1' )then
TX_Ctrl <= IDLE;
end if;
 
when others => null;
end case;
 
end if;
end process;
 
Baud_Rate_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Baud_Cntr <= (others => '0');
Baud_Tick <= '0';
elsif( rising_edge( Clock ) )then
Baud_Cntr <= Baud_Cntr - 1;
Baud_Tick <= nor_reduce(Baud_Cntr);
if( Baud_Cntr = 0 )then
Baud_Cntr <= BAUD_DLY;
end if;
end if;
end process;
 
io_FSM: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
io_state <= IDLE;
bit_cntr <= (others => '0');
tx_buffer <= (others => '0');
TX_Idle <= '0';
 
Mx_Clock <= '0';
Mx_Data <= '0';
MX_LDCSn <= '0';
 
elsif( rising_edge(Clock) )then
 
TX_Idle <= '0';
Mx_Clock <= '0';
 
case( io_state )is
when IDLE =>
Mx_Data <= '0';
MX_LDCSn <= '1';
TX_Idle <= '1';
if( TX_En = '1' )then
tx_buffer <= "0000" & FIFO_Rd_Data;
bit_cntr <= (others => '1');
io_state <= SYNC_CLK;
end if;
 
when SYNC_CLK =>
if( Baud_Tick = '1' )then
io_state <= SCLK_L;
end if;
 
when SCLK_L =>
MX_LDCSn <= '0';
Mx_Data <= tx_buffer(conv_integer(bit_cntr));
if( Baud_Tick = '1' )then
io_state <= SCLK_H;
end if;
 
when SCLK_H =>
Mx_Clock <= '1';
if( Baud_Tick = '1' )then
bit_cntr <= bit_cntr - 1;
io_state <= ADV_BIT;
end if;
 
when ADV_BIT =>
io_state <= SCLK_L;
if( and_reduce(bit_cntr) = '1' )then
io_state <= DONE;
end if;
 
when DONE =>
Mx_Data <= '0';
if( Baud_Tick = '1' )then
io_state <= IDLE;
end if;
 
when others => null;
end case;
end if;
end process;
 
end architecture;
/o8_max7221_fifo.vhd
0,0 → 1,183
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
 
-- ============================================================
-- File Name: o8_max7221_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY o8_max7221_fifo IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END o8_max7221_fifo;
 
 
ARCHITECTURE SYN OF o8_max7221_fifo IS
 
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (11 DOWNTO 0);
 
 
 
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
 
BEGIN
empty <= sub_wire0;
q <= sub_wire1(11 DOWNTO 0);
 
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone IV GX",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 12,
lpm_widthu => 9,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
q => sub_wire1
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "12"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "12"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_max7221_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_max7221_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_max7221_fifo.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_max7221_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_max7221_fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/o8_ram_1k.vhd
56,10 → 56,10
alias Comp_Addr is Bus_Address(15 downto 10);
alias RAM_Addr is Bus_Address(9 downto 0);
 
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Rd_En : std_logic;
signal Rd_Data_i : DATA_TYPE;
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
82,10 → 82,10
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match and Rd_Enable;
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
end if;
/o8_register.vhd
37,7 → 37,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
94,7 → 94,7
Wr_Data_q <= (others => '0');
Reg_Out <= Default_Value;
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
102,7 → 102,7
Reg_Out <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
Rd_Data <= Reg_Out;
/o8_rom_32k.vhd
54,9 → 54,9
alias Comp_Addr is Bus_Address(15 downto 15);
alias ROM_Addr is Bus_Address(14 downto 0);
 
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
signal Rd_Data_i : DATA_TYPE;
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
74,10 → 74,10
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match;
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
end if;
/o8_rtc.vhd
1,4 → 1,27
-- VHDL Units : realtime_clock
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_rtc
-- Description: Provides automatically updated registers that maintain the
-- : time of day. Keeps track of the day of week, hours, minutes
-- : seconds, and tenths of a second. Module is doubled buffered
5,7 → 28,7
-- : to ensure time consistency during accesses. Also provides
-- : a programmable periodic interrupt timer, as well as a uSec
-- : tick for external use.
--
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)
189,7 → 212,7
Reg_Addr_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
 
elsif( rising_edge( Clock ) )then
 
361,7 → 384,7
update_ctmr <= (others => '1');
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
/o8_status_led.vhd
44,7 → 44,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
103,7 → 103,7
Wr_Data_q <= (others => '0');
LED_Mode <= (others => '0');
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data(2 downto 0);
111,7 → 111,7
LED_Mode <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
Rd_Data <= "00000" & LED_Mode;
119,7 → 119,7
 
end if;
end process;
 
Output_FF: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
/o8_sys_timer.vhd
69,14 → 69,14
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
signal Rd_En_q : std_logic;
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := OPEN8_NULLBUS;
signal Rd_En : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Interval : DATA_TYPE;
signal Timer_Cnt : DATA_TYPE;
signal Interval : DATA_TYPE := x"00";
signal Timer_Cnt : DATA_TYPE := x"00";
 
constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
85,7 → 85,7
 
signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
:= (others => '0');
signal uSec_Tick_i : std_logic;
signal uSec_Tick_i : std_logic := '0';
begin
 
uSec_Tick <= uSec_Tick_i;
97,7 → 97,7
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
Interval <= x"00";
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
/o8_vdsm12.vhd
178,7 → 178,7
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
Wr_En <= '0';
Wr_Data_q <= x"00";
DAC_Val_LB <= x"00";
203,7 → 203,7
end case;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
case( Reg_Sel )is
244,7 → 244,7
(others => '0');
 
Next_Period <= q(DAC_Width-1 downto 0) - 1;
 
vDSM_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
/o8_vdsm8.vhd
139,7 → 139,7
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= x"00";
Rd_Data <= OPEN8_NULLBUS;
DACin <= x"00";
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
148,7 → 148,7
DACin <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
Rd_Data <= DACin;
/ram_1k_core.vhd
0,0 → 1,186
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: ram_1k_core.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY ram_1k_core IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_1k_core;
 
 
ARCHITECTURE SYN OF ram_1k_core IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=LRAM",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "LRAM"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=LRAM"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_1k_core_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
/rom_32k_core.vhd
0,0 → 1,171
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: rom_32k_core.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY rom_32k_core IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END rom_32k_core;
 
 
ARCHITECTURE SYN OF rom_32k_core IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
 
 
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "Software/APP.HEX",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM",
lpm_type => "altsyncram",
numwords_a => 32768,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 15,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "ROM"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "Software/APP.HEX"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "Software/APP.HEX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ROM"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_32k_core_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
/sdlc_crc16_ccitt.vhd
0,0 → 1,115
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : crc16_ccitt
-- Description: Implements the 16-bit CCITT CRC on byte-wide data. Logic
-- equations were taken from Intel/Altera app note AN049.
 
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.sdlc_serial_pkg.all;
 
entity sdlc_crc16_ccitt is
generic(
Poly_Init : std_logic_vector(15 downto 0) := x"0000";
Reset_Level : std_logic := '1'
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Clear : in std_logic;
Wr_Data : in DATA_IN_TYPE;
Wr_En : in std_logic;
--
CRC16_Out : out CRC_OUT_TYPE;
CRC16_Valid : out std_logic
);
end entity;
 
architecture behave of sdlc_crc16_ccitt is
 
signal Calc_En : std_logic;
signal Buffer_En : std_logic;
signal Data : DATA_IN_TYPE;
signal Exr : DATA_IN_TYPE;
signal Reg : CRC_OUT_TYPE;
 
begin
 
Exr(0) <= Reg(0) xor Data(0);
Exr(1) <= Reg(1) xor Data(1);
Exr(2) <= Reg(2) xor Data(2);
Exr(3) <= Reg(3) xor Data(3);
Exr(4) <= Reg(4) xor Data(4);
Exr(5) <= Reg(5) xor Data(5);
Exr(6) <= Reg(6) xor Data(6);
Exr(7) <= Reg(7) xor Data(7);
 
CRC16_Calc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Calc_En <= '0';
Buffer_En <= '0';
Data <= x"00";
Reg <= x"0000";
CRC16_Out <= x"0000";
CRC16_Valid <= '0';
elsif( rising_edge(Clock) )then
Calc_En <= Wr_En;
if( Wr_En = '1' )then
Data <= Wr_Data;
end if;
 
if( Calc_En = '1' )then
Reg(0) <= Reg(8) xor Exr(4) xor Exr(0);
Reg(1) <= Reg(9) xor Exr(5) xor Exr(1);
Reg(2) <= Reg(10) xor Exr(6) xor Exr(2);
Reg(3) <= Reg(11) xor Exr(0) xor Exr(7) xor Exr(3);
Reg(4) <= Reg(12) xor Exr(1) ;
Reg(5) <= Reg(13) xor Exr(2) ;
Reg(6) <= Reg(14) xor Exr(3) ;
Reg(7) <= Reg(15) xor Exr(4) xor Exr(0);
Reg(8) <= Exr(0) xor Exr(5) xor Exr(1);
Reg(9) <= Exr(1) xor Exr(6) xor Exr(2);
Reg(10) <= Exr(2) xor Exr(7) xor Exr(3);
Reg(11) <= Exr(3) ;
Reg(12) <= Exr(4) xor Exr(0);
Reg(13) <= Exr(5) xor Exr(1);
Reg(14) <= Exr(6) xor Exr(2);
Reg(15) <= Exr(7) xor Exr(3);
elsif( Clear = '1' )then
Reg <= Poly_Init;
end if;
 
Buffer_En <= Calc_En;
if( Buffer_En = '1' )then
CRC16_Out <= Reg xor x"FFFF";
end if;
CRC16_Valid <= Buffer_En;
end if;
end process;
 
end architecture;

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