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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 208 to Rev 209
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  •

Rev 208 → Rev 209

/async_ser_rx.vhd
24,6 → 24,13
-- VHDL Units : async_ser_rx
-- Description: Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode
-- and bit rate are set with generics.
--
--
-- Note: The baud rate generator will produce an approximate frequency. The
-- final bit rate should be within +/- 1% of the true bit rate to
-- ensure the receiver can successfully receive. With a sufficiently
-- high core clock, this is generally achievable for common PC serial
-- data rates.
 
library ieee;
use ieee.std_logic_1164.all;
/async_ser_tx.vhd
24,6 → 24,12
-- VHDL Units : async_ser_tx
-- Description: Asynchronous transmitter wired for 8[N/E/O]1 data. Parity mode
-- and bit rate are set with generics.
--
-- Note: The baud rate generator will produce an approximate frequency. The
-- final bit rate should be within +/- 1% of the true bit rate to
-- ensure the receiver can successfully receive. With a sufficiently
-- high core clock, this is generally achievable for common PC serial
-- data rates.
 
library ieee;
use ieee.std_logic_1164.all;
/o8_async_serial.vhd
25,6 → 25,12
-- Description: Provides a single 8-bit, asynchronous transceiver. While the
-- width is fixed at 8-bits, the bit rate and parity controls
-- are settable via generics.
--
-- Note: The baud rate generator will produce an approximate frequency. The
-- final bit rate should be within +/- 1% of the true bit rate to
-- ensure the receiver can successfully receive. With a sufficiently
-- high core clock, this is generally achievable for common PC serial
-- data rates.
 
library ieee;
use ieee.std_logic_1164.all;
95,11 → 101,11
alias CTS_Okay is CTS_sr(3);
 
signal RX_FIFO_Wr_En : std_logic := '0';
signal RX_FIFO_Wr_Data : DATA_TYPE;
signal RX_FIFO_Rd_En : std_logic;
signal RX_FIFO_Empty : std_logic;
signal RX_FIFO_AFull : std_logic;
signal RX_FIFO_Rd_Data : DATA_TYPE;
signal RX_FIFO_Wr_Data : DATA_TYPE := x"00";
signal RX_FIFO_Rd_En : std_logic := '0';
signal RX_FIFO_Empty : std_logic := '0';
signal RX_FIFO_AFull : std_logic := '0';
signal RX_FIFO_Rd_Data : DATA_TYPE := x"00";
 
begin
 
/o8_cpu.vhd
1094,7 → 1094,7
("0" & Regfile(Index));
Flags(PSR_Z) <= nor_reduce(Sum(7 downto 0));
Flags(PSR_C) <= Sum(8);
Flags(PSR_N) <= Sum(7);
Flags(PSR_N) <= Sum(7);
Regfile(Index) <= Sum(7 downto 0);
 
when ALU_UPP => -- Rn = Rn + 1
/o8_epoch_timer.vhd
113,10 → 113,14
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
epoch_tmr <= epoch_tmr + uSec_Tick;
-- Force the lower bits of the setpoint to "11" so that the offset is
-- reduced to 1uS (reproducing the original behavior). Software should
-- always subtract 4uS (-1) from the desired time to compensate
epoch_setpt(1 downto 0) <= "11";
-- Force the lower bits of the setpoint to "11" so that the offset is
-- reduced to 1uS (reproducing the original behavior). Software should
-- always subtract 4uS (-1) from the desired time to compensate
epoch_setpt(1 downto 0) <= "11";
if( epoch_setpt(25 downto 2) = 0 )then
epoch_setpt(1 downto 0) <= "00";
end if;
 
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Wr_Data;
 
149,7 → 153,7
end if;
 
-- Set and hold on alarm condition
if( epoch_tmr > epoch_setpt )then
if( epoch_tmr > epoch_setpt and epoch_setpt > 0 )then
epoch_alarm <= '1';
end if;
 
/o8_ram_4k.vhd
0,0 → 1,95
-- Copyright (c)2013, 2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_ram_1k
-- Description: Provides a wrapper layer for a 1kx8 RAM model
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_ram_4k is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Rd_Data : out DATA_TYPE
);
end entity;
 
architecture behave of o8_ram_4k is
 
constant User_Addr : std_logic_vector(15 downto 12)
:= Address(15 downto 12);
alias Comp_Addr is Bus_Address(15 downto 12);
alias RAM_Addr is Bus_Address(11 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_Data_i : DATA_TYPE := OPEN8_NULLBUS;
 
begin
 
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En <= Addr_Match and Wr_Enable;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_4k_core
port map(
address => RAM_Addr,
clock => Clock,
data => Wr_Data,
wren => Wr_En,
q => Rd_Data_i
);
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match and Rd_Enable;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
end if;
end if;
end process;
 
end architecture;
/o8_rtc.vhd
139,6 → 139,7
signal rtc : RTC_TYPE;
 
signal interval : DATA_TYPE;
signal mask_pit_int : std_logic;
 
signal shd_tens : DATA_TYPE;
signal shd_secs : DATA_TYPE;
207,6 → 208,7
update_ctmr <= (others => '0');
 
interval <= x"00";
mask_pit_int <= '0';
 
Wr_Data_q <= (others => '0');
Reg_Addr_q <= (others => '0');
228,7 → 230,9
pit.timer_ro <= '0';
if( or_reduce(pit.timer_cnt) = '0' )then
pit.timer_cnt <= interval;
pit.timer_ro <= or_reduce(interval); -- Only issue output on Int > 0
pit.timer_ro <= or_reduce(interval) and -- Only issue output on Int > 0
(not mask_pit_int); -- and we didn't just update it
end if;
 
-- Fractional decisecond counter - cycles every 10k microseconds
341,6 → 345,8
update_shd <= '0';
end if;
 
mask_pit_int <= '0';
 
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Wr_Data;
 
350,6 → 356,7
case( Reg_Addr_q )is
when "000" =>
interval <= Wr_Data_q;
mask_pit_int <= '1';
 
when "001" =>
shd_tens <= Wr_Data_q;
/ram_4k_core.vhd
0,0 → 1,156
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: ram_4k_core.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY ram_4k_core IS
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_4k_core;
 
 
ARCHITECTURE SYN OF ram_4k_core IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=LRAM",
lpm_type => "altsyncram",
numwords_a => 4096,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 12,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "LRAM"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=LRAM"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_4k_core_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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