URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 214 to Rev 215
- ↔ Reverse comparison
Rev 214 → Rev 215
/async_ser_rx.vhd
40,20 → 40,20
|
entity async_ser_rx is |
generic( |
Reset_Level : std_logic; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Clock_Divider : integer |
Reset_Level : std_logic; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Clock_Divider : integer |
); |
port( |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Rx_In : in std_logic; |
-- |
Rx_Data : out std_logic_vector(7 downto 0); |
Rx_Valid : out std_logic; |
Rx_PErr : out std_logic |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Rx_In : in std_logic; |
-- |
Rx_Data : out std_logic_vector(7 downto 0); |
Rx_Valid : out std_logic; |
Rx_PErr : out std_logic |
); |
end entity; |
|
/async_ser_tx.vhd
39,21 → 39,21
|
entity async_ser_tx is |
generic( |
Reset_Level : std_logic; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Clock_Divider : integer |
Reset_Level : std_logic; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Clock_Divider : integer |
); |
port( |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Tx_Data : in std_logic_vector(7 downto 0); |
Tx_Valid : in std_logic; |
-- |
Tx_Out : out std_logic; |
Tx_Done : out std_logic |
); |
Clock : in std_logic; |
Reset : in std_logic; |
-- |
Tx_Data : in std_logic_vector(7 downto 0); |
Tx_Valid : in std_logic; |
-- |
Tx_Out : out std_logic; |
Tx_Done : out std_logic |
|
end entity; |
|
architecture behave of async_ser_tx is |