URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 219 to Rev 220
- ↔ Reverse comparison
Rev 219 → Rev 220
/Open8_pkg.vhd
18,11 → 18,12
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|
-- VHDL Units : Open8_pkg |
-- Description: Contains constant definitions for the Open8 processor |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
/async_ser_rx.vhd
18,8 → 18,8
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : async_ser_rx |
-- Description: Asynchronous receiver wired for 8[N/E/O]1 data. Parity mode |
/async_ser_tx.vhd
18,8 → 18,8
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : async_ser_tx |
-- Description: Asynchronous transmitter wired for 8[N/E/O]1 data. Parity mode |
/o8_ltc2355_2p.vhd
18,8 → 18,8
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL units : ltc2355_2p |
-- Description: Reads out a pair of LTC2355 14-bit ADCs which are wired with |
/sdlc_crc16_ccitt.vhd
24,6 → 24,11
-- VHDL Units : crc16_ccitt |
-- Description: Implements the 16-bit CCITT CRC on byte-wide data. Logic |
-- equations were taken from Intel/Altera app note AN049. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/sdlc_serial_arbfsm.vhd
23,6 → 23,11
-- |
-- VHDL Units : sdlc_serial_arbfsm |
-- Description: Handles access to the shared buffer memory |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/sdlc_serial_clk.vhd
28,6 → 28,10
-- serial bit rate as a real (BitClock_Freq). Note that the clock is free- |
-- running rather than gated. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/sdlc_serial_frame.vhd
29,6 → 29,10
-- Note that this frame detection system can handle either an |
-- idle line or repeated flags. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/sdlc_serial_pkg.vhd
20,6 → 20,14
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : sdlc_serial_pkg |
-- Description: Contains constant definitions for the SDLC packet engine |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/sdlc_serial_rx.vhd
44,6 → 44,10
-- logic shortly after the rising edge of the bitclock on the "clock" clock |
-- domain. |
-- |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
|
library ieee; |
use ieee.std_logic_1164.all; |
/vdsm8.vhd
18,8 → 18,8
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : vdsm8 |
-- Description: 8-bit variable delta-sigma modulator single-bit DAC |