OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 222 to Rev 223
    ↔ Reverse comparison
  •

Rev 222 → Rev 223

/Open8_pkg.vhd
76,6 → 76,13
 
constant OPEN8_NULLBUS : DATA_TYPE := x"00";
 
type OPEN8_BUS_TYPE is record
Address : ADDRESS_TYPE;
Wr_En : std_logic;
Wr_Data : DATA_TYPE;
Rd_En : std_logic;
end record;
 
-- Component declaration
-- (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
component o8_cpu is
95,13 → 102,11
Clock : in std_logic;
Reset : in std_logic;
CPU_Halt : in std_logic;
Interrupts : in INTERRUPT_BUNDLE;
GP_Flags : out EXT_GP_FLAGS;
Address : out ADDRESS_TYPE;
Open8_Bus : out OPEN8_BUS_TYPE;
Rd_Data : in DATA_TYPE;
Rd_Enable : out std_logic;
Wr_Data : out DATA_TYPE;
Wr_Enable : out std_logic );
Interrupts : in INTERRUPT_BUNDLE
);
end component;
 
-- This function is used to calculate RAM parameters, but is generally
/o8_alu16.vhd
174,10 → 174,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
246,7 → 243,7
 
constant User_Addr : std_logic_vector(15 downto 5):=
Address(15 downto 5);
alias Comp_Addr is Bus_Address(15 downto 5);
alias Comp_Addr is Open8_Bus.Address(15 downto 5);
 
signal Reg_Addr : std_logic_vector(4 downto 0) :=
(others => '0');
441,9 → 438,9
Reg_Sel := conv_integer(Reg_Addr(3 downto 1));
Oper_Sel := conv_integer(Operand_Sel);
 
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Reg_Addr <= Bus_Address(4 downto 0);
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Reg_Addr <= Open8_Bus.Address(4 downto 0);
 
Start <= '0';
if( Wr_En = '1' )then
476,7 → 473,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
 
if( Rd_En = '1' )then
case( Reg_Addr )is
/o8_async_serial.vhd
71,10 → 71,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
TX_Out : out std_logic;
90,15 → 87,15
 
constant User_Addr : std_logic_vector(15 downto 1) :=
Address(15 downto 1);
alias Comp_Addr is Bus_Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(0);
alias Reg_Addr is Open8_Bus.Address(0);
signal Reg_Sel : std_logic := '0';
signal Rd_En : std_logic := '0';
 
signal TX_FIFO_Wr_En : std_logic := '0';
alias TX_FIFO_Wr_Data is Wr_Data;
alias TX_FIFO_Wr_Data is Open8_Bus.Wr_Data;
signal TX_FIFO_Rd_En : std_logic := '0';
signal TX_FIFO_Empty : std_logic := '0';
signal TX_FIFO_AFull : std_logic := '0';
136,7 → 133,7
RTS_Out <= '0';
elsif( rising_edge( Clock ) )then
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Rd_Enable and Addr_Match;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Reg_Sel <= Reg_Addr;
if( Rd_En = '1' and Reg_Sel = '1' )then
Rd_Data(4) <= RX_FIFO_Empty;
161,7 → 158,9
 
TX_Enabled : if( not Disable_Transmit )generate
 
TX_FIFO_Wr_En <= Wr_Enable and Addr_Match and not Reg_Addr;
TX_FIFO_Wr_En <= Open8_Bus.Wr_En and
Addr_Match and
(not Reg_Addr);
 
FIFO_Reset <= '1' when Reset = Reset_Level else '0';
 
264,7 → 263,9
Rx_PErr => open
);
 
RX_FIFO_Rd_En <= Rd_Enable and Addr_Match and not Reg_Addr;
RX_FIFO_Rd_En <= Open8_Bus.Rd_En and
Addr_Match and
(not Reg_Addr);
 
U_RX_FIFO : entity work.fifo_1k_core
port map(
/o8_btn_int.vhd
55,8 → 55,7
Reset : in std_logic := '0';
uSec_Tick : in std_logic := '0';
--
Bus_Address : in ADDRESS_TYPE := x"0000";
Rd_Enable : in std_logic := '0';
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
67,7 → 66,7
architecture behave of o8_btn_int is
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
 
82,7 → 81,8
 
begin
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
 
io_reg: process( Clock, Reset )
begin
/o8_clk_detect.vhd
51,8 → 51,7
--
Ref_Clk_In : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
61,7 → 60,7
architecture behave of o8_clk_detect is
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Rd_En : std_logic := '0';
87,7 → 86,7
 
begin
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
/o8_cpu.vhd
230,14 → 230,12
Clock : in std_logic;
Reset : in std_logic;
CPU_Halt : in std_logic := '0';
Interrupts : in INTERRUPT_BUNDLE := x"00";
GP_Flags : out EXT_GP_FLAGS;
--
Address : out ADDRESS_TYPE;
Open8_Bus : out OPEN8_BUS_TYPE;
Rd_Data : in DATA_TYPE;
Rd_Enable : out std_logic;
Wr_Data : out DATA_TYPE;
Wr_Enable : out std_logic );
Interrupts : in INTERRUPT_BUNDLE := x"00"
);
end entity;
 
architecture behave of o8_cpu is
316,22 → 314,22
case( CPU_State )is
 
when LDA_C2 | STA_C2 =>
Address <= Operand2 & Operand1;
Open8_Bus.Address <= Operand2 & Operand1;
 
when LDX_C1 | STX_C1 =>
Address <= (Regfile(Reg_1) & Regfile(Reg));
Open8_Bus.Address <= (Regfile(Reg_1) & Regfile(Reg));
 
when LDO_C1 | STO_C1 =>
Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
Open8_Bus.Address <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
 
when ISR_C1 | ISR_C2 =>
Address <= ISR_Addr;
Open8_Bus.Address <= ISR_Addr;
 
when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
Address <= Stack_Ptr;
Open8_Bus.Address <= Stack_Ptr;
 
when others =>
Address <= Program_Ctr;
Open8_Bus.Address <= Program_Ctr;
 
end case;
 
891,9 → 889,9
 
CPU_Halt_Req <= '0';
 
Wr_Data <= OPEN8_NULLBUS;
Wr_Enable <= '0';
Rd_Enable <= '1';
Open8_Bus.Wr_En <= '0';
Open8_Bus.Wr_Data <= OPEN8_NULLBUS;
Open8_Bus.Rd_En <= '1';
 
Program_Ctr <= Program_Start_Addr;
Stack_Ptr <= Stack_Start_Addr;
924,9 → 922,9
 
CPU_Halt_Req <= CPU_Halt;
 
Wr_Enable <= '0';
Wr_Data <= OPEN8_NULLBUS;
Rd_Enable <= '0';
Open8_Bus.Wr_En <= '0';
Open8_Bus.Wr_Data <= OPEN8_NULLBUS;
Open8_Bus.Rd_En <= '0';
 
-------------------------------------------------------------------------------
-- Instruction/Operand caching for pipelined memory access
983,21 → 981,21
null;
 
when DATA_RD_MEM =>
Rd_Enable <= '1';
Open8_Bus.Rd_En <= '1';
 
when DATA_WR_REG =>
Wr_Enable <= '1';
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
Open8_Bus.Wr_En <= '1';
Open8_Bus.Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg));
 
when DATA_WR_FLAG =>
Wr_Enable <= '1';
Wr_Data <= Flags;
Open8_Bus.Wr_En <= '1';
Open8_Bus.Wr_Data <= Flags;
 
when DATA_WR_PC =>
Wr_Enable <= '1';
Wr_Data <= Program_Ctr(15 downto 8);
Open8_Bus.Wr_En <= '1';
Open8_Bus.Wr_Data <= Program_Ctr(15 downto 8);
if( DP_Ctrl.Reg = PC_LSB )then
Wr_Data <= Program_Ctr(7 downto 0);
Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
end if;
 
when others =>
/o8_crc16_ccitt.vhd
58,10 → 58,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
73,8 → 70,8
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
alias Reg_Addr is Bus_Address(1 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) :=
(others => '0');
signal Addr_Match : std_logic;
124,8 → 121,8
elsif( rising_edge(Clock) )then
Reg_Sel <= Reg_Addr;
 
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
 
if( Wr_En = '1' )then
case( Reg_Sel )is
141,7 → 138,7
end case;
end if;
 
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
case( Reg_Sel )is
/o8_datalatch.vhd
52,8 → 52,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
65,7 → 64,7
architecture behave of o8_datalatch is
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
 
78,7 → 77,7
 
begin
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
Strobe_re <= Strobe_sr(2) and not Strobe_sr(3);
 
io_reg: process( Clock, Reset )
/o8_epoch_timer.vhd
73,10 → 73,7
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
87,10 → 84,10
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
 
alias Comp_Addr is Bus_Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(2 downto 0);
alias Reg_Addr is Open8_Bus.Address(2 downto 0);
signal Reg_Addr_q : std_logic_vector(2 downto 0) :=
(others => '0');
 
154,8 → 151,8
elsif( rising_edge( Clock ) )then
 
Reg_Addr_q <= Reg_Addr;
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
 
buffer_update <= '0';
capture_epoch <= '0';
189,7 → 186,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
when "000" =>
/o8_epoch_timer_ii.vhd
79,10 → 79,7
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
93,10 → 90,10
constant User_Addr : std_logic_vector(15 downto 4)
:= Address(15 downto 4);
 
alias Comp_Addr is Bus_Address(15 downto 4);
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(3 downto 0);
alias Reg_Addr is Open8_Bus.Address(3 downto 0);
signal Reg_Addr_q : std_logic_vector(3 downto 0) :=
(others => '0');
 
162,8 → 159,8
elsif( rising_edge( Clock ) )then
 
Reg_Addr_q <= Reg_Addr;
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
 
buffer_update <= '0';
timer_clear <= '0';
202,7 → 199,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
when x"0" =>
/o8_gpin.vhd
49,8 → 49,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
GPIN : in DATA_TYPE
60,7 → 59,7
architecture behave of o8_gpin is
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
 
70,7 → 69,8
 
begin
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
 
io_reg: process( Clock, Reset )
begin
/o8_gpio.vhd
55,10 → 55,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
GPIO : inout DATA_TYPE
69,17 → 66,17
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
alias Reg_Addr is Bus_Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
 
signal User_Out : DATA_TYPE;
signal User_En : DATA_TYPE;
signal User_In : DATA_TYPE;
signal User_Out : DATA_TYPE := x"00";
signal User_En : DATA_TYPE := x"00";
signal User_In : DATA_TYPE := x"00";
 
begin
 
98,8 → 95,8
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
 
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
case( Reg_Sel )is
when "00" =>
113,7 → 110,7
User_In <= GPIO;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= User_In;
case( Reg_Sel )is
/o8_gpout.vhd
58,10 → 58,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
GPO : out DATA_TYPE
72,16 → 69,16
 
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Bus_Address(15 downto 1);
alias Reg_Addr is Bus_Address(0);
signal Reg_Sel : std_logic;
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
alias Reg_Addr is Open8_Bus.Address(0);
signal Reg_Sel : std_logic := '0';
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
 
signal User_Out : DATA_TYPE;
signal User_En : DATA_TYPE;
signal User_Out : DATA_TYPE := x"00";
signal User_En : DATA_TYPE := x"00";
 
begin
 
101,8 → 98,8
end if;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
if( Disable_Tristate )then
User_Out <= Wr_Data_q;
116,7 → 113,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= User_Out;
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
/o8_hd44780_4b.vhd
97,10 → 97,7
--
uSec_Tick : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
117,10 → 114,10
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(1 downto 0);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
 
signal Wr_En : std_logic := '0';
214,8 → 211,8
elsif( rising_edge( Clock ) )then
Reg_Addr_q <= Reg_Addr;
 
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
Reg_Valid <= '0';
 
234,7 → 231,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
when "00" | "01" =>
/o8_hd44780_8b.vhd
96,10 → 96,7
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
116,10 → 113,10
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(1 downto 0);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
 
signal Wr_En : std_logic := '0';
209,8 → 206,8
elsif( rising_edge( Clock ) )then
Reg_Addr_q <= Reg_Addr;
 
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
Reg_Valid <= '0';
 
229,7 → 226,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
when "00" | "01" =>
/o8_lfsr32.vhd
51,8 → 51,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
61,8 → 60,8
 
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Bus_Address(15 downto 1);
alias Reg_Sel is Bus_Address(0);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
alias Reg_Sel is Open8_Bus.Address(0);
signal Reg_Sel_q : std_logic := '0';
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
73,7 → 72,8
 
begin
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
 
lfsr_proc: process( Clock, Reset )
/o8_ltc2355_2p.vhd
50,11 → 50,8
Clock : in std_logic; -- 96MHz MAX for proper operation
Reset : in std_logic;
uSec_Tick : in std_logic;
-- Client IF
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
-- ADC IF
70,8 → 67,8
constant Divide_SCLK_by_2 : boolean := (Sys_Freq > 96000000.0);
 
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
alias Comp_Addr is Bus_Address(15 downto 3);
alias Reg_Sel is Bus_Address(2 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
alias Reg_Sel is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0);
signal Wr_Data_q : DATA_TYPE;
signal Addr_Match : std_logic;
113,8 → 110,8
Timer_Int <= x"00";
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel;
Wr_Data_q <= Wr_Data;
Wr_En <= Wr_Enable and Addr_Match;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
User_Trig <= '0';
if( Wr_En = '1' )then
if( Reg_Sel_q = "110" )then
125,7 → 122,7
end if;
end if;
 
Rd_En <= Rd_Enable and Addr_Match;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
 
if( Rd_En = '1' )then
/o8_max7221.vhd
50,9 → 50,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Open8_Bus : in OPEN8_BUS_TYPE;
--
Mx_Data : out std_logic;
Mx_Clock : out std_logic;
66,7 → 64,7
 
constant User_Addr : std_logic_vector(15 downto 4) :=
Address(15 downto 4);
alias Comp_Addr is Bus_Address(15 downto 4);
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
 
signal FIFO_Wr_En : std_logic;
signal FIFO_Wr_Data : std_logic_vector(11 downto 0);
97,8 → 95,12
 
begin
 
FIFO_Wr_En <= Wr_Enable when Comp_Addr = User_Addr else '0';
FIFO_Wr_Data <= Bus_Address(3 downto 0) & Wr_Data;
FIFO_Wr_En <= Open8_Bus.Wr_En when Comp_Addr = User_Addr else
'0';
 
FIFO_Wr_Data <= Open8_Bus.Address(3 downto 0) &
Open8_Bus.Wr_Data;
 
FIFO_Reset <= Reset when Reset_Level = '1' else (not Reset);
 
U_FIFO : entity work.o8_max7221_fifo
/o8_pwm16.vhd
59,14 → 59,11
Reset : in std_logic;
uSec_Tick : in std_logic;
--
PWM_Out : out std_logic;
-- Bus interface
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
Interrupt : out std_logic;
--
PWM_Out : out std_logic
);
end entity;
 
75,10 → 72,10
constant User_Addr : std_logic_vector(15 downto 3) :=
Address(15 downto 3);
 
alias Comp_Addr is Bus_Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Bus_Address(2 downto 0);
alias Reg_Addr is Open8_Bus.Address(2 downto 0);
signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
 
signal Wr_En : std_logic := '0';
120,8 → 117,8
PWM_Out <= '0';
elsif( rising_edge(Clock) )then
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
if( Wr_En = '1' )then
case( Reg_Addr_q )is
140,7 → 137,7
end if;
 
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
when "000" =>
/o8_ram_1k.vhd
41,10 → 41,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
53,8 → 50,8
 
constant User_Addr : std_logic_vector(15 downto 10)
:= Address(15 downto 10);
alias Comp_Addr is Bus_Address(15 downto 10);
alias RAM_Addr is Bus_Address(9 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 10);
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
66,7 → 63,7
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En <= Addr_Match and Wr_Enable;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_1k_core
73,7 → 70,7
port map(
address => RAM_Addr,
clock => Clock,
data => Wr_Data,
data => Open8_Bus.Wr_Data,
wren => Wr_En,
q => Rd_Data_i
);
84,7 → 81,7
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
/o8_ram_4k.vhd
41,10 → 41,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
53,8 → 50,8
 
constant User_Addr : std_logic_vector(15 downto 12)
:= Address(15 downto 12);
alias Comp_Addr is Bus_Address(15 downto 12);
alias RAM_Addr is Bus_Address(11 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 12);
alias RAM_Addr is Open8_Bus.Address(11 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
66,7 → 63,7
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En <= Addr_Match and Wr_Enable;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
-- Note that this RAM should be created without an output FF (unregistered Q)
U_RAM : entity work.ram_4k_core
73,7 → 70,7
port map(
address => RAM_Addr,
clock => Clock,
data => Wr_Data,
data => Open8_Bus.Wr_Data,
wren => Wr_En,
q => Rd_Data_i
);
84,7 → 81,7
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Rd_Data_i;
/o8_register.vhd
52,10 → 52,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
Register_Out : out DATA_TYPE
66,7 → 63,7
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
86,14 → 83,14
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
Reg_Out <= Wr_Data_q;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= Reg_Out;
end if;
/o8_rom_32k.vhd
41,8 → 41,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
end entity;
51,8 → 50,8
 
constant User_Addr : std_logic_vector(15 downto 15) :=
Address(15 downto 15);
alias Comp_Addr is Bus_Address(15 downto 15);
alias ROM_Addr is Bus_Address(14 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 15);
alias ROM_Addr is Open8_Bus.Address(14 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
68,7 → 67,8
q => Rd_Data_i
);
 
Addr_Match <= Rd_Enable when Comp_Addr = User_Addr else '0';
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
 
RAM_proc: process( Reset, Clock )
begin
/o8_rtc.vhd
63,10 → 63,7
Reset : in std_logic;
uSec_Tick : out std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
Interrupt_PIT : out std_logic;
78,10 → 75,10
 
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
alias Comp_Addr is Bus_Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic;
 
alias Reg_Addr is Bus_Address(2 downto 0);
alias Reg_Addr is Open8_Bus.Address(2 downto 0);
signal Reg_Addr_q : std_logic_vector(2 downto 0);
 
signal Wr_En : std_logic;
350,9 → 347,9
update_interval <= '0';
 
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Wr_Data;
Wr_Data_q <= Open8_Bus.Wr_Data;
 
Wr_En <= Addr_Match and Wr_Enable;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
update_rtc <= '0';
if( Wr_En = '1' )then
case( Reg_Addr_q )is
394,7 → 391,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
when "000" =>
/o8_sdlc_if.vhd
87,10 → 87,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
-- Serial IO
106,18 → 103,18
constant Base_Addr : std_logic_vector(15 downto 9)
:= Address(15 downto 9);
 
alias CPU_Upper_Addr is Bus_Address(15 downto 9);
alias CPU_Upper_Addr is Open8_Bus.Address(15 downto 9);
signal Base_Addr_Match : std_logic := '0';
 
alias DP_A_Addr is Bus_Address(8 downto 0);
alias DP_A_Addr is Open8_Bus.Address(8 downto 0);
signal DP_A_Wr_En : std_logic := '0';
alias DP_A_Wr_Data is Wr_Data;
alias DP_A_Wr_Data is Open8_Bus.Wr_Data;
signal DP_A_Rd_En : std_logic := '0';
signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
alias Reg_Upper_Addr is Bus_Address(8 downto 1);
alias Reg_Lower_Addr is Bus_Address(0);
alias Reg_Upper_Addr is Open8_Bus.Address(8 downto 1);
alias Reg_Lower_Addr is Open8_Bus.Address(0);
 
signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
signal Reg_Sel : std_logic := '0';
184,7 → 181,7
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
DP_A_Wr_En <= Base_Addr_Match and Wr_Enable;
DP_A_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
 
CPU_IF_proc: process( Reset, Clock )
begin
199,7 → 196,7
elsif( rising_edge(Clock) )then
Reg_Addr <= Reg_Upper_Addr;
Reg_Sel <= Reg_Lower_Addr;
Reg_Wr_En <= Base_Addr_Match and Wr_Enable;
Reg_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
 
Reg_Clk_Sel <= '0';
Reg_TxS_Sel <= '0';
208,7 → 205,7
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
end if;
 
DP_A_Rd_En <= Base_Addr_Match and Rd_Enable;
DP_A_Rd_En <= Base_Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
if( DP_A_Rd_En = '1' )then
Rd_Data <= DP_A_Rd_Data;
/o8_status_led.vhd
58,10 → 58,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
LED_Out : out std_logic
72,7 → 69,7
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : std_logic_vector(2 downto 0);
105,14 → 102,14
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data(2 downto 0);
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data(2 downto 0);
if( Wr_En = '1' )then
LED_Mode <= Wr_Data_q;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= "00000" & LED_Mode;
end if;
/o8_sys_timer.vhd
58,10 → 58,7
Reset : in std_logic;
uSec_Tick : out std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
70,10 → 67,10
architecture behave of o8_sys_timer is
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := OPEN8_NULLBUS;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
104,8 → 101,8
Interval <= x"00";
Update_Interval <= '0';
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Update_Interval <= '0';
if( Wr_En = '1' )then
Interval <= Wr_Data_q;
113,7 → 110,7
end if;
 
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= Interval;
end if;
/o8_vdsm12.vhd
54,10 → 54,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
PDM_Out : out std_logic
68,8 → 65,8
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
alias Reg_Addr is Bus_Address(1 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
205,8 → 202,8
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
 
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
case( Reg_Sel )is
when "00" =>
222,7 → 219,7
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Sel )is
when "00" =>
/o8_vdsm8.vhd
52,10 → 52,7
Clock : in std_logic;
Reset : in std_logic;
--
Bus_Address : in ADDRESS_TYPE;
Wr_Enable : in std_logic;
Wr_Data : in DATA_TYPE;
Rd_Enable : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
DACout : out std_logic
66,7 → 63,7
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Bus_Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
86,14 → 83,14
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
Reg_Out <= Wr_Data_q;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Rd_Enable;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= Reg_Out;
end if;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.