OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 223 to Rev 224
    ↔ Reverse comparison
  •

Rev 223 → Rev 224

/Open8_pkg.vhd
77,12 → 77,18
constant OPEN8_NULLBUS : DATA_TYPE := x"00";
 
type OPEN8_BUS_TYPE is record
Clock : std_logic;
Reset : std_logic;
uSec_Tick : std_logic;
Address : ADDRESS_TYPE;
Wr_En : std_logic;
Wr_Data : DATA_TYPE;
Rd_En : std_logic;
GP_Flags : EXT_GP_FLAGS;
end record;
 
constant Reset_Level : std_logic := '1';
 
-- Component declaration
-- (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
component o8_cpu is
97,15 → 103,15
Enable_NMI : boolean := true;
RTI_Ignores_GP_Flags : boolean := false;
Default_Interrupt_Mask : DATA_TYPE := x"FF";
Reset_Level : std_logic := '0' );
Clock_Frequency : real
);
port(
Clock : in std_logic;
Reset : in std_logic;
CPU_Halt : in std_logic;
GP_Flags : out EXT_GP_FLAGS;
PLL_Locked : in std_logic;
CPU_Halt : in std_logic := '0';
Open8_Bus : out OPEN8_BUS_TYPE;
Rd_Data : in DATA_TYPE;
Interrupts : in INTERRUPT_BUNDLE
Interrupts : in INTERRUPT_BUNDLE := x"00"
);
end component;
 
/o8_alu16.vhd
155,6 → 155,7
-- Seth Henry 03/13/15 Added "Almost Equal" instruction
-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
-- Seth Henry 04/10/20 Comment and code cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
167,13 → 168,9
 
entity o8_alu16 is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
182,6 → 179,9
 
architecture behave of o8_alu16 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
-------------------------------------------------------------------
-- Opcode Definitions (should match the table above)
-- Register Manipulation
/o8_async_serial.vhd
46,6 → 46,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/20/19 Design Start
-- Seth Henry 04/10/20 Code cleanup and register documentation
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
63,14 → 64,10
Bit_Rate : real;
Enable_Parity : boolean;
Parity_Odd_Even_n : std_logic;
Sys_Freq : real;
Reset_Level : std_logic;
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
83,6 → 80,10
 
architecture behave of o8_async_serial is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
signal FIFO_Reset : std_logic := '0';
 
constant User_Addr : std_logic_vector(15 downto 1) :=
109,7 → 110,7
signal TX_Xmit : std_logic := '0';
signal TX_Done : std_logic := '0';
 
constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
 
signal CTS_sr : std_logic_vector(3 downto 0) := "0000";
alias CTS_Okay is CTS_sr(3);
/o8_btn_int.vhd
33,6 → 33,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 01/22/20 Re-write of original with separate debouncer
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
47,14 → 48,9
generic(
Num_Buttons : integer range 1 to 8 := 8;
Button_Level : std_logic := '0';
Address : ADDRESS_TYPE := x"0000";
Reset_Level : std_logic := '1'
Address : ADDRESS_TYPE := x"0000"
);
port(
Clock : in std_logic := '0';
Reset : in std_logic := '0';
uSec_Tick : in std_logic := '0';
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
65,6 → 61,10
 
architecture behave of o8_btn_int is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
/o8_clk_detect.vhd
29,6 → 29,11
-- 0x00 BA------ Recieve Clock Status (RO)
-- A = Clock Line State (follows input)
-- B = Clock Detect (1 = transition detected)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
42,13 → 47,9
entity o8_clk_detect is
generic(
Threshold_Count : integer;
Address : ADDRESS_TYPE;
Reset_Level : std_logic
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Ref_Clk_In : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
59,6 → 60,9
 
architecture behave of o8_clk_detect is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
/o8_cpu.vhd
202,6 → 202,8
-- the I bit.
-- Also added the I bit to the exported flags for
-- use in memory protection schemes.
-- Seth Henry 04/16/20 Modified to use new Open8 bus record. Also added
-- reset and usec_tick logic to drive utility signals
 
library ieee;
use ieee.std_logic_1164.all;
223,14 → 225,14
BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
Enable_NMI : boolean := true; -- Force INTR0 enabled
Sequential_Interrupts : boolean := false; -- Interruptable ISRs
RTI_Ignores_GP_Flags : boolean := false; -- RTI restores all flags
RTI_Ignores_GP_Flags : boolean := false; -- RTI sets all flags
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
Reset_Level : std_logic := '0' ); -- Active reset level
Clock_Frequency : real -- Clock Frequency
);
port(
Clock : in std_logic;
Reset : in std_logic;
PLL_Locked : in std_logic;
CPU_Halt : in std_logic := '0';
GP_Flags : out EXT_GP_FLAGS;
--
Open8_Bus : out OPEN8_BUS_TYPE;
Rd_Data : in DATA_TYPE;
240,6 → 242,16
 
architecture behave of o8_cpu is
 
signal Reset_q : std_logic := Reset_Level;
signal Reset : std_logic := Reset_Level;
 
constant USEC_VAL : integer := integer(Clock_Frequency / 1000000.0);
constant USEC_WDT : integer := ceil_log2(USEC_VAL - 1);
constant USEC_DLY : std_logic_vector :=
conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
signal uSec_Cntr : std_logic_vector( USEC_WDT - 1 downto 0 );
signal uSec_Tick : std_logic;
 
constant INT_VECTOR_0 : ADDRESS_TYPE := ISR_Start_Addr;
constant INT_VECTOR_1 : ADDRESS_TYPE := ISR_Start_Addr+2;
constant INT_VECTOR_2 : ADDRESS_TYPE := ISR_Start_Addr+4;
289,7 → 301,39
 
begin
 
-------------------------------------------------------------------------------
-- Reset & uSec Tick
-------------------------------------------------------------------------------
 
CPU_Reset_Sync: process( Clock, PLL_Locked )
begin
if( PLL_Locked = '0' )then
Reset_q <= Reset_Level;
Reset <= Reset_Level;
elsif( rising_edge(Clock) )then
Reset_q <= not Reset_Level;
Reset <= Reset_q;
end if;
end process;
 
uSec_Tick_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
uSec_Cntr <= USEC_DLY;
uSec_Tick <= '0';
elsif( rising_edge( Clock ) )then
uSec_Cntr <= uSec_Cntr - 1;
if( or_reduce(uSec_Cntr) = '0' )then
uSec_Cntr <= USEC_DLY;
end if;
uSec_Tick <= nor_reduce(uSec_Cntr);
end if;
end process;
 
Open8_Bus.Clock <= Clock;
Open8_Bus.Reset <= Reset;
Open8_Bus.uSec_Tick <= uSec_Tick;
 
-------------------------------------------------------------------------------
-- Address bus selection/generation logic
-------------------------------------------------------------------------------
916,7 → 960,7
end loop;
Flags <= x"00";
 
GP_Flags <= (others => '0');
Open8_Bus.GP_Flags <= (others => '0');
 
elsif( rising_edge(Clock) )then
 
1253,7 → 1297,7
null;
end case;
 
GP_Flags <= Flags(7 downto 3);
Open8_Bus.GP_Flags <= Flags(7 downto 3);
 
end if;
end process;
/o8_crc16_ccitt.vhd
41,6 → 41,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/19/19 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
51,13 → 52,9
 
entity o8_crc16_ccitt is
generic(
Reset_Level : std_logic := '1';
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
65,6 → 62,9
 
architecture behave of o8_crc16_ccitt is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant Poly_Init : std_logic_vector(15 downto 0) :=
(others => '0');
 
/o8_datalatch.vhd
36,6 → 36,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 01/22/20 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
45,13 → 46,9
 
entity o8_datalatch is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
63,6 → 60,9
 
architecture behave of o8_datalatch is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
/o8_epoch_timer.vhd
53,6 → 53,7
-- Seth Henry 12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
-- Seth Henry 04/10/20 Overhauled the register interface of the timer to
-- make the interface more sensible to software.
-- Seth Henry 04/160/20 Modified to make use of Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
65,14 → 66,9
 
entity o8_epoch_timer is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
81,6 → 77,10
 
architecture behave of o8_epoch_timer is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
 
/o8_epoch_timer_ii.vhd
59,6 → 59,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
-- change.
-- Seth Henry 04/16/20 Modifiefd to make use of Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
71,14 → 72,9
 
entity o8_epoch_timer_ii is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
87,6 → 83,10
 
architecture behave of o8_epoch_timer_ii is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 4)
:= Address(15 downto 4);
 
/o8_gpin.vhd
33,6 → 33,7
-- Seth Henry 12/19/19 Renamed to "o8_gpin" to fit "theme"
-- Seth Henry 12/20/19 Added metastability registers
-- Seth Henry 04/10/20 Code Cleanup
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
42,13 → 43,9
 
entity o8_gpin is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
57,6 → 54,8
end entity;
 
architecture behave of o8_gpin is
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
/o8_gpio.vhd
37,6 → 37,7
-- Seth Henry 04/10/20 Code cleanup and register documentation
-- Also removed "input only" generic, as there is a
-- separate module for that
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
48,13 → 49,9
generic(
Default_Out : DATA_TYPE := x"00";
Default_En : DATA_TYPE := x"00";
Reset_Level : std_logic := '1';
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
64,6 → 61,9
 
architecture behave of o8_gpio is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
/o8_gpout.vhd
39,6 → 39,7
-- Seth Henry 07/28/11 Design Start
-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
-- Seth Henry 04/10/20 Code Cleanup and comments
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
48,76 → 49,75
 
entity o8_gpout is
generic(
Default_Out : DATA_TYPE := x"00";
Default_En : DATA_TYPE := x"00";
Disable_Tristate : boolean := false;
Reset_Level : std_logic;
Address : ADDRESS_TYPE
Default_Out : DATA_TYPE := x"00";
Default_En : DATA_TYPE := x"00";
Disable_Tristate : boolean := false;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
GPO : out DATA_TYPE
GPO : out DATA_TYPE
);
end entity;
 
architecture behave of o8_gpout is
 
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
alias Reg_Addr is Open8_Bus.Address(0);
signal Reg_Sel : std_logic := '0';
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
signal User_Out : DATA_TYPE := x"00";
signal User_En : DATA_TYPE := x"00";
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
alias Reg_Addr is Open8_Bus.Address(0);
signal Reg_Sel : std_logic := '0';
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
 
signal User_Out : DATA_TYPE := x"00";
signal User_En : DATA_TYPE := x"00";
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= '0';
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
User_Out <= Default_Out;
Reg_Sel <= '0';
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
User_Out <= Default_Out;
if( not Disable_Tristate)then
User_En <= Default_En;
User_En <= Default_En;
end if;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Reg_Sel <= Reg_Addr;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
if( Disable_Tristate )then
User_Out <= Wr_Data_q;
User_Out <= Wr_Data_q;
else
if( Reg_Sel = '0' )then
User_Out <= Wr_Data_q;
User_Out <= Wr_Data_q;
else
User_En <= Wr_Data_q;
User_En <= Wr_Data_q;
end if;
end if;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= User_Out;
Rd_Data <= User_Out;
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
Rd_Data <= User_En;
Rd_Data <= User_En;
end if;
end if;
end if;
124,7 → 124,7
end process;
 
No_Tristates: if( Disable_Tristate )generate
GPO <= User_Out;
GPO <= User_Out;
end generate;
 
Tristates: if( not Disable_Tristate )generate
132,9 → 132,9
Output_Ctl_proc: process( User_Out, User_En )
begin
for i in 0 to 7 loop
GPO(i) <= 'Z';
GPO(i) <= 'Z';
if( User_En(i) = '1' )then
GPO(i) <= User_Out(i);
GPO(i) <= User_Out(i);
end if;
end loop;
end process;
/o8_hd44780_4b.vhd
72,6 → 72,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 01/22/13 Design Start
-- Seth Henry 04/10/20 Code & comment cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
87,16 → 88,10
Default_Contrast : std_logic_vector(7 downto 0);
Use_Backlight : boolean;
Default_Brightness : std_logic_vector(7 downto 0);
Address : ADDRESS_TYPE;
Reset_Level : std_logic;
Sys_Freq : real
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
uSec_Tick : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
112,6 → 107,10
 
architecture behave of o8_hd44780_4b is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
159,7 → 158,7
 
signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0);
 
constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
constant SNH_600NS : integer := integer(Clock_Frequency * 0.000000600);
constant SNH_BITS : integer := ceil_log2(SNH_600NS);
constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
/o8_hd44780_8b.vhd
72,6 → 72,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 01/22/13 Design Start
-- Seth Henry 04/10/20 Code & comment cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
87,15 → 88,10
Default_Contrast : std_logic_vector(7 downto 0);
Use_Backlight : boolean;
Default_Brightness : std_logic_vector(7 downto 0);
Address : ADDRESS_TYPE;
Reset_Level : std_logic;
Sys_Freq : real
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
111,6 → 107,10
 
architecture behave of o8_hd44780_8b is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
157,7 → 157,7
 
signal busy_timer : std_logic_vector(INIT_BITS-1 downto 0) := (others => '0');
 
constant SNH_600NS : integer := integer(Sys_Freq * 0.000000600);
constant SNH_600NS : integer := integer(Clock_Frequency * 0.000000600);
constant SNH_BITS : integer := ceil_log2(SNH_600NS);
constant SNH_DELAY : std_logic_vector(SNH_BITS-1 downto 0) :=
conv_std_logic_vector(SNH_600NS-1, SNH_BITS);
/o8_lfsr32.vhd
33,6 → 33,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/25/18 Design Start
-- Seth Henry 04/10/20 Code cleanup and comments
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
44,13 → 45,9
entity o8_lfsr32 is
generic(
Init_Seed : std_logic_vector(31 downto 0) := x"CAFEBABE";
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
58,6 → 55,9
 
architecture behave of o8_lfsr32 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
/o8_ltc2355_2p.vhd
30,6 → 30,14
-- Notes : Depends on the fact that the two LTC2355 converters are wired
-- : with their SCLK and CONV lines tied together, and DATA1 and
-- : DATA2 independently routed to separate I/O pins.
--
-- : Works best when the clock frequency is 96MHz or lower. Module
-- : will divide the clock by 2 if it is greater than this.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
42,15 → 50,10
 
entity o8_ltc2355_2p is
generic(
Address : ADDRESS_TYPE;
Reset_Level : std_logic;
Sys_Freq : real
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic; -- 96MHz MAX for proper operation
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
64,8 → 67,12
 
architecture behave of o8_ltc2355_2p is
 
constant Divide_SCLK_by_2 : boolean := (Sys_Freq > 96000000.0);
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant Divide_SCLK_by_2 : boolean := (Clock_Frequency > 96000000.0);
 
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
alias Reg_Sel is Open8_Bus.Address(2 downto 0);
/o8_max7221.vhd
29,6 → 29,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 01/22/20 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
41,15 → 42,11
 
entity o8_max7221 is
generic(
Bit_Rate : real := 5000000.0;
Sys_Freq : real;
Reset_Level : std_logic;
Bitclock_Frequency : real := 5000000.0;
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
--
Mx_Data : out std_logic;
60,6 → 57,9
 
architecture behave of o8_max7221 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
signal FIFO_Reset : std_logic;
 
constant User_Addr : std_logic_vector(15 downto 4) :=
79,7 → 79,8
signal TX_En : std_logic;
signal TX_Idle : std_logic;
 
constant BAUD_DLY_VAL : integer := integer((Sys_Freq / Bit_Rate)/ 2.0);
constant BAUD_DLY_RATIO : real := (Clock_Frequency / Bitclock_Frequency);
constant BAUD_DLY_VAL : integer := integer(BAUD_DLY_RATIO * 0.5);
constant BAUD_DLY_WDT : integer := ceil_log2(BAUD_DLY_VAL - 1);
constant BAUD_DLY : std_logic_vector :=
conv_std_logic_vector(BAUD_DLY_VAL - 1, BAUD_DLY_WDT);
/o8_pwm16.vhd
40,6 → 40,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/25/18 Design Start
-- Seth Henry 04/10/20 Code cleanup and comments
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
51,14 → 52,9
 
entity o8_pwm16 is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
69,6 → 65,10
 
architecture behave of o8_pwm16 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 3) :=
Address(15 downto 3);
 
/o8_ram_1k.vhd
23,6 → 23,11
--
-- VHDL Units : o8_ram_1k
-- Description: Provides a wrapper layer for a 1kx8 RAM model
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
34,13 → 39,9
 
entity o8_ram_1k is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
48,6 → 49,9
 
architecture behave of o8_ram_1k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 10)
:= Address(15 downto 10);
alias Comp_Addr is Open8_Bus.Address(15 downto 10);
/o8_ram_4k.vhd
23,6 → 23,11
--
-- VHDL Units : o8_ram_1k
-- Description: Provides a wrapper layer for a 1kx8 RAM model
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
34,13 → 39,9
 
entity o8_ram_4k is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
48,6 → 49,9
 
architecture behave of o8_ram_4k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 12)
:= Address(15 downto 12);
alias Comp_Addr is Open8_Bus.Address(15 downto 12);
/o8_register.vhd
32,6 → 32,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/20/19 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
45,13 → 46,9
entity o8_register is
generic(
Default_Value : DATA_TYPE := x"00";
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
61,6 → 58,9
 
architecture behave of o8_register is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
/o8_rom_32k.vhd
23,6 → 23,11
--
-- VHDL Units : o8_rom_32k
-- Description: Provides a wrapper layer for a 32kx8 ROM model
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
34,13 → 39,9
 
entity o8_rom_32k is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE
);
48,6 → 49,9
 
architecture behave of o8_rom_32k is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 15) :=
Address(15 downto 15);
alias Comp_Addr is Open8_Bus.Address(15 downto 15);
/o8_rtc.vhd
42,6 → 42,11
-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
-- A = Update is Busy
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
54,15 → 59,9
 
entity o8_rtc is
generic(
Sys_Freq : real;
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : out std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
73,6 → 72,10
 
architecture behave of o8_rtc is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
85,15 → 88,6
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
 
constant DLY_1USEC_VAL : integer := integer(Sys_Freq / 1000000.0);
constant DLY_1USEC_WDT : integer := ceil_log2(DLY_1USEC_VAL - 1);
constant DLY_1USEC : std_logic_vector :=
conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
 
signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
:= (others => '0');
signal uSec_Tick_i : std_logic;
 
type PIT_TYPE is record
timer_cnt : DATA_TYPE;
timer_ro : std_logic;
152,7 → 146,6
 
begin
 
uSec_Tick <= uSec_Tick_i;
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
Interrupt_PIT <= pit.timer_ro;
161,9 → 154,6
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
uSec_Cntr <= (others => '0');
uSec_Tick_i <= '0';
 
pit.timer_cnt <= x"00";
pit.timer_ro <= '0';
 
217,15 → 207,8
 
elsif( rising_edge( Clock ) )then
 
uSec_Cntr <= uSec_Cntr - 1;
uSec_Tick_i <= '0';
if( uSec_Cntr = 0 )then
uSec_Cntr <= DLY_1USEC;
uSec_Tick_i <= '1';
end if;
 
-- Periodic Interval Timer
pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
pit.timer_cnt <= pit.timer_cnt - uSec_Tick;
pit.timer_ro <= '0';
if( update_interval = '1' )then
pit.timer_cnt <= interval;
235,7 → 218,7
end if;
 
-- Fractional decisecond counter - cycles every 10k microseconds
rtc.frac <= rtc.frac - uSec_Tick_i;
rtc.frac <= rtc.frac - uSec_Tick;
rtc.frac_ro <= '0';
if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
rtc.frac <= DECISEC;
/o8_sdlc_if.vhd
59,6 → 59,11
-- by a start followed by a stop flag. Incomplete frames are ignored.
-- 2) If too many bytes are received (buffer overflow), a value of
-- ERR_LENGTH is written.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
 
library ieee;
use ieee.std_logic_1164.all;
78,15 → 83,11
Poly_Init : std_logic_vector(15 downto 0) := x"0000";
Set_As_Master : boolean := true;
Clock_Offset : integer := 6;
BitClock_Freq : real := 500000.0;
Sys_Freq : real := 100000000.0;
Reset_Level : std_logic := '1';
BitClock_Frequency : real := 500000.0;
Clock_Frequency : real := 100000000.0;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
100,6 → 101,9
 
architecture behave of o8_sdlc_if is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant Base_Addr : std_logic_vector(15 downto 9)
:= Address(15 downto 9);
 
296,9 → 300,9
U_BCLK : entity work.sdlc_serial_clk
generic map(
Set_As_Master => Set_As_Master,
BitClock_Freq => BitClock_Freq,
BitClock_Freq => BitClock_Frequency,
Reset_Level => Reset_Level,
Sys_Freq => Sys_Freq
Sys_Freq => Clock_Frequency
)
port map(
Clock => Clock,
/o8_status_led.vhd
39,6 → 39,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/20/19 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
51,13 → 52,9
 
entity o8_status_led is
generic(
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
67,6 → 64,9
 
architecture behave of o8_status_led is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
/o8_sys_timer.vhd
37,6 → 37,7
-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
-- interval write.
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
49,15 → 50,9
 
entity o8_sys_timer is
generic(
Sys_Freq : real;
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : out std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
66,6 → 61,10
 
architecture behave of o8_sys_timer is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
78,17 → 77,8
signal Update_Interval : std_logic;
signal Timer_Cnt : DATA_TYPE := x"00";
 
constant DLY_1USEC_VAL : integer := integer(Sys_Freq / 1000000.0);
constant DLY_1USEC_WDT : integer := ceil_log2(DLY_1USEC_VAL - 1);
constant DLY_1USEC : std_logic_vector :=
conv_std_logic_vector(DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
 
signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 )
:= (others => '0');
signal uSec_Tick_i : std_logic := '0';
begin
 
uSec_Tick <= uSec_Tick_i;
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
117,21 → 107,6
end if;
end process;
 
uSec_Tick_i_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
uSec_Cntr <= (others => '0');
uSec_Tick_i <= '0';
elsif( rising_edge( Clock ) )then
uSec_Cntr <= uSec_Cntr - 1;
uSec_Tick_i <= '0';
if( uSec_Cntr = 0 )then
uSec_Cntr <= DLY_1USEC;
uSec_Tick_i <= '1';
end if;
end if;
end process;
 
Interval_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
139,7 → 114,7
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Interrupt <= '0';
Timer_Cnt <= Timer_Cnt - uSec_Tick_i;
Timer_Cnt <= Timer_Cnt - uSec_Tick;
if( Update_Interval = '1' )then
Timer_Cnt <= Interval;
elsif( or_reduce(Timer_Cnt) = '0' )then
/o8_vdsm12.vhd
36,6 → 36,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/18/19 Design start
-- Seth Henry 04/10/20 Code Cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
47,22 → 48,22
 
entity o8_vdsm12 is
generic(
Reset_Level : std_logic := '1';
Default_Value : std_logic_vector(11 downto 0) := x"000";
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
PDM_Out : out std_logic
DACOut : out std_logic
);
end entity;
 
architecture behave of o8_vdsm12 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
198,7 → 199,7
Wr_Data_q <= x"00";
DAC_Val_LB <= x"00";
DAC_Val_UB <= x"0";
DAC_Val <= (others => '0');
DAC_Val <= Default_Value;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
 
271,7 → 272,7
PWM_Period <= (others => '0');
Period_Ctr <= (others => '0');
Width_Ctr <= (others => '0');
PDM_Out <= '0';
DACOut <= '0';
elsif( rising_edge(Clock) )then
q <= diff(DIV_WIDTH-1 downto 0) &
q(DIV_WIDTH-2 downto 0) & '1';
293,9 → 294,9
Period_Ctr <= Period_Ctr - 1;
Width_Ctr <= Width_Ctr - 1;
 
PDM_Out <= '1';
DACOut <= '1';
if( Width_Ctr = 0 )then
PDM_Out <= '0';
DACOut <= '0';
Width_Ctr <= (others => '0');
end if;
 
/o8_vdsm8.vhd
33,6 → 33,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 06/23/16 Design start
-- Seth Henry 04/10/20 Code Cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
 
library ieee;
use ieee.std_logic_1164.all;
45,13 → 46,9
entity o8_vdsm8 is
generic(
Default_Value : DATA_TYPE := x"00";
Reset_Level : std_logic;
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
61,6 → 58,9
 
architecture behave of o8_vdsm8 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);

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