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Rev 240 → Rev 241

/o8_7seg.vhd
0,0 → 1,259
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Units : o8_register
-- Description: Provides a single addressible 8-bit output register
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 ---AAAAA Display 1 value (RW)
-- 0x01 ---AAAAA Display 2 value (RW)
-- 0x02 AAAAAAAA Display 1 brightness (RW)
-- 0x03 AAAAAAAA Display 2 brightness (RW)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/08/19 Design Start
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_7seg is
generic(
Default_LED1_Value : std_logic_vector(4 downto 0);
Default_LED1_Bright : DATA_TYPE := x"FF";
Default_LED2_Value : std_logic_vector(4 downto 0);
Default_LED2_Bright : DATA_TYPE := x"FF";
Common_Cathode : boolean := TRUE;
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
SegLED1 : out std_logic_vector(6 downto 0);
SegLED2 : out std_logic_vector(6 downto 0)
);
end entity;
 
architecture behave of o8_7seg is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic;
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0);
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
 
signal LED1_Reg : std_logic_vector(4 downto 0);
signal LED1_Brt : DATA_TYPE;
signal LED2_Reg : std_logic_vector(4 downto 0);
signal LED2_Brt : DATA_TYPE;
 
 
signal LED1_PDM : std_logic;
signal LED1_Ext : std_logic_vector(6 downto 0);
 
signal LED2_PDM : std_logic;
signal LED2_Ext : std_logic_vector(6 downto 0);
 
signal SegLED1_Full : std_logic_vector(6 downto 0);
signal SegLED2_Full : std_logic_vector(6 downto 0);
 
-- Standard 7-Segment Numeric Display
--
-- -A-
-- | |
-- F B
-- | |
-- -G-
-- | |
-- E C
-- | |
-- -D- (DP)
 
type LED_DEFS_TYPE is array(0 to 31) of std_logic_vector(6 downto 0);
constant CHAR_DEFINITIONS : LED_DEFS_TYPE := (
-- GFEDCBA
"0111111", -- 00 -> 0
"0000110", -- 01 -> 1
"1011011", -- 02 -> 2
"1001111", -- 03 -> 3
"1100110", -- 04 -> 4
"1101101", -- 05 -> 5
"1111101", -- 06 -> 6
"0000111", -- 07 -> 7
"1111111", -- 08 -> 8
"1101111", -- 09 -> 9
"1110111", -- 10 -> A
"1111100", -- 11 -> B
"1011000", -- 12 -> C
"1011110", -- 13 -> D
"1111001", -- 14 -> E
"1110001", -- 15 -> F
"0111101", -- 16 -> G
"1110110", -- 17 -> H
"0000100", -- 18 -> i
"0001110", -- 19 -> J
"0111000", -- 20 -> L
"1010100", -- 21 -> n
"1011100", -- 22 -> o
"1110011", -- 23 -> P
"1010000", -- 24 -> r
"0011100", -- 25 -> u
"1101110", -- 26 -> y
"1000000", -- 27 -> -
"1001000", -- 28 -> =
"1100011", -- 29 -> DEG
"0000010", -- 30 -> '
"0000000" -- 31 -> " "
);
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Wr_En <= '0';
Wr_Data_q <= x"00";
LED1_Reg <= Default_LED1_Value;
LED2_Reg <= Default_LED2_Value;
LED1_Brt <= Default_LED1_Bright;
LED2_Brt <= Default_LED2_Bright;
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
case( Reg_Sel )is
when "00" =>
LED1_Reg <= Wr_Data_q(4 downto 0);
when "01" =>
LED2_Reg <= Wr_Data_q(4 downto 0);
when "10" =>
LED1_Brt <= Wr_Data_q;
when "11" =>
LED2_Brt <= Wr_Data_q;
when others =>
null;
end case;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Sel )is
when "00" =>
Rd_Data <= "000" & LED1_Reg;
when "01" =>
Rd_Data <= "000" & LED2_Reg;
when "10" =>
Rd_Data <= LED1_Brt;
when "11" =>
Rd_Data <= LED2_Brt;
when others =>
null;
end case;
end if;
end if;
end process;
 
U_LED1_PWM : entity work.vdsm8
generic map(
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
DACin => LED1_Brt,
DACout => LED1_PDM
);
 
U_LED2_PWM : entity work.vdsm8
generic map(
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
DACin => LED2_Brt,
DACout => LED2_PDM
);
 
LED1_Ext <= (others => LED1_PDM);
LED2_Ext <= (others => LED2_PDM);
 
SegLED1_Full <= CHAR_DEFINITIONS(conv_integer(LED1_Reg));
SegLED2_Full <= CHAR_DEFINITIONS(conv_integer(LED2_Reg));
 
Common_Cathode_Mode : if( Common_Cathode )generate
 
LUT_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
SegLED1 <= (others => '0');
SegLED2 <= (others => '0');
elsif( rising_edge(Clock) )then
SegLED1 <= (SegLED1_Full and LED1_Ext) xor "1111111";
SegLED2 <= (SegLED2_Full and LED2_Ext) xor "1111111";
end if;
end process;
 
end generate;
 
Common_Anode_Mode : if( not Common_Cathode )generate
 
LUT_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
SegLED1 <= (others => '1');
SegLED2 <= (others => '1');
elsif( rising_edge(Clock) )then
SegLED1 <= (SegLED1_Full and LED1_Ext);
SegLED2 <= (SegLED2_Full and LED2_Ext);
end if;
end process;
 
 
end generate;
 
end architecture;
/o8_pwm_adc.vhd
0,0 → 1,119
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Entity: pwm_adc
-- Description: Integrates a PWM input to return the approximate duty cycle
-- Uses a 1kB block ram as storage for a rolling integrator that
-- acts as a simple successive-approximation ADC.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/07/20 Design Start
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_pwm_adc is
generic(
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
--
PWM_In : in std_logic
);
end entity;
 
architecture behave of o8_pwm_adc is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 0) := Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
 
signal Sample : DATA_TYPE := x"00";
signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
signal RAM_Data : DATA_TYPE := x"00";
signal Accumulator : std_logic_vector(17 downto 0) := (others => '0');
signal Average : DATA_TYPE := x"00";
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
elsif( rising_edge( Clock ) )then
 
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_Data <= OPEN8_NULLBUS;
 
if( Rd_En = '1' )then
Rd_Data <= Average;
end if;
end if;
end process;
 
-- PWM input is binary, so the sample swings between 0x00 and 0xFF
Sample <= (others => PWM_In);
 
U_DP : entity work.o8_pwm_adc_ram
port map(
address => RAM_Addr,
clock => Clock,
data => Sample,
wren => '1',
q => RAM_Data
);
 
ADC_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
RAM_Addr <= (others => '0');
Accumulator <= (others => '0');
Average <= (others => '0');
elsif( rising_edge(Clock) )then
RAM_Addr <= RAM_Addr + 1;
Accumulator <= Accumulator + ("0000000000" & RAM_Data);
if( RAM_Addr = 0 )then
Accumulator <= (others => '0');
Average <= Accumulator(17 downto 10);
end if;
end if;
end process;
 
end architecture;
/o8_pwm_adc_ram.vhd
0,0 → 1,158
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: o8_pwm_adc_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY o8_pwm_adc_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END o8_pwm_adc_ram;
 
 
ARCHITECTURE SYN OF o8_pwm_adc_ram IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "LRAM"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_pwm_adc_ram_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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