URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 254 to Rev 255
- ↔ Reverse comparison
Rev 254 → Rev 255
/o8_cpu.vhd
87,6 → 87,13
-- : bypassing memory protection. Init code should clear the I bit |
-- : when done; |
-- : |
-- : Unsigned_Index_Offsets alters the way offsets are added to |
-- : [Rn+1:Rn] during LDO/STO instructions. The original, defeault |
-- : behavior treats these offsets as signed values, allowing |
-- : instructions to offset by -128 to +127 from [Rn+1:Rn]. |
-- : Setting this generic to TRUE will switch to unsigned offsets, |
-- : switching the range to 0 to 255 instead. |
-- : |
-- : Default_Interrupt_Mask sets the intial/reset value of the |
-- : interrupt mask. To remain true to the original core, which |
-- : had no interrupt mask, this should be set to x"FF". Otherwise |
337,8 → 344,13
constant INT_VECTOR_6 : std_logic_vector(3 downto 0) := x"C"; |
constant INT_VECTOR_7 : std_logic_vector(3 downto 0) := x"E"; |
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signal IDX_Offset_SX : std_logic := '0'; |
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signal IDX_Offset : ADDRESS_TYPE := x"0000"; |
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signal IDX_Sel_l : std_logic_vector(2 downto 0) := "000"; |
signal IDX_Sel_h : std_logic_vector(2 downto 0) := "000"; |
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signal IDX_Reg_l : integer := 0; |
signal IDX_Reg_h : integer := 0; |
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388,7 → 400,8
-- as adding pipeline registration would add a clock cycle to every instr, |
-- without really adding the Fmax to compensate. |
Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc, |
IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr, Program_Ctr ) |
IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr, |
Program_Ctr ) |
begin |
case( CPU_State )is |
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404,7 → 417,9
when ISR_C1 | ISR_C2 => |
Open8_Bus.Address <= ISR_Addr_Base & ISR_Addr_Offset; |
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when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 => |
when PSH_C1 | POP_C1 | |
ISR_C3 | JSR_C1 | JSR_C2 | |
RTS_C1 | RTS_C2 | RTS_C3 => |
Open8_Bus.Address <= Stack_Ptr; |
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when others => |
418,30 → 433,24
-- always helpful, so the generic allows the CPU to use unsigned math |
-- for the offsets. This makes the range 0 to +255 instead. |
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Unsigned_Idx_Offsets : if( Unsigned_Index_Offsets )generate |
IDX_Offset(15 downto 8) <= (others => '0'); |
IDX_Offset(7 downto 0) <= Operand1; |
end generate; |
IDX_Offset_SX <= '0' when Unsigned_Index_Offsets else Operand1(7); |
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Signed_Idx_Offsets: if( not Unsigned_Index_Offsets )generate |
IDX_Offset(15 downto 8) <= (others => Operand1(7)); |
IDX_Offset(15 downto 8) <= (others => IDX_Offset_SX); |
IDX_Offset(7 downto 0) <= Operand1; |
end generate; |
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-- Enable_Auto_Increment uses the LSB to determine whether or not to |
-- do the auto-increment, so we need to lock the LSB for each operand |
-- if it is enabled. This forces [ODD:EVEN] pairing. |
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Auto_Incr_Set: if( Enable_Auto_Increment )generate |
IDX_Reg_l <= conv_integer(SubOp(2 downto 1) & '0'); |
IDX_Reg_h <= conv_integer(SubOp(2 downto 1) & '1'); |
end generate; |
IDX_Sel_l <= (SubOp(2 downto 1) & '0') when Enable_Auto_Increment else |
SubOp; |
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Auto_Incr_Not_Set: if( not Enable_Auto_Increment )generate |
IDX_Reg_l <= conv_integer(SubOp); |
IDX_Reg_h <= conv_integer(SubOp_p1); |
end generate; |
IDX_Sel_h <= (SubOp(2 downto 1) & '1') when Enable_Auto_Increment else |
SubOp_p1; |
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IDX_Reg_l <= conv_integer(IDX_Sel_l); |
IDX_Reg_h <= conv_integer(IDX_Sel_h); |
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-- Pipeline registers for the indexed and indexed with offset addresses. |
Idx_Addr_Calc_proc: process( Clock, Reset ) |
variable Reg, Reg_1 : integer range 0 to 7 := 0; |