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    /open8_urisc/trunk/VHDL
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Rev 257 → Rev 258

/Open8_cfg.vhd
1,158 → 1,279
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
-- VHDL units : em_interface
-- Description: Connects all of the components that comprise the ROMEO/JAGM
-- ESAF test stimulus controller
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-- VHDL Units : open8_cfg
-- Description: Contains project specific constants to configure an Open8
-- system
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Design Start
-- Seth Henry 04/16/20 Version block added
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
library work;
use work.open8_pkg.all;
use work.open8_cfg.all;
 
package open8_cfg is
entity em_interface is
port(
-- Master oscillator
Ext_50M_Osc : in std_logic;
-- Push buttons
KEY0 : in std_logic;
KEY1 : in std_logic;
-- LED outputs
LEDS : out std_logic_vector(7 downto 0);
-- Configuration Switches
DIPSW : in std_logic_vector(3 downto 0);
-- GPINs (input only)
GPIN0 : in std_logic_vector(1 downto 0);
GPIN1 : in std_logic_vector(1 downto 0);
GPIN2 : in std_logic_vector(2 downto 0);
-- GPIO
GPIO0 : inout std_logic_vector(33 downto 0);
GPIO1 : inout std_logic_vector(33 downto 0);
GPIO2 : inout std_logic_vector(12 downto 0)
);
end entity;
 
-- Internal signals & constants
constant Clock_Frequency : real := 100000000.0;
architecture behave of em_interface is
 
-- Peripheral Options
-- I/O mapping aliases
 
-- SDLC Configuration
constant Master_Mode : boolean := true;
constant BitClock_Freq : real := 20000000.0;
constant Clock_Offset : integer := 3;
-- Clocks & Resets
alias Sys_Clock_50M is Ext_50M_Osc;
 
-- FM Serial Configuration
constant SERIAL_58_125K : real := 58125.0;
constant PARITY_ENABLE : boolean := true;
constant PARITY_ODD_EVENn : std_logic := '1';
-- External Pushbuttons
alias FMSIM_PB_Reset is GPIN2(0);
alias FPGA_PB_Reset is GPIN2(2);
alias DBG_PB is GPIO2(3);
 
-- MAX7221 Driver Configuration
constant MAX7221_BITRATE : real := 5000000.0;
-- Diagnostic
alias JP1_1 is GPIN0(0);
alias JP1_3 is GPIN0(1);
 
-- Test Vector Receiver Configuration
constant VECTOR_BITRATE : real := 10000000.0;
constant VECTOR_PARITY : boolean := TRUE;
constant VECTOR_ODD_EVENn : std_logic := '0';
alias JP1_37 is GPIO0(30);
alias JP1_38 is GPIO0(31);
alias JP1_39 is GPIO0(32);
alias JP1_40 is GPIO0(33);
 
-- Open8 CPU Options
constant Allow_Stack_Address_Move : boolean := true;
constant Stack_Xfer_Flag : integer := PSR_GP4;
constant Enable_Auto_Increment : boolean := true;
constant BRK_Implements_WAI : boolean := true;
constant Enable_NMI : boolean := true;
constant Sequential_Interrupts : boolean := true;
constant RTI_Ignores_GP_Flags : boolean := true;
constant Default_Int_Mask : DATA_TYPE := x"00";
alias JP2_4 is GPIO1(1);
 
-- System Memory Map
constant RAM_Address : ADDRESS_TYPE := x"0000"; -- System RAM
constant ALU_Address : ADDRESS_TYPE := x"1000"; -- ALU16 coprocessor
constant RTC_Address : ADDRESS_TYPE := x"1100"; -- System Timer / RT Clock
constant ETC_Address : ADDRESS_TYPE := x"1200"; -- Epoch Timer/Alarm Clock
constant TMR_Address : ADDRESS_TYPE := x"1400"; -- PIT timer
constant SDLC_Address : ADDRESS_TYPE := x"1800"; -- LCD serial interface
constant LED_Address : ADDRESS_TYPE := x"2000"; -- LED Display
constant DSW_Address : ADDRESS_TYPE := x"2100"; -- Dip Switches
constant BTN_Address : ADDRESS_TYPE := x"2200"; -- Push Buttons
constant SER_Address : ADDRESS_TYPE := x"2400"; -- UART interface
constant MAX_Address : ADDRESS_TYPE := x"2800"; -- Max 7221 base address
constant VEC_Address : ADDRESS_TYPE := x"3000"; -- Vector RX base address
constant CHR_Address : ADDRESS_TYPE := x"3100"; -- Elapsed Time / Chronometer
constant ROM_Address : ADDRESS_TYPE := x"8000"; -- Application ROM
constant ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- ISR Vector Table
-- Status LED
alias Status_LED is GPIO2(10);
 
-- RAM size is used to calculate the initial stack pointer, which is set at
-- the top of the RAM region.
constant RAM_Size : integer := 4096;
-- Telemetry Serial
alias TM_Tx_Out is GPIO1(0);
alias TM_CTS_In is GPIN1(1);
 
-- Interrupt assignments
-- These are assigned in order priority from 0 (highest) to 7 (lowest)
constant INT_PIT : integer range 0 to OPEN8_DATA_WIDTH - 1 := 0;
constant INT_ETC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 1;
constant INT_TMR : integer range 0 to OPEN8_DATA_WIDTH - 1 := 2;
constant INT_ALU : integer range 0 to OPEN8_DATA_WIDTH - 1 := 3;
constant INT_RTC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 4;
constant INT_SDLC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 5;
constant INT_BTN : integer range 0 to OPEN8_DATA_WIDTH - 1 := 6;
constant INT_VEC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 7;
-- Vector RX (TS Input)
alias Vec_Rx is GPIN1(0);
 
-- Set this to the number of readable modules (entities wth a Rd_Data port) in the design,
-- as it sets the number of ports on the read aggregator function.
constant NUM_READ_BUSES : integer := 13;
-- MAX 7221 SPI Interface
alias MX_LDCSn is GPIO2(9);
alias Mx_Clock is GPIO2(5);
alias Mx_Data is GPIO2(7);
 
-- Read Data Bus aggregator and bus assignments.
-- Note that the ordering isn't important, only that each device has a
-- unique number less than READ_BUS_COUNT.
constant RDB_RAM : integer range 0 to NUM_READ_BUSES - 1 := 0;
constant RDB_ALU : integer range 0 to NUM_READ_BUSES - 1 := 1;
constant RDB_RTC : integer range 0 to NUM_READ_BUSES - 1 := 2;
constant RDB_TMR : integer range 0 to NUM_READ_BUSES - 1 := 3;
constant RDB_ETC : integer range 0 to NUM_READ_BUSES - 1 := 4;
constant RDB_LED : integer range 0 to NUM_READ_BUSES - 1 := 5;
constant RDB_DSW : integer range 0 to NUM_READ_BUSES - 1 := 6;
constant RDB_BTN : integer range 0 to NUM_READ_BUSES - 1 := 7;
constant RDB_SDLC : integer range 0 to NUM_READ_BUSES - 1 := 8;
constant RDB_SER : integer range 0 to NUM_READ_BUSES - 1 := 9;
constant RDB_VEC : integer range 0 to NUM_READ_BUSES - 1 := 10;
constant RDB_CHR : integer range 0 to NUM_READ_BUSES - 1 := 11;
constant RDB_ROM : integer range 0 to NUM_READ_BUSES - 1 := 12;
-- SDLC Serial Interface
alias SDLC_EM2IF is GPIO0(18);
alias SDLC_Clock is GPIO0(19);
alias SDLC_IF2EM is GPIO0(20);
 
-- System configuration calculations - no adjustable parameters below this point
type OPEN8_BUS_ARRAY is array(0 to NUM_READ_BUSES - 1) of DATA_TYPE;
-- Relay/Discrete I/O
alias EM_Elec_Power is GPIO2(8);
alias EM_Arm_Power is GPIO0(29);
alias EM_Separation is GPIO0(5);
alias EM_Detonate_Cmd_1 is GPIO0(17);
alias EM_Detonate_Cmd_2 is GPIO0(9);
alias EM_Test_G1 is GPIO0(7);
alias EM_Test_G2 is GPIO0(11);
alias EM_Test_Mode is GPIO0(2);
 
constant INIT_READ_BUS : OPEN8_BUS_ARRAY := (others => OPEN8_NULLBUS);
alias EM_Config_ID_1 is GPIO0(0);
alias EM_Config_ID_2 is GPIO0(4);
alias EM_Config_ID_3 is GPIO0(8);
alias EM_Spare_1 is GPIO0(1);
alias EM_Int_Impact is GPIO0(3);
alias EM_FPGA_POR_Reset is GPIO0(6);
alias EM_PIC_POR_Reset is GPIO0(10);
alias EM_Spare_Rly is GPIO0(12);
 
function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE;
alias EM_Accel_PDM is GPIO2(11);
 
-- Compute the stack start address based on the RAM size
constant RAM_Vector_Size : integer := ceil_log2(RAM_Size - 1);
constant RAM_End_Addr : std_logic_vector(RAM_Vector_Size - 1 downto 0)
:= (others => '1');
-- Unused EM signals
alias EM_TXD_TST is GPIO0(13);
alias EM_Aux_In_1 is GPIO0(14);
alias EM_Aux_Out_1 is GPIO0(15);
alias EM_RCV_TST is GPIO0(16);
 
constant Stack_Start_Addr : ADDRESS_TYPE := RAM_Address + RAM_End_Addr;
-- PC FM Simulator IF (NANO)
alias PC_Contact is GPIO0(26);
alias PC_EM2FM is GPIO0(27);
alias PC_FM2EM is GPIO0(28);
alias PC_Fire_Out is GPIO0(21);
 
end package;
-- MC FM Simulator IF (NANO)
alias MC_Contact is GPIO0(23);
alias MC_EM2FM is GPIO0(24);
alias MC_FM2EM is GPIO0(25);
alias MC_Fire_Out is GPIO0(22);
 
package body open8_cfg is
-- NI DIO
alias NI_P0_0 is GPIO1(17);
alias NI_P0_1 is GPIO1(2);
alias NI_P0_2 is GPIO1(15);
alias NI_P0_3 is GPIO1(4);
alias NI_P0_4 is GPIO1(13);
alias NI_P0_5 is GPIO1(6);
alias NI_P0_6 is GPIO1(11);
alias NI_P0_7 is GPIO1(8);
 
function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE is
variable i : integer := 0;
variable retval : DATA_TYPE := x"00";
alias NI_P1_0 is GPIO1(9);
alias NI_P1_1 is GPIO1(10);
alias NI_P1_2 is GPIO1(7);
alias NI_P1_3 is GPIO1(12);
alias NI_P1_4 is GPIO1(5);
alias NI_P1_5 is GPIO1(14);
alias NI_P1_6 is GPIO1(3);
alias NI_P1_7 is GPIO1(16);
 
alias NI_P2_0 is GPIO1(33);
alias NI_P2_1 is GPIO1(18);
alias NI_P2_2 is GPIO1(31);
alias NI_P2_3 is GPIO1(20);
alias NI_P2_4 is GPIO1(29);
alias NI_P2_5 is GPIO1(22);
alias NI_P2_6 is GPIO1(27);
alias NI_P2_7 is GPIO1(20);
 
alias NI_P3_0 is GPIO1(25);
alias NI_P3_1 is GPIO1(26);
alias NI_P3_2 is GPIO1(23);
alias NI_P3_3 is GPIO1(28);
alias NI_P3_4 is GPIO1(21);
alias NI_P3_5 is GPIO1(30);
alias NI_P3_6 is GPIO1(19);
alias NI_P3_7 is GPIO1(32);
 
-- Internal mapping signals
 
signal Sys_Async_Reset : std_logic;
 
signal Ext_Switches : DATA_TYPE := x"00";
signal CPU_Flags : EXT_GP_FLAGS := "00000";
 
signal BAR_LED : DATA_TYPE := x"00";
 
signal Vec_Req : std_logic := '0';
signal Vec_Index : std_logic_vector(5 downto 0) := "000000";
signal Vec_Data : std_logic_vector(15 downto 0 ) := x"0000";
 
begin
 
Reset_Input_proc: process( Sys_Clock_50M, FPGA_PB_Reset, NI_P0_7 )
begin
retval := x"00";
for i in 0 to NUM_READ_BUSES - 1 loop
retval := retval or x(i);
end loop;
return retval;
end function;
if( FPGA_PB_Reset = '0' or NI_P0_7 = '1' )then
Sys_Async_Reset <= '0';
elsif( rising_edge( Sys_Clock_50M ) )then
Sys_Async_Reset <= '1';
end if;
end process;
 
end package body;
Vec_Req <= NI_P0_6;
 
Vec_Index <= NI_P0_5 & NI_P0_4 & NI_P0_3 &
NI_P0_2 & NI_P0_1 & NI_P0_0;
 
Vec_Data <= NI_P2_7 & NI_P2_6 & NI_P2_5 & NI_P2_4 &
NI_P2_3 & NI_P2_2 & NI_P2_1 & NI_P2_0 &
NI_P1_7 & NI_P1_6 & NI_P1_5 & NI_P1_4 &
NI_P1_3 & NI_P1_2 & NI_P1_1 & NI_P1_0;
 
NI_P3_0 <= BAR_LED(0);
NI_P3_1 <= BAR_LED(1);
NI_P3_2 <= BAR_LED(2);
NI_P3_3 <= BAR_LED(3);
NI_P3_4 <= BAR_LED(4);
NI_P3_5 <= BAR_LED(5);
NI_P3_6 <= BAR_LED(6);
NI_P3_7 <= BAR_LED(7);
 
LEDS <= BAR_LED;
 
Ext_Switches <= DIPSW & KEY1 & KEY0 & DBG_PB & FMSIM_PB_Reset;
 
JP1_37 <= CPU_Flags(EXT_ISR);
JP1_38 <= CPU_Flags(EXT_GP5);
JP1_39 <= CPU_Flags(EXT_GP6);
JP1_40 <= CPU_Flags(EXT_GP7);
 
U_CORE : entity work.em_core
port map(
Sys_Async_Reset => Sys_Async_Reset,
Sys_Clock_50M => Sys_Clock_50M,
 
-- Switches
Ext_Switches => Ext_Switches,
 
-- LEDS
BAR_LED => BAR_LED,
Status_LED => Status_LED,
 
-- CPU Flags
CPU_Flags => CPU_Flags,
 
-- Telemetry Serial
TM_Tx_Out => TM_Tx_Out,
TM_CTS_In => TM_CTS_In,
 
-- MAX 7221 SPI Interface
MX_LDCSn => MX_LDCSn,
Mx_Clock => Mx_Clock,
Mx_Data => Mx_Data,
 
-- Vector RX (Aux TS Input)
Vec_Req => Vec_Req,
Vec_Index => Vec_Index,
Vec_Data => Vec_Data,
Vec_Rx => Vec_Rx,
 
-- SDLC Serial Interface
SDLC_EM2IF => SDLC_EM2IF,
SDLC_Clock => SDLC_Clock,
SDLC_IF2EM => SDLC_IF2EM,
 
-- Relay/Discrete I/O
EM_Elec_Power => EM_Elec_Power,
EM_Arm_Power => EM_Arm_Power,
EM_Separation => EM_Separation,
EM_Detonate_Cmd_1 => EM_Detonate_Cmd_1,
EM_Detonate_Cmd_2 => EM_Detonate_Cmd_2,
EM_Test_G1 => EM_Test_G1,
EM_Test_G2 => EM_Test_G2,
EM_Test_Mode => EM_Test_Mode,
 
EM_Config_ID_1 => EM_Config_ID_1,
EM_Config_ID_2 => EM_Config_ID_2,
EM_Config_ID_3 => EM_Config_ID_3,
EM_Spare_1 => EM_Spare_1,
EM_Int_Impact => EM_Int_Impact,
EM_FPGA_POR_Reset => EM_FPGA_POR_Reset,
EM_PIC_POR_Reset => EM_PIC_POR_Reset,
EM_Spare_Rly => EM_Spare_Rly,
 
EM_Accel_PDM => EM_Accel_PDM,
 
-- PC FM Simulator IF
PC_Contact => PC_Contact,
PC_EM2FM => PC_EM2FM,
PC_FM2EM => PC_FM2EM,
PC_Fire_Out => PC_Fire_Out,
 
-- MC FM Simulator IF
MC_Contact => MC_Contact,
MC_EM2FM => MC_EM2FM,
MC_FM2EM => MC_FM2EM,
MC_Fire_Out => MC_Fire_Out
);
 
end architecture;
/o8_ltc2355_2p.vhd
106,6 → 106,7
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
/sys_tick.vhd
0,0 → 1,104
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Entity: sys_tick
-- Description: Provides a single clock tick every microsecond and millisecond.
-- Requires that the system clock frequency be passed as a real.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Code cleanup and revision section added
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
entity sys_tick is
generic(
Reset_Level : std_logic;
Sys_Freq : real := 50000000.0
);
port(
Clock : in std_logic;
Reset : in std_logic;
uSec_Tick : out std_logic;
mSec_Tick : out std_logic
);
end entity;
 
architecture behave of sys_tick is
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
 
constant DLY_1USEC_VAL : integer := integer(Sys_Freq / 1000000.0);
constant DLY_1USEC_WDT : integer := ceil_log2(DLY_1USEC_VAL - 1);
constant DLY_1USEC : std_logic_vector :=
conv_std_logic_vector( DLY_1USEC_VAL - 1, DLY_1USEC_WDT);
signal uSec_Cntr : std_logic_vector( DLY_1USEC_WDT - 1 downto 0 );
 
constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
conv_std_logic_vector(1000,10);
 
signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0');
 
begin
 
Tick_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
uSec_Cntr <= DLY_1USEC;
uSec_Tick <= '0';
 
mSec_Timer <= (others => '0');
mSec_Tick <= '0';
elsif( rising_edge( Clock ) )then
uSec_Cntr <= uSec_Cntr - 1;
uSec_Tick <= '0';
if( or_reduce(uSec_Cntr) = '0' )then
uSec_Cntr <= DLY_1USEC;
uSec_Tick <= '1';
mSec_Timer <= mSec_Timer - 1;
end if;
 
mSec_Tick <= '0';
if( mSec_Timer = 0 )then
mSec_Timer <= MSEC_DELAY;
mSec_Tick <= '1';
end if;
end if;
end process;
 
end architecture;

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