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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 262 to Rev 263
    ↔ Reverse comparison
  •

Rev 262 → Rev 263

/o8_cpu.vhd
821,6 → 821,10
 
when LDX_C2 =>
CPU_Next_State <= LDX_C3;
if( Enable_Auto_Increment and SubOp(0) = '1' )then
ALU_Ctrl.Oper <= ALU_UPP2;
ALU_Ctrl.Reg <= SubOp(2 downto 1) & '1';
end if;
PC_Ctrl.Offset <= PC_NEXT;
 
when LDX_C3 =>
1321,7 → 1325,7
-- The ALU code is responsible for (and should be the only code altering)
-- the register file. Most of the "instructions" directly map to opcodes
-- but a few are for internal use only, such as operations involving the
-- stack pointer of interrupt mask.
-- stack pointer or interrupt mask.
 
Index := conv_integer(ALU_Ctrl.Reg);
Sum := (others => '0');
1343,9 → 1347,8
Regfile(Index) <= Sum(7 downto 0);
 
when ALU_UPP2 => -- Rn = Rn + C
Sum := ("0" & x"00") +
("0" & Regfile(Index)) +
Flags(PSR_C);
Sum := (x"00" & Flags(PSR_C)) +
("0" & Regfile(Index));
Flags(PSR_C) <= Sum(8);
Regfile(Index) <= Sum(7 downto 0);
 
/o8_sdlc_if.vhd
90,7 → 90,8
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
TX_Interrupt : out std_logic;
RX_Interrupt : out std_logic;
-- Serial IO
SDLC_In : in std_logic;
SDLC_SClk : in std_logic;
161,8 → 162,6
signal TX_CRC_Data : CRC_OUT_TYPE := x"0000";
signal TX_CRC_Valid : std_logic := '0';
 
signal TX_Interrupt : std_logic := '0';
 
signal RX_Valid : std_logic := '0';
signal RX_Flag : std_logic := '0';
signal RX_Data : DATA_IN_TYPE;
176,8 → 175,6
signal RX_CRC_Valid : std_logic := '0';
signal RX_CRC_Data : CRC_OUT_TYPE := x"0000";
 
signal RX_Interrupt : std_logic := '0';
 
begin
 
-- ***************************************************************************
206,7 → 203,6
Reg_TxS_Sel <= '0';
DP_A_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Reg_Addr <= Reg_Upper_Addr;
Reg_Sel <= Reg_Lower_Addr;
224,8 → 220,6
if( DP_A_Rd_En_q = '1' )then
Rd_Data <= DP_A_Rd_Data;
end if;
 
Interrupt <= RX_Interrupt or TX_Interrupt;
end if;
end process;
 

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