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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path
    /open8_urisc/trunk/VHDL
    from Rev 273 to Rev 274
    Reverse comparison

Rev 273 → Rev 274

/o8_async_serial.vhd
29,7 → 29,7
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA TX Data (WR) RX Data (RD) (RW)
-- 0x01 EDCBA--- FIFO Status (RO*)
-- 0x01 EDCBA--- Status (RO*)
-- A: RX Parity Error (write to clear)
-- B: RX FIFO Empty
-- C: RX FIFO almost full (922/1024)
/o8_trig_delay.vhd
22,9 → 22,10
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Entity: o8_trig_delay
-- Description: Receives a 6-bit vector command and 16-bit argument from the
-- vector_tx entity. Issues interrupt to the CPU on receipt of
-- three bytes.
-- Description: Programmable delay timer with time-base selection. Allows both
-- they delay after triggering and pulse width to be set by
-- software. Output may either be routed to a pin or used to
-- trigger an interrupt.
--
-- Register Map:
-- Offset Bitfield Description Read/Write

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