URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 279 to Rev 280
- ↔ Reverse comparison
Rev 279 → Rev 280
/o8_sdlc_if.vhd
132,16 → 132,11
signal TX_Ctl_Len : std_logic := '0'; |
|
-- Dual-port memory |
signal DP_Addr : std_logic_vector(8 downto 0); |
signal DP_Wr_Data : DATA_TYPE; |
signal DP_Wr_En : std_logic; |
signal DP_Rd_Data : DATA_TYPE; |
signal DP_B_Addr : std_logic_vector(8 downto 0); |
signal DP_B_Wr_Data : DATA_TYPE; |
signal DP_B_Wr_En : std_logic; |
signal DP_B_Rd_Data : DATA_TYPE; |
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alias DP_B_Addr is DP_Addr; |
alias DP_B_Wr_Data is DP_Wr_Data; |
alias DP_B_Wr_En is DP_Wr_En; |
alias DP_B_Rd_Data is DP_Rd_Data; |
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-- Internal definitions |
constant SDLC_Flag : DATA_TYPE := x"7E"; |
|
396,9 → 391,9
if( Reset = Reset_Level )then |
DP_Arb_State <= IDLE; |
DP_Last_Port <= '0'; |
DP_Addr <= (others => '0'); |
DP_Wr_Data <= x"00"; |
DP_Wr_En <= '0'; |
DP_B_Addr <= (others => '0'); |
DP_B_Wr_Data <= x"00"; |
DP_B_Wr_En <= '0'; |
DP_Port0_RdData <= x"00"; |
DP_Port0_Ack <= '0'; |
DP_Port1_RdData <= x"00"; |
406,7 → 401,7
elsif( rising_edge(Clock) )then |
DP_Port0_Ack <= '0'; |
DP_Port1_Ack <= '0'; |
DP_Wr_En <= '0'; |
DP_B_Wr_En <= '0'; |
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case( DP_Arb_State )is |
when IDLE => |
418,9 → 413,9
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when PORT0_AD => |
DP_Last_Port <= '0'; |
DP_Addr <= '0' & DP_Port0_Addr; |
DP_Wr_Data <= DP_Port0_WrData; |
DP_Wr_En <= not DP_Port0_RWn; |
DP_B_Addr <= '0' & DP_Port0_Addr; |
DP_B_Wr_Data <= DP_Port0_WrData; |
DP_B_Wr_En <= not DP_Port0_RWn; |
if( DP_Port0_RWn = '1' )then |
DP_Arb_State <= PORT0_RD0; |
else |
436,14 → 431,14
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when PORT0_RD1 => |
DP_Port0_Ack <= '1'; |
DP_Port0_RdData <= DP_Rd_Data; |
DP_Port0_RdData <= DP_B_Rd_Data; |
DP_Arb_State <= PAUSE; |
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when PORT1_AD => |
DP_Last_Port <= '1'; |
DP_Addr <= '1' & DP_Port1_Addr; |
DP_Wr_Data <= DP_Port1_WrData; |
DP_Wr_En <= not DP_Port1_RWn; |
DP_B_Addr <= '1' & DP_Port1_Addr; |
DP_B_Wr_Data <= DP_Port1_WrData; |
DP_B_Wr_En <= not DP_Port1_RWn; |
if( DP_Port0_RWn = '1' )then |
DP_Arb_State <= PORT1_RD0; |
else |
459,7 → 454,7
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when PORT1_RD1 => |
DP_Port1_Ack <= '1'; |
DP_Port1_RdData <= DP_Rd_Data; |
DP_Port1_RdData <= DP_B_Rd_Data; |
DP_Arb_State <= PAUSE; |
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when PAUSE => |