URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 280 to Rev 281
- ↔ Reverse comparison
Rev 280 → Rev 281
/o8_sdlc_if.vhd
132,10 → 132,10
signal TX_Ctl_Len : std_logic := '0'; |
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-- Dual-port memory |
signal DP_B_Addr : std_logic_vector(8 downto 0); |
signal DP_B_Wr_Data : DATA_TYPE; |
signal DP_B_Wr_En : std_logic; |
signal DP_B_Rd_Data : DATA_TYPE; |
signal DP_B_Addr : std_logic_vector(8 downto 0) := (others => '0'); |
signal DP_B_Wr_Data : DATA_TYPE := x"00"; |
signal DP_B_Wr_En : std_logic := '0'; |
signal DP_B_Rd_Data : DATA_TYPE := x"00"; |
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-- Internal definitions |
constant SDLC_Flag : DATA_TYPE := x"7E"; |
185,7 → 185,6
signal BClk_Div : std_logic := '0'; |
signal BClk_Okay_SR : std_logic_vector(3 downto 0) := (others => '0'); |
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signal BClk_SR : std_logic_vector(2 downto 0) := (others => '0'); |
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constant CLK_RATIO_R : real := Clock_Frequency / (1.0 * BitClock_Frequency); |