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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 284 to Rev 285
    ↔ Reverse comparison
  •

Rev 284 → Rev 285

/o8_vector_rx.vhd
41,6 → 41,7
-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
-- conditions instead
-- Seth Henry 05/23/20 Added the parallel interface
-- Seth Henry 04/07/21 Added checksum to prevent glitching on serial noise
 
library ieee;
use ieee.std_logic_1164.all;
107,7 → 108,11
signal Rx_Data : DATA_TYPE := x"00";
signal Rx_Valid : std_logic;
 
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
type VECTOR_RX_STATES is ( CHECKSUM_INIT,
GET_VECTOR_CMD,
GET_VECTOR_ARG_LB,
GET_VECTOR_ARG_UB,
GET_VECTOR_SUM,
SEND_INTERRUPT );
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
 
118,7 → 123,11
signal Vector_Data : ADDRESS_TYPE := x"0000";
alias Vector_Data_LB is Vector_Data(7 downto 0);
alias Vector_Data_UB is Vector_Data(15 downto 8);
signal Vector_RX_Sum : DATA_TYPE := x"00";
 
constant MAGIC_NUM : DATA_TYPE := x"4D";
signal Checksum : DATA_TYPE := x"00";
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
200,7 → 209,7
begin
if( Reset = Reset_Level )then
Vec_Req_SR <= (others => '0');
Vector_State <= GET_VECTOR_CMD;
Vector_State <= CHECKSUM_INIT;
Vector_Index <= x"00";
Vector_Data <= x"0000";
Interrupt <= '0';
216,8 → 225,13
end if;
 
case( Vector_State )is
when CHECKSUM_INIT =>
Checksum <= MAGIC_NUM;
Vector_State <= GET_VECTOR_CMD;
 
when GET_VECTOR_CMD =>
if( Rx_Valid = '1' )then
Checksum <= Checksum + Rx_Data;
Vector_Index <= "00" & Rx_Data(5 downto 0);
Vector_State <= GET_VECTOR_ARG_LB;
end if;
224,6 → 238,7
 
when GET_VECTOR_ARG_LB =>
if( Rx_Valid = '1' )then
Checksum <= Checksum + Rx_Data;
Vector_Data_LB <= Rx_Data;
Vector_State <= GET_VECTOR_ARG_UB;
end if;
230,18 → 245,27
 
when GET_VECTOR_ARG_UB =>
if( Rx_Valid = '1' )then
Checksum <= Checksum + Rx_Data;
Vector_Data_UB <= Rx_Data;
Vector_State <= GET_VECTOR_SUM;
end if;
 
when GET_VECTOR_SUM =>
if( Rx_Valid = '1' )then
Vector_RX_Sum <= Rx_Data;
Vector_State <= SEND_INTERRUPT;
end if;
 
when SEND_INTERRUPT =>
Interrupt <= '1';
Vector_State <= GET_VECTOR_CMD;
if( Checksum = Vector_RX_Sum )then
Interrupt <= '1';
end if;
Vector_State <= CHECKSUM_INIT;
when others => null;
end case;
 
if( Rx_Idle = '1' )then
Vector_State <= GET_VECTOR_CMD;
Vector_State <= CHECKSUM_INIT;
end if;
 
end if;
/vector_tx.vhd
30,6 → 30,8
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/06/20 Added version block
-- Seth Henry 04/07/21 Modified to replace hard-coded blocks with true
-- argument inputs.
 
library ieee;
use ieee.std_logic_1164.all;
37,6 → 39,9
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity vector_tx is
generic(
Button_Level : std_logic;
50,135 → 55,71
Clock : in std_logic;
Reset : in std_logic;
--
Switches : in std_logic_vector(9 downto 0);
Pushbutton : in std_logic;
Tx_Enable : in std_logic;
Tx_Command : in DATA_TYPE;
Tx_Arg_Lower : in DATA_TYPE;
Tx_Arg_Upper : in DATA_TYPE;
--
Tx_Out : out std_logic
Tx_Busy : out std_logic;
--
Tx_Out : out std_logic;
Tx_FC : in std_logic := '1'
);
end entity;
 
architecture behave of vector_tx is
 
signal uSec_Tick : std_logic;
signal mSec_Tick : std_logic;
signal Command_Buffer : DATA_TYPE := x"00";
signal Arg_Lower_Buffer : DATA_TYPE := x"00";
signal Arg_Upper_Buffer : DATA_TYPE := x"00";
 
signal Button_Pressed : std_logic := '0';
signal Button_CoS : std_logic := '0';
 
type VEC_ARG_TYPE is array(0 to 31) of std_logic_vector(15 downto 0);
constant VEC_ARGS : VEC_ARG_TYPE := (
x"0000",
x"0001",
x"0002",
x"0003",
x"0004",
x"0005",
x"0006",
x"0007",
x"0008",
x"0009",
x"000A",
x"000B",
x"000C",
x"000D",
x"000E",
x"000F",
 
x"0800",
x"0866",
x"0975",
x"00AE",
x"DEAD",
x"BEEF",
x"CAFE",
x"BABE",
x"DECA",
x"A5A5",
x"C3C3",
x"0123",
x"4567",
x"89AB",
x"CDEF",
x"FFFF"
);
 
alias Vector_Arg_Sel is Switches(9 downto 5);
alias Vector_Cmd_Sel is Switches(4 downto 0);
 
signal Vector_Cmd : std_logic_vector(7 downto 0);
 
signal Vector_Arg : std_logic_vector(15 downto 0);
alias Vector_Arg_LB is Vector_Arg(7 downto 0);
alias Vector_Arg_UB is Vector_Arg(15 downto 8);
 
type VECTOR_TX_STATES is (IDLE, SEND_CMD, WAIT_CMD, SEND_ARG_LB, WAIT_ARG_LB, SEND_ARG_UB, WAIT_ARG_UB );
type VECTOR_TX_STATES is (IDLE,
SEND_CMD, WAIT_CMD,
SEND_ARG_LB, WAIT_ARG_LB,
SEND_ARG_UB, WAIT_ARG_UB,
SEND_SUM, WAIT_SUM );
signal Vector_State : VECTOR_TX_STATES := IDLE;
 
constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
 
signal Tx_Data : std_logic_vector(7 downto 0) := x"00";
constant MAGIC_NUM : DATA_TYPE := x"4D";
signal Checksum : DATA_TYPE := x"00";
 
signal Tx_Data : DATA_TYPE := x"00";
signal Tx_Valid : std_logic := '0';
signal Tx_Done : std_logic := '0';
 
begin
 
U_USEC : entity work.sys_tick
generic map(
Reset_Level => Reset_Level,
Sys_Freq => Sys_Freq
)
port map(
Clock => Clock,
Reset => Reset,
uSec_Tick => uSec_Tick,
mSec_Tick => mSec_Tick
);
 
U_BTN : entity work.button_db
generic map(
Button_Level => Button_Level,
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
mSec_Tick => mSec_Tick,
--
Button_In => Pushbutton,
--
Button_Pressed => Button_Pressed,
Button_CoS => Button_CoS
);
 
Input_reg_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Vector_Cmd <= x"00";
Vector_Arg <= x"0000";
elsif( rising_edge(Clock) )then
Vector_Cmd <= "000" & Vector_Cmd_Sel;
Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));
end if;
end process;
 
TX_FSM_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Vector_State <= IDLE;
Command_Buffer <= x"00";
Arg_Lower_Buffer <= x"00";
Arg_Upper_Buffer <= x"00";
Tx_Busy <= '0';
Tx_Data <= x"00";
Tx_Valid <= '0';
elsif( rising_edge(Clock) )then
Tx_Busy <= '1';
Tx_Data <= x"00";
Tx_Valid <= '0';
case( Vector_State )is
when IDLE =>
if( Button_CoS = '1' and Button_Pressed = '1' )then
Tx_Busy <= '0';
Checksum <= MAGIC_NUM;
if( Tx_Enable = '1' )then
Command_Buffer <= Tx_Command;
Arg_Lower_Buffer <= Tx_Arg_Lower;
Arg_Upper_Buffer <= Tx_Arg_Upper;
Vector_State <= SEND_CMD;
end if;
 
when SEND_CMD =>
Tx_Data <= Vector_Cmd;
Tx_Data <= Command_Buffer;
Tx_Valid <= '1';
Checksum <= Checksum + Command_Buffer;
Vector_State <= WAIT_CMD;
 
when WAIT_CMD =>
187,8 → 128,9
end if;
 
when SEND_ARG_LB =>
Tx_Data <= Vector_Arg_LB;
Tx_Data <= Arg_Lower_Buffer;
Tx_Valid <= '1';
Checksum <= Checksum + Arg_Lower_Buffer;
Vector_State <= WAIT_ARG_LB;
 
when WAIT_ARG_LB =>
197,12 → 139,23
end if;
 
when SEND_ARG_UB =>
Tx_Data <= Vector_Arg_UB;
Tx_Data <= Arg_Upper_Buffer;
Tx_Valid <= '1';
Checksum <= Checksum + Arg_Upper_Buffer;
Vector_State <= WAIT_ARG_UB;
 
when WAIT_ARG_UB =>
if( Tx_Done = '1' )then
Vector_State <= SEND_SUM;
end if;
 
when SEND_SUM =>
Tx_Data <= Checksum;
Tx_Valid <= '1';
Vector_State <= WAIT_SUM;
 
when WAIT_SUM =>
if( Tx_Done = '1' )then
Vector_State <= IDLE;
end if;
 

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